2 * Common internal memory map for some Freescale SoCs
4 * Copyright 2014 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
15 #ifdef CONFIG_SYS_FSL_SEC_LE
16 #define sec_in32(a) in_le32(a)
17 #define sec_out32(a, v) out_le32(a, v)
18 #define sec_in16(a) in_le16(a)
19 #define sec_clrbits32 clrbits_le32
20 #define sec_setbits32 setbits_le32
21 #elif defined(CONFIG_SYS_FSL_SEC_BE)
22 #define sec_in32(a) in_be32(a)
23 #define sec_out32(a, v) out_be32(a, v)
24 #define sec_in16(a) in_be16(a)
25 #define sec_clrbits32 clrbits_be32
26 #define sec_setbits32 setbits_be32
27 #elif defined(CONFIG_SYS_FSL_HAS_SEC)
28 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
31 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
32 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
33 /* RNG4 TRNG test registers */
35 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
36 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
37 both entropy shifter and
38 statistical checker */
39 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
41 statistical checker */
42 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
43 entropy shifter, raw data
44 in statistical checker */
45 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
46 u32 rtmctl; /* misc. control register */
47 u32 rtscmisc; /* statistical check misc. register */
48 u32 rtpkrrng; /* poker range register */
49 #define RTSDCTL_ENT_DLY_MIN 3200
50 #define RTSDCTL_ENT_DLY_MAX 12800
52 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
53 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
55 #define RTSDCTL_ENT_DLY_SHIFT 16
56 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
57 u32 rtsdctl; /* seed control register */
59 u32 rtsblim; /* PRGM=1: sparse bit limit register */
60 u32 rttotsam; /* PRGM=0: total samples register */
62 u32 rtfreqmin; /* frequency count min. limit register */
63 #define RTFRQMAX_DISABLE (1 << 20)
65 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
66 u32 rtfreqcnt; /* PRGM=0: freq. count register */
69 #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
70 #define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
71 #define RNG_STATE_HANDLE_MASK \
72 (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
73 u32 rdsta; /*RNG DRNG Status Register*/
77 typedef struct ccsr_sec {
79 u32 mcfgr; /* Master CFG Register */
83 u32 ms; /* Job Ring LIODN Register, MS */
84 u32 ls; /* Job Ring LIODN Register, LS */
87 u32 jrstartr; /* Job Ring Start Register */
89 u32 ms; /* RTIC LIODN Register, MS */
90 u32 ls; /* RTIC LIODN Register, LS */
93 u32 decorr; /* DECO Request Register */
95 u32 ms; /* DECO LIODN Register, MS */
96 u32 ls; /* DECO LIODN Register, LS */
99 u32 dar; /* DECO Avail Register */
100 u32 drr; /* DECO Reset Register */
102 struct rng4tst rng; /* RNG Registers */
104 u32 crnr_ms; /* CHA Revision Number Register, MS */
105 u32 crnr_ls; /* CHA Revision Number Register, LS */
106 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
107 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
109 u32 far_ms; /* Fault Address Register, MS */
110 u32 far_ls; /* Fault Address Register, LS */
111 u32 falr; /* Fault Address LIODN Register */
112 u32 fadr; /* Fault Address Detail Register */
114 u32 csta; /* CAAM Status Register */
115 u32 smpart; /* Secure Memory Partition Parameters */
116 u32 smvid; /* Secure Memory Version ID */
117 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
118 u32 ccbvid; /* CHA Cluster Block Version ID Register */
119 u32 chavid_ms; /* CHA Version ID Register, MS */
120 u32 chavid_ls; /* CHA Version ID Register, LS */
121 u32 chanum_ms; /* CHA Number Register, MS */
122 u32 chanum_ls; /* CHA Number Register, LS */
123 u32 secvid_ms; /* SEC Version ID Register, MS */
124 u32 secvid_ls; /* SEC Version ID Register, LS */
126 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
127 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
131 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
132 #define SEC_CTPR_MS_QI 0x02000000
133 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
134 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
135 #define SEC_RVID_MA 0x0f000000
136 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
137 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
138 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
139 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
140 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
141 #define SEC_SECVID_MS_IPID_SHIFT 16
142 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
143 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
144 #define SEC_CCBVID_ERA_MASK 0xff000000
145 #define SEC_CCBVID_ERA_SHIFT 24
146 #define SEC_SCFGR_RDBENABLE 0x00000400
147 #define SEC_SCFGR_VIRT_EN 0x00008000
148 #define SEC_CHAVID_LS_RNG_SHIFT 16
149 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
151 #define CONFIG_JRSTARTR_JR0 0x00000001
154 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
155 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
168 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
169 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
197 * Scatter Gather Entry - Specifies the the Scatter Gather Format
198 * related information
201 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
202 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
203 uint32_t addr_lo; /* Memory Address - lo */
204 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
206 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
207 uint32_t addr_lo; /* Memory Address - lo */
210 uint32_t len_flag; /* Length of the data in the frame */
211 #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
212 #define SG_ENTRY_EXTENSION_BIT 0x80000000
213 #define SG_ENTRY_FINAL_BIT 0x40000000
214 uint32_t bpid_offset;
215 #define SG_ENTRY_BPID_MASK 0x00FF0000
216 #define SG_ENTRY_BPID_SHIFT 16
217 #define SG_ENTRY_OFFSET_MASK 0x00001FFF
218 #define SG_ENTRY_OFFSET_SHIFT 0
221 #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
223 #if defined(CONFIG_MX6) || defined(CONFIG_MX7)
224 /* Job Ring Base Address */
225 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
226 /* Secure Memory Offset varies accross versions */
227 #define SM_V1_OFFSET 0x0f4
228 #define SM_V2_OFFSET 0xa00
229 /*Secure Memory Versioning */
230 #define SMVID_V2 0x20105
231 #define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2)
232 #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
233 /* CAAM Job Ring 0 Registers */
234 /* Secure Memory Partition Owner register */
235 #define SMCSJR_PO (3 << 6)
236 /* JR Allocation Error */
237 #define SMCSJR_AERR (3 << 12)
238 /* Secure memory partition 0 page 0 owner register */
239 #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
240 /* Secure memory command register */
241 #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
242 /* Secure memory command status register */
243 #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
244 /* Secure memory access permissions register */
245 #define CAAM_SMAPJR(v, jr, y) \
246 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
247 /* Secure memory access group 2 register */
248 #define CAAM_SMAG2JR(v, jr, y) \
249 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
250 /* Secure memory access group 1 register */
251 #define CAAM_SMAG1JR(v, jr, y) \
252 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
254 /* Commands and macros for secure memory */
255 #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
256 #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
257 #define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
258 #define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8)
259 #define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC)
260 #define CMD_PAGE_ALLOC 0x1
261 #define CMD_PAGE_DEALLOC 0x2
262 #define CMD_PART_DEALLOC 0x3
263 #define CMD_INQUIRY 0x5
264 #define CMD_COMPLETE (3 << 14)
265 #define PAGE_AVAILABLE 0
266 #define PAGE_OWNED (3 << 6)
267 #define PAGE(x) (x << 16)
268 #define PARTITION(x) (x << 8)
269 #define PARTITION_OWNER(x) (0x3 << (x*2))
271 /* Address of secure 4kbyte pages */
272 #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
273 #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
274 #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
275 #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
277 #define JR_MID 2 /* Matches ROM configuration */
278 #define KS_G1 (1 << JR_MID) /* CAAM only */
279 #define PERM 0x0000B008 /* Clear on release, lock SMAP
280 * lock SMAG group 1 Blob */
282 /* HAB WRAPPED KEY header */
283 #define WRP_HDR_SIZE 0x08
286 /* HAB WRAPPED KEY Data */
291 /* Partition and Page IDs */
292 #define PARTITION_1 1
295 #define ERROR_IN_PAGE_ALLOC 1
296 #define ECONSTRJDESC -1
301 * Encapsulates the src in a secure blob and stores it dst
302 * @src: reference to the plaintext
303 * @dst: reference to the output adrress
304 * @len: size in bytes of src
305 * @return: 0 on success, error otherwise
307 int blob_dek(const u8 *src, u8 *dst, u8 len);
309 #if defined(CONFIG_ARCH_C29X)
310 int sec_init_idx(uint8_t);
315 #endif /* __FSL_SEC_H */