2 * Common internal memory map for some Freescale SoCs
4 * Copyright 2014 Freescale Semiconductor, Inc.
14 #ifdef CONFIG_SYS_FSL_SEC_LE
15 #define sec_in32(a) in_le32(a)
16 #define sec_out32(a, v) out_le32(a, v)
17 #define sec_in16(a) in_le16(a)
18 #define sec_clrbits32 clrbits_le32
19 #define sec_setbits32 setbits_le32
20 #elif defined(CONFIG_SYS_FSL_SEC_BE)
21 #define sec_in32(a) in_be32(a)
22 #define sec_out32(a, v) out_be32(a, v)
23 #define sec_in16(a) in_be16(a)
24 #define sec_clrbits32 clrbits_be32
25 #define sec_setbits32 setbits_be32
27 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
30 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
31 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
32 typedef struct ccsr_sec {
34 u32 mcfgr; /* Master CFG Register */
38 u32 ms; /* Job Ring LIODN Register, MS */
39 u32 ls; /* Job Ring LIODN Register, LS */
42 u32 jrstartr; /* Job Ring Start Register */
44 u32 ms; /* RTIC LIODN Register, MS */
45 u32 ls; /* RTIC LIODN Register, LS */
48 u32 decorr; /* DECO Request Register */
50 u32 ms; /* DECO LIODN Register, MS */
51 u32 ls; /* DECO LIODN Register, LS */
54 u32 dar; /* DECO Avail Register */
55 u32 drr; /* DECO Reset Register */
57 u32 crnr_ms; /* CHA Revision Number Register, MS */
58 u32 crnr_ls; /* CHA Revision Number Register, LS */
59 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
60 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
62 u32 far_ms; /* Fault Address Register, MS */
63 u32 far_ls; /* Fault Address Register, LS */
64 u32 falr; /* Fault Address LIODN Register */
65 u32 fadr; /* Fault Address Detail Register */
67 u32 csta; /* CAAM Status Register */
69 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
70 u32 ccbvid; /* CHA Cluster Block Version ID Register */
71 u32 chavid_ms; /* CHA Version ID Register, MS */
72 u32 chavid_ls; /* CHA Version ID Register, LS */
73 u32 chanum_ms; /* CHA Number Register, MS */
74 u32 chanum_ls; /* CHA Number Register, LS */
75 u32 secvid_ms; /* SEC Version ID Register, MS */
76 u32 secvid_ls; /* SEC Version ID Register, LS */
78 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
79 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
83 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
84 #define SEC_CTPR_MS_QI 0x02000000
85 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
86 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
87 #define SEC_RVID_MA 0x0f000000
88 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
89 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
90 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
91 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
92 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
93 #define SEC_SECVID_MS_IPID_SHIFT 16
94 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
95 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
96 #define SEC_CCBVID_ERA_MASK 0xff000000
97 #define SEC_CCBVID_ERA_SHIFT 24
98 #define SEC_SCFGR_RDBENABLE 0x00000400
99 #define SEC_SCFGR_VIRT_EN 0x00008000
100 #define SEC_CHAVID_LS_RNG_SHIFT 16
101 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
104 #endif /* __FSL_SEC_H */