1 /*****************************************************************************/
5 /* Gamate system specific definitions */
9 /* (w) 2015 Groepaz/Hitmen (groepaz@gmx.net) */
10 /* based on technical reference by PeT (mess@utanet.at) */
12 /* This software is provided 'as-is', without any expressed or implied */
13 /* warranty. In no event will the authors be held liable for any damages */
14 /* arising from the use of this software. */
16 /* Permission is granted to anyone to use this software for any purpose, */
17 /* including commercial applications, and to alter it and redistribute it */
18 /* freely, subject to the following restrictions: */
20 /* 1. The origin of this software must not be misrepresented; you must not */
21 /* claim that you wrote the original software. If you use this software */
22 /* in a product, an acknowledgment in the product documentation would be */
23 /* appreciated but is not required. */
24 /* 2. Altered source versions must be plainly marked as such, and must not */
25 /* be misrepresented as being the original software. */
26 /* 3. This notice may not be removed or altered from any source */
29 /*****************************************************************************/
34 /* Check for errors */
35 #if !defined(__GAMATE__)
36 # error This module may only be used when compiling for the Gamate!
39 #define AUDIO_BASE 0x4000
42 base clock cpu clock/32 ?
44 0/1: 1. channel(right): 12 bit frequency: right frequency 0 nothing, 1 high;
45 3 23khz; 4 17,3; 10 6,9; 15 4.6; $60 720hz; $eff 18,0; $fff 16,9 hz)
47 2/3: 2. channel(left): 12 bit frequency
48 4/5: 3. channel(both): 12 bit frequency
49 6: 0..5 noise frequency 0 fast 1f slow (about 500us) 15.6ns--> clock/32 counts
50 7 control (hinibble right)
51 bit 0: right channel high (full cycle, else square pulse/tone)
52 bit 1: left channel high
53 bit 2: both channel high
54 bit 3: set right tone (else noise)
55 bit 4: set left channel normal
56 bit 5: set both normal
57 bits 30: 11 high, 10 square, 01 noise, 00 noise only when square high
58 noise means switches channel to ad converter based noise algorithmen
59 (white noise shift register 17bit wide, repeats after about 130000 cycles)
60 probably out=!bit16, bit0=bit16 xor bit13; runs through, so start value anything than 0
61 8: 1st volume: 0..3 square volume; bit 4 envelope (higher priority)
64 11/12: envelope delay time 0 fast, 0xffff slow/nearly no effect (2 22us, 4 56us)
65 frequency $800, envelope $10 2 times in pulse high time (4*16*16)
71 a starts with down falling, rising; same falling time, but double/longer cycle
72 b one time falling, on
75 e rising, falling (double cycle before restart)
79 bit 2: start rising (else falling)
85 resolution 160x152 in 4 greys/greens
86 2 256x256 sized bitplanes (2x 8kbyte ram)
88 #define LCD_BASE 0x5000
90 #define LCD_MODE 0x5001
92 bit 3..0 (from zeropage 15)
93 bit 0 set no normal screen display, seldom scrolling effects on screen;
94 bytes written to somewhat actual display refresh position!?
97 bit 4 swaps plane intensity
98 bit 5 ? display effect
99 bit 6 on y auto increment (else auto x increment), reading
100 bit 7 ? lcd flickering
102 #define LCD_MODE_INC_Y 0x40
104 #define LCD_XPOS 0x5002 /* smooth scrolling X */
105 #define LCD_YPOS 0x5003 /* smooth scrolling Y */
107 smooth scrolling until $c8 with 200 limit
108 after 200 display if ((value & 0xf) < 8) display of (value & 0xf) - 8
109 chaos lines from value + current line from plane 2 only then lines starting
110 with zero (problematic 200 limit/overrun implementation!?)
112 #define LCD_X 0x5004 /* x-addr */
115 bit 7 0 1st/1 2nd bitplane
117 #define LCD_XPOS_PLANE1 0x00
118 #define LCD_XPOS_PLANE2 0x80
120 #define LCD_Y 0x5005 /* y-addr */
122 #define LCD_READ 0x5006 /* read from RAM (no auto inc?) */
123 #define LCD_DATA 0x5007 /* write to RAM */
125 /* BIOS zeropage usage */
127 /* locations 0x0a-0x0c, 0x0e-0x11 and 0xe8 are in use by the BIOS IRQ/NMI handlers */
128 #define ZP_NMI_4800 0x0a /* content of I/O reg 4800 gets copied here each NMI */
130 #define ZP_IRQ_COUNT 0x0b /* increments once per IRQ, used elsewhere in the
131 BIOS for synchronisation purposes */
132 #define ZP_IRQ_CTRL 0x0c /* if 0 then cartridge irq stubs will not get called */
134 /* each of the following 4 increments by 1 per IRQ - it is _not_ a 32bit
135 counter (see code at $ffa6 in BIOS)
136 these are not used elsewhere in the bios and can be (re)set as needed by
139 #define ZP_IRQ_CNT1 0x0e
140 #define ZP_IRQ_CNT2 0x0f
141 #define ZP_IRQ_CNT3 0x10
142 #define ZP_IRQ_CNT4 0x11
144 #define ZP_NMI_FLAG 0xe8 /* set to 0xff each NMI */
146 /* constants for the conio implementation */
147 #define COLOR_BLACK 0x03
148 #define COLOR_WHITE 0x00
153 #define CH_ULCORNER 4
154 #define CH_URCORNER 5
155 #define CH_LLCORNER 6
156 #define CH_LRCORNER 7
170 /* No support for dynamically loadable drivers */
173 /* Masks for joy_read */
174 #define JOY_UP_MASK 0x01
175 #define JOY_DOWN_MASK 0x02
176 #define JOY_LEFT_MASK 0x04
177 #define JOY_RIGHT_MASK 0x08
178 #define JOY_BTN_1_MASK 0x10
179 #define JOY_BTN_2_MASK 0x20
180 #define JOY_BTN_3_MASK 0x40
181 #define JOY_BTN_4_MASK 0x80
183 #define JOY_BTN_A_MASK JOY_BTN_1_MASK
184 #define JOY_BTN_B_MASk JOY_BTN_2_MASK
185 #define JOY_START_MASK JOY_BTN_3_MASK
186 #define JOY_SELECT_MASK JOY_BTN_4_MASK
188 #define JOY_BTN_A(v) ((v) & JOY_BTN_A_MASK)
189 #define JOY_BTN_B(v) ((v) & JOY_BTN_B_MASK)
190 #define JOY_START(v) ((v) & JOY_START_MASK)
191 #define JOY_SELECT(v) ((v) & JOY_SELECT_MASK)
193 /* The addresses of the static drivers */
194 extern void gamate_stdjoy_joy[]; /* Referred to by joy_static_stddrv[] */
196 void waitvsync (void);
197 /* Wait for start of next frame */
199 /* NOTE: all Gamate are "NTSC" */
200 #define get_tv() TV_NTSC
201 /* Return the video mode the machine is using. */
203 /* End of gamate.h */