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1 /*
2  * (C) Copyright 2010
3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #ifndef __GDSYS_FPGA_H
9 #define __GDSYS_FPGA_H
10
11 int init_func_fpga(void);
12
13 enum {
14         FPGA_STATE_DONE_FAILED = 1 << 0,
15         FPGA_STATE_REFLECTION_FAILED = 1 << 1,
16         FPGA_STATE_PLATFORM = 1 << 2,
17 };
18
19 int get_fpga_state(unsigned dev);
20 void print_fpga_state(unsigned dev);
21
22 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
23 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
24
25 extern struct ihs_fpga *fpga_ptr[];
26
27 #define FPGA_SET_REG(ix, fld, val) \
28         fpga_set_reg((ix), \
29                      &fpga_ptr[ix]->fld, \
30                      offsetof(struct ihs_fpga, fld), \
31                      val)
32
33 #define FPGA_GET_REG(ix, fld, val) \
34         fpga_get_reg((ix), \
35                      &fpga_ptr[ix]->fld, \
36                      offsetof(struct ihs_fpga, fld), \
37                      val)
38
39 struct ihs_gpio {
40         u16 read;
41         u16 clear;
42         u16 set;
43 };
44
45 struct ihs_i2c {
46         u16 interrupt_status;
47         u16 interrupt_enable;
48         u16 write_mailbox_ext;
49         u16 write_mailbox;
50         u16 read_mailbox_ext;
51         u16 read_mailbox;
52 };
53
54 struct ihs_osd {
55         u16 version;
56         u16 features;
57         u16 control;
58         u16 xy_size;
59         u16 xy_scale;
60         u16 x_pos;
61         u16 y_pos;
62 };
63
64 struct ihs_mdio {
65         u16 control;
66         u16 address_data;
67         u16 rx_data;
68 };
69
70 struct ihs_io_ep {
71         u16 transmit_data;
72         u16 rx_tx_control;
73         u16 receive_data;
74         u16 rx_tx_status;
75         u16 reserved;
76         u16 device_address;
77         u16 target_address;
78 };
79
80 #ifdef CONFIG_NEO
81 struct ihs_fpga {
82         u16 reflection_low;     /* 0x0000 */
83         u16 versions;           /* 0x0002 */
84         u16 fpga_features;      /* 0x0004 */
85         u16 fpga_version;       /* 0x0006 */
86         u16 reserved_0[8187];   /* 0x0008 */
87         u16 reflection_high;    /* 0x3ffe */
88 };
89 #endif
90
91 #ifdef CONFIG_IO
92 struct ihs_fpga {
93         u16 reflection_low;     /* 0x0000 */
94         u16 versions;           /* 0x0002 */
95         u16 fpga_features;      /* 0x0004 */
96         u16 fpga_version;       /* 0x0006 */
97         u16 reserved_0[5];      /* 0x0008 */
98         u16 quad_serdes_reset;  /* 0x0012 */
99         u16 reserved_1[8181];   /* 0x0014 */
100         u16 reflection_high;    /* 0x3ffe */
101 };
102 #endif
103
104 #ifdef CONFIG_IO64
105 struct ihs_fpga_channel {
106         u16 status_int;
107         u16 config_int;
108         u16 switch_connect_config;
109         u16 tx_destination;
110 };
111
112 struct ihs_fpga_hicb {
113         u16 status_int;
114         u16 config_int;
115 };
116
117 struct ihs_fpga {
118         u16 reflection_low;     /* 0x0000 */
119         u16 versions;           /* 0x0002 */
120         u16 fpga_features;      /* 0x0004 */
121         u16 fpga_version;       /* 0x0006 */
122         u16 reserved_0[5];      /* 0x0008 */
123         u16 quad_serdes_reset;  /* 0x0012 */
124         u16 reserved_1[502];    /* 0x0014 */
125         struct ihs_fpga_channel ch[32];         /* 0x0400 */
126         struct ihs_fpga_channel hicb_ch[32];    /* 0x0500 */
127         u16 reserved_2[7487];   /* 0x0580 */
128         u16 reflection_high;    /* 0x3ffe */
129 };
130 #endif
131
132 #ifdef CONFIG_IOCON
133 struct ihs_fpga {
134         u16 reflection_low;     /* 0x0000 */
135         u16 versions;           /* 0x0002 */
136         u16 fpga_version;       /* 0x0004 */
137         u16 fpga_features;      /* 0x0006 */
138         u16 reserved_0[1];      /* 0x0008 */
139         u16 top_interrupt;      /* 0x000a */
140         u16 reserved_1[4];      /* 0x000c */
141         struct ihs_gpio gpio;   /* 0x0014 */
142         u16 mpc3w_control;      /* 0x001a */
143         u16 reserved_2[2];      /* 0x001c */
144         struct ihs_io_ep ep;    /* 0x0020 */
145         u16 reserved_3[9];      /* 0x002e */
146         struct ihs_i2c i2c;     /* 0x0040 */
147         u16 reserved_4[10];     /* 0x004c */
148         u16 mc_int;             /* 0x0060 */
149         u16 mc_int_en;          /* 0x0062 */
150         u16 mc_status;          /* 0x0064 */
151         u16 mc_control;         /* 0x0066 */
152         u16 mc_tx_data;         /* 0x0068 */
153         u16 mc_tx_address;      /* 0x006a */
154         u16 mc_tx_cmd;          /* 0x006c */
155         u16 mc_res;             /* 0x006e */
156         u16 mc_rx_cmd_status;   /* 0x0070 */
157         u16 mc_rx_data;         /* 0x0072 */
158         u16 reserved_5[69];     /* 0x0074 */
159         u16 reflection_high;    /* 0x00fe */
160         struct ihs_osd osd;     /* 0x0100 */
161         u16 reserved_6[889];    /* 0x010e */
162         u16 videomem[31736];    /* 0x0800 */
163 };
164 #endif
165
166 #ifdef CONFIG_HRCON
167 struct ihs_fpga {
168         u16 reflection_low;     /* 0x0000 */
169         u16 versions;           /* 0x0002 */
170         u16 fpga_version;       /* 0x0004 */
171         u16 fpga_features;      /* 0x0006 */
172         u16 reserved_0[1];      /* 0x0008 */
173         u16 top_interrupt;      /* 0x000a */
174         u16 reserved_1[4];      /* 0x000c */
175         struct ihs_gpio gpio;   /* 0x0014 */
176         u16 mpc3w_control;      /* 0x001a */
177         u16 reserved_2[2];      /* 0x001c */
178         struct ihs_io_ep ep;    /* 0x0020 */
179         u16 reserved_3[9];      /* 0x002e */
180         struct ihs_i2c i2c;     /* 0x0040 */
181         u16 reserved_4[10];     /* 0x004c */
182         u16 mc_int;             /* 0x0060 */
183         u16 mc_int_en;          /* 0x0062 */
184         u16 mc_status;          /* 0x0064 */
185         u16 mc_control;         /* 0x0066 */
186         u16 mc_tx_data;         /* 0x0068 */
187         u16 mc_tx_address;      /* 0x006a */
188         u16 mc_tx_cmd;          /* 0x006c */
189         u16 mc_res;             /* 0x006e */
190         u16 mc_rx_cmd_status;   /* 0x0070 */
191         u16 mc_rx_data;         /* 0x0072 */
192         u16 reserved_5[69];     /* 0x0074 */
193         u16 reflection_high;    /* 0x00fe */
194         struct ihs_osd osd;     /* 0x0100 */
195         u16 reserved_6[889];    /* 0x010e */
196         u16 videomem[31736];    /* 0x0800 */
197 };
198 #endif
199
200 #ifdef CONFIG_DLVISION_10G
201 struct ihs_fpga {
202         u16 reflection_low;     /* 0x0000 */
203         u16 versions;           /* 0x0002 */
204         u16 fpga_version;       /* 0x0004 */
205         u16 fpga_features;      /* 0x0006 */
206         u16 reserved_0[10];     /* 0x0008 */
207         u16 extended_interrupt; /* 0x001c */
208         u16 reserved_1[29];     /* 0x001e */
209         u16 mpc3w_control;      /* 0x0058 */
210         u16 reserved_2[3];      /* 0x005a */
211         struct ihs_i2c i2c;     /* 0x0060 */
212         u16 reserved_3[205];    /* 0x0066 */
213         struct ihs_osd osd;     /* 0x0200 */
214         u16 reserved_4[761];    /* 0x020e */
215         u16 videomem[31736];    /* 0x0800 */
216 };
217 #endif
218
219 #endif