3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
12 #define MAX_PLUGIN_CODE_SIZE (64 * 1024)
13 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
14 #define APP_CODE_BARKER 0xB1
15 #define DCD_BARKER 0xB17219E9
18 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
19 * mach-imx/imximage.cfg because tools/imximage.c can not
20 * cross-include headers from arch/arm/ and vice-versa.
22 #define CMD_DATA_STR "DATA"
24 /* Initial Vector Table Offset */
25 #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
26 #define FLASH_OFFSET_STANDARD 0x400
27 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
28 #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
29 #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
30 #define FLASH_OFFSET_ONENAND 0x100
31 #define FLASH_OFFSET_NOR 0x1000
32 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
33 #define FLASH_OFFSET_QSPI 0x1000
35 /* Initial Load Region Size */
36 #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
37 #define FLASH_LOADSIZE_STANDARD 0x1000
38 #define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
39 #define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
40 #define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
41 #define FLASH_LOADSIZE_ONENAND 0x400
42 #define FLASH_LOADSIZE_NOR 0x0 /* entire image */
43 #define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
44 #define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
46 /* Command tags and parameters */
47 #define IVT_HEADER_TAG 0xD1
48 #define IVT_VERSION 0x40
49 #define DCD_HEADER_TAG 0xD2
50 #define DCD_VERSION 0x40
51 #define DCD_WRITE_DATA_COMMAND_TAG 0xCC
52 #define DCD_WRITE_DATA_PARAM 0x4
53 #define DCD_WRITE_CLR_BIT_PARAM 0xC
54 #define DCD_WRITE_SET_BIT_PARAM 0x1C
55 #define DCD_CHECK_DATA_COMMAND_TAG 0xCF
56 #define DCD_CHECK_BITS_SET_PARAM 0x14
57 #define DCD_CHECK_BITS_CLR_PARAM 0x04
73 enum imximage_fld_types {
81 enum imximage_version {
82 IMXIMAGE_VER_INVALID = -1,
88 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
89 uint32_t addr; /* Address to write to */
90 uint32_t value; /* Data to write */
91 } dcd_type_addr_data_t;
94 uint32_t barker; /* Barker for sanity check */
95 uint32_t length; /* Device configuration length (without preamble) */
99 dcd_preamble_t preamble;
100 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
104 uint32_t app_code_jump_vector;
105 uint32_t app_code_barker;
106 uint32_t app_code_csf;
107 uint32_t dcd_ptr_ptr;
108 uint32_t super_root_key;
110 uint32_t app_dest_ptr;
114 uint32_t length; /* Length of data to be read from flash */
118 flash_header_v1_t fhdr;
120 flash_cfg_parms_t ext_header;
132 } __attribute__((packed)) ivt_header_t;
138 } __attribute__((packed)) write_dcd_command_t;
141 write_dcd_command_t write_dcd_command;
142 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
147 struct dcd_v2_cmd dcd_cmd;
148 uint32_t padding[1]; /* end up on an 8-byte boundary */
162 uint32_t boot_data_ptr;
169 flash_header_v2_t fhdr;
170 boot_data_t boot_data;
173 char plugin_code[MAX_PLUGIN_CODE_SIZE];
177 /* The header must be aligned to 4k on MX53 for NAND boot */
180 imx_header_v1_t hdr_v1;
181 imx_header_v2_t hdr_v2;
185 typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
186 char *name, int lineno,
187 int fld, uint32_t value,
190 typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len,
193 typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
195 char *name, int lineno);
197 typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
198 uint32_t entry_point, uint32_t flash_offset);
200 #endif /* _IMXIMAGE_H_ */