2 * definitions for MPC8xxx I/O Ports
4 * Murray.Jensen@cmst.csiro.au, 20-Oct-00
8 * this structure mirrors the layout of the five port registers in
9 * the internal memory map
12 unsigned int pdir; /* Port Data Direction Register (35-3) */
13 unsigned int ppar; /* Port Pin Assignment Register (35-4) */
14 unsigned int psor; /* Port Special Options Register (35-5) */
15 unsigned int podr; /* Port Open Drain Register (35-2) */
16 unsigned int pdat; /* Port Data Register (35-3) */
20 * this macro calculates the address within the internal
21 * memory map (im) of the set of registers for a port (idx)
23 * the internal memory map aligns the above structure on
24 * a 0x20 byte boundary
27 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
29 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
33 * this structure provides configuration
34 * information for one port pin
37 unsigned char conf:1; /* if 1, configure this port */
38 unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */
39 unsigned char psor:1; /* Port Special Options Register (35-2) */
40 unsigned char pdir:1; /* Port Data Direction Register (35-3) */
41 unsigned char podr:1; /* Port Open Drain Register (35-2) */
42 unsigned char pdat:1; /* Port Data Register (35-2) */
46 * a table that contains configuration information for all 32 pins
48 * NOTE: in the second dimension of this table, index 0 refers to pin 31
49 * and index 31 refers to pin 0. this made the code in the table look more
50 * like the table in the 8260UM (and in the hymod manuals).
52 extern const iop_conf_t iop_conf_tab[4][32];
62 #define QE_IOP_TAB_END (-1)