3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __FSMC_NAND_H__
9 #define __FSMC_NAND_H__
11 #include <linux/mtd/nand.h>
15 u8 reserved_1[0x40 - 0x04];
19 u32 attrib; /* 0x4c */
24 u8 reserved_2[0xfe0 - 0x60];
25 u32 peripid0; /* 0xfe0 */
26 u32 peripid1; /* 0xfe4 */
27 u32 peripid2; /* 0xfe8 */
28 u32 peripid3; /* 0xfec */
29 u32 pcellid0; /* 0xff0 */
30 u32 pcellid1; /* 0xff4 */
31 u32 pcellid2; /* 0xff8 */
32 u32 pcellid3; /* 0xffc */
35 /* ctrl register definitions */
36 #define FSMC_WP (1 << 7)
38 /* pc register definitions */
39 #define FSMC_RESET (1 << 0)
40 #define FSMC_WAITON (1 << 1)
41 #define FSMC_ENABLE (1 << 2)
42 #define FSMC_DEVTYPE_NAND (1 << 3)
43 #define FSMC_DEVWID_8 (0 << 4)
44 #define FSMC_DEVWID_16 (1 << 4)
45 #define FSMC_ECCEN (1 << 6)
46 #define FSMC_ECCPLEN_512 (0 << 7)
47 #define FSMC_ECCPLEN_256 (1 << 7)
48 #define FSMC_TCLR_1 (1 << 9)
49 #define FSMC_TAR_1 (1 << 13)
51 /* sts register definitions */
52 #define FSMC_CODE_RDY (1 << 15)
54 /* comm register definitions */
55 #define FSMC_TSET_0 (0 << 0)
56 #define FSMC_TWAIT_6 (6 << 8)
57 #define FSMC_THOLD_4 (4 << 16)
58 #define FSMC_THIZ_1 (1 << 24)
60 /* peripid2 register definitions */
61 #define FSMC_REVISION_MSK (0xf)
62 #define FSMC_REVISION_SHFT (0x4)
67 * There are 13 bytes of ecc for every 512 byte block and it has to be read
68 * consecutively and immediately after the 512 byte data block for hardware to
69 * generate the error bit offsets
70 * Managing the ecc bytes in the following way is easier. This way is similar to
71 * oobfree structure maintained already in u-boot nand driver
73 #define FSMC_MAX_ECCPLACE_ENTRIES 32
75 struct fsmc_nand_eccplace {
80 struct fsmc_eccplace {
81 struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
84 extern int fsmc_nand_init(struct nand_chip *nand);