2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
11 * Contains standard defines and IDs for NAND flash devices
16 #ifndef __LINUX_MTD_NAND_H
17 #define __LINUX_MTD_NAND_H
21 #include <linux/compat.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/flashchip.h>
24 #include <linux/mtd/bbm.h>
27 struct nand_flash_dev;
30 /* Scan and identify a NAND device */
31 int nand_scan(struct mtd_info *mtd, int max_chips);
33 * Separate phases of nand_scan(), allowing board driver to intervene
34 * and override command or ECC setup according to flash type.
36 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
37 struct nand_flash_dev *table);
38 int nand_scan_tail(struct mtd_info *mtd);
40 /* Free resources held by the NAND device */
41 void nand_release(struct mtd_info *mtd);
43 /* Internal helper for board drivers which need to override command function */
44 void nand_wait_ready(struct mtd_info *mtd);
47 * This constant declares the max. oobsize / page, which
48 * is supported now. If you add a chip with bigger oobsize/page
49 * adjust this accordingly.
51 #define NAND_MAX_OOBSIZE 1664
52 #define NAND_MAX_PAGESIZE 16384
55 * Constants for hardware specific CLE/ALE/NCE function
57 * These are bits which can be or'ed to set/clear multiple
60 /* Select the chip by setting nCE to low */
62 /* Select the command latch by setting CLE to high */
64 /* Select the address latch by setting ALE to high */
67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
69 #define NAND_CTRL_CHANGE 0x80
72 * Standard NAND flash commands
74 #define NAND_CMD_READ0 0
75 #define NAND_CMD_READ1 1
76 #define NAND_CMD_RNDOUT 5
77 #define NAND_CMD_PAGEPROG 0x10
78 #define NAND_CMD_READOOB 0x50
79 #define NAND_CMD_ERASE1 0x60
80 #define NAND_CMD_STATUS 0x70
81 #define NAND_CMD_SEQIN 0x80
82 #define NAND_CMD_RNDIN 0x85
83 #define NAND_CMD_READID 0x90
84 #define NAND_CMD_ERASE2 0xd0
85 #define NAND_CMD_PARAM 0xec
86 #define NAND_CMD_GET_FEATURES 0xee
87 #define NAND_CMD_SET_FEATURES 0xef
88 #define NAND_CMD_RESET 0xff
90 #define NAND_CMD_LOCK 0x2a
91 #define NAND_CMD_UNLOCK1 0x23
92 #define NAND_CMD_UNLOCK2 0x24
94 /* Extended commands for large page devices */
95 #define NAND_CMD_READSTART 0x30
96 #define NAND_CMD_RNDOUTSTART 0xE0
97 #define NAND_CMD_CACHEDPROG 0x15
99 /* Extended commands for AG-AND device */
101 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
102 * there is no way to distinguish that from NAND_CMD_READ0
103 * until the remaining sequence of commands has been completed
104 * so add a high order bit and mask it off in the command.
106 #define NAND_CMD_DEPLETE1 0x100
107 #define NAND_CMD_DEPLETE2 0x38
108 #define NAND_CMD_STATUS_MULTI 0x71
109 #define NAND_CMD_STATUS_ERROR 0x72
110 /* multi-bank error status (banks 0-3) */
111 #define NAND_CMD_STATUS_ERROR0 0x73
112 #define NAND_CMD_STATUS_ERROR1 0x74
113 #define NAND_CMD_STATUS_ERROR2 0x75
114 #define NAND_CMD_STATUS_ERROR3 0x76
115 #define NAND_CMD_STATUS_RESET 0x7f
116 #define NAND_CMD_STATUS_CLEAR 0xff
118 #define NAND_CMD_NONE -1
121 #define NAND_STATUS_FAIL 0x01
122 #define NAND_STATUS_FAIL_N1 0x02
123 #define NAND_STATUS_TRUE_READY 0x20
124 #define NAND_STATUS_READY 0x40
125 #define NAND_STATUS_WP 0x80
127 #define NAND_DATA_IFACE_CHECK_ONLY -1
130 * Constants for ECC_MODES
136 NAND_ECC_HW_SYNDROME,
137 NAND_ECC_HW_OOB_FIRST,
142 * Constants for Hardware ECC
144 /* Reset Hardware ECC for read */
145 #define NAND_ECC_READ 0
146 /* Reset Hardware ECC for write */
147 #define NAND_ECC_WRITE 1
148 /* Enable Hardware ECC before syndrome is read back from flash */
149 #define NAND_ECC_READSYN 2
152 * Enable generic NAND 'page erased' check. This check is only done when
153 * ecc.correct() returns -EBADMSG.
154 * Set this flag if your implementation does not fix bitflips in erased
155 * pages and you want to rely on the default implementation.
157 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
158 #define NAND_ECC_MAXIMIZE BIT(1)
160 * If your controller already sends the required NAND commands when
161 * reading or writing a page, then the framework is not supposed to
162 * send READ0 and SEQIN/PAGEPROG respectively.
164 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
166 /* Bit mask for flags passed to do_nand_read_ecc */
167 #define NAND_GET_DEVICE 0x80
171 * Option constants for bizarre disfunctionality and real
174 /* Buswidth is 16 bit */
175 #define NAND_BUSWIDTH_16 0x00000002
176 /* Device supports partial programming without padding */
177 #define NAND_NO_PADDING 0x00000004
178 /* Chip has cache program function */
179 #define NAND_CACHEPRG 0x00000008
180 /* Chip has copy back function */
181 #define NAND_COPYBACK 0x00000010
183 * Chip requires ready check on read (for auto-incremented sequential read).
184 * True only for small page devices; large page devices do not support
187 #define NAND_NEED_READRDY 0x00000100
189 /* Chip does not allow subpage writes */
190 #define NAND_NO_SUBPAGE_WRITE 0x00000200
192 /* Device is one of 'new' xD cards that expose fake nand command set */
193 #define NAND_BROKEN_XD 0x00000400
195 /* Device behaves just like nand, but is readonly */
196 #define NAND_ROM 0x00000800
198 /* Device supports subpage reads */
199 #define NAND_SUBPAGE_READ 0x00001000
202 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
205 #define NAND_NEED_SCRAMBLING 0x00002000
207 /* Options valid for Samsung large page devices */
208 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
210 /* Macros to identify the above */
211 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
212 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
213 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
215 /* Non chip related options */
216 /* This option skips the bbt scan during initialization. */
217 #define NAND_SKIP_BBTSCAN 0x00010000
219 * This option is defined if the board driver allocates its own buffers
220 * (e.g. because it needs them DMA-coherent).
222 #define NAND_OWN_BUFFERS 0x00020000
223 /* Chip may not exist, so silence any errors in scan */
224 #define NAND_SCAN_SILENT_NODEV 0x00040000
226 * Autodetect nand buswidth with readid/onfi.
227 * This suppose the driver will configure the hardware in 8 bits mode
228 * when calling nand_scan_ident, and update its configuration
229 * before calling nand_scan_tail.
231 #define NAND_BUSWIDTH_AUTO 0x00080000
233 * This option could be defined by controller drivers to protect against
234 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
236 #define NAND_USE_BOUNCE_BUFFER 0x00100000
238 /* Options set by nand scan */
239 /* bbt has already been read */
240 #define NAND_BBT_SCANNED 0x40000000
241 /* Nand scan has allocated controller struct */
242 #define NAND_CONTROLLER_ALLOC 0x80000000
244 /* Cell info constants */
245 #define NAND_CI_CHIPNR_MSK 0x03
246 #define NAND_CI_CELLTYPE_MSK 0x0C
247 #define NAND_CI_CELLTYPE_SHIFT 2
253 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
254 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
256 /* ONFI timing mode, used in both asynchronous and synchronous mode */
257 #define ONFI_TIMING_MODE_0 (1 << 0)
258 #define ONFI_TIMING_MODE_1 (1 << 1)
259 #define ONFI_TIMING_MODE_2 (1 << 2)
260 #define ONFI_TIMING_MODE_3 (1 << 3)
261 #define ONFI_TIMING_MODE_4 (1 << 4)
262 #define ONFI_TIMING_MODE_5 (1 << 5)
263 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
265 /* ONFI feature address */
266 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
268 /* Vendor-specific feature address (Micron) */
269 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
271 /* ONFI subfeature parameters length */
272 #define ONFI_SUBFEATURE_PARAM_LEN 4
274 /* ONFI optional commands SET/GET FEATURES supported? */
275 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
277 struct nand_onfi_params {
278 /* rev info and features block */
279 /* 'O' 'N' 'F' 'I' */
285 __le16 ext_param_page_length; /* since ONFI 2.1 */
286 u8 num_of_param_pages; /* since ONFI 2.1 */
289 /* manufacturer information block */
290 char manufacturer[12];
296 /* memory organization block */
297 __le32 byte_per_page;
298 __le16 spare_bytes_per_page;
299 __le32 data_bytes_per_ppage;
300 __le16 spare_bytes_per_ppage;
301 __le32 pages_per_block;
302 __le32 blocks_per_lun;
307 __le16 block_endurance;
308 u8 guaranteed_good_blocks;
309 __le16 guaranteed_block_endurance;
310 u8 programs_per_page;
317 /* electrical parameter block */
318 u8 io_pin_capacitance_max;
319 __le16 async_timing_mode;
320 __le16 program_cache_timing_mode;
325 __le16 src_sync_timing_mode;
326 u8 src_ssync_features;
327 __le16 clk_pin_capacitance_typ;
328 __le16 io_pin_capacitance_typ;
329 __le16 input_pin_capacitance_typ;
330 u8 input_pin_capacitance_max;
331 u8 driver_strength_support;
337 __le16 vendor_revision;
343 #define ONFI_CRC_BASE 0x4F4E
345 /* Extended ECC information Block Definition (since ONFI 2.1) */
346 struct onfi_ext_ecc_info {
350 __le16 block_endurance;
354 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
355 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
356 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
357 struct onfi_ext_section {
362 #define ONFI_EXT_SECTION_MAX 8
364 /* Extended Parameter Page Definition (since ONFI 2.1) */
365 struct onfi_ext_param_page {
367 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
369 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
372 * The actual size of the Extended Parameter Page is in
373 * @ext_param_page_length of nand_onfi_params{}.
374 * The following are the variable length sections.
375 * So we do not add any fields below. Please see the ONFI spec.
379 struct nand_onfi_vendor_micron {
384 u8 dq_imped_num_settings;
385 u8 dq_imped_feat_addr;
386 u8 rb_pulldown_strength;
387 u8 rb_pulldown_strength_feat_addr;
388 u8 rb_pulldown_strength_num_settings;
391 u8 otp_data_prot_addr;
394 u8 read_retry_options;
399 struct jedec_ecc_info {
403 __le16 block_endurance;
408 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
410 struct nand_jedec_params {
411 /* rev info and features block */
412 /* 'J' 'E' 'S' 'D' */
418 u8 num_of_param_pages;
421 /* manufacturer information block */
422 char manufacturer[12];
427 /* memory organization block */
428 __le32 byte_per_page;
429 __le16 spare_bytes_per_page;
431 __le32 pages_per_block;
432 __le32 blocks_per_lun;
436 u8 programs_per_page;
438 u8 multi_plane_op_attr;
441 /* electrical parameter block */
442 __le16 async_sdr_speed_grade;
443 __le16 toggle_ddr_speed_grade;
444 __le16 sync_ddr_speed_grade;
445 u8 async_sdr_features;
446 u8 toggle_ddr_features;
447 u8 sync_ddr_features;
451 __le16 t_r_multi_plane;
453 __le16 io_pin_capacitance_typ;
454 __le16 input_pin_capacitance_typ;
455 __le16 clk_pin_capacitance_typ;
456 u8 driver_strength_support;
460 /* ECC and endurance block */
461 u8 guaranteed_good_blocks;
462 __le16 guaranteed_block_endurance;
463 struct jedec_ecc_info ecc_info[4];
470 __le16 vendor_rev_num;
473 /* CRC for Parameter Page */
478 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
479 * @lock: protection lock
480 * @active: the mtd device which holds the controller currently
481 * @wq: wait queue to sleep on if a NAND operation is in
482 * progress used instead of the per chip wait queue
483 * when a hw controller is available.
485 struct nand_hw_control {
487 struct nand_chip *active;
491 * struct nand_ecc_step_info - ECC step information of ECC engine
492 * @stepsize: data bytes per ECC step
493 * @strengths: array of supported strengths
494 * @nstrengths: number of supported strengths
496 struct nand_ecc_step_info {
498 const int *strengths;
503 * struct nand_ecc_caps - capability of ECC engine
504 * @stepinfos: array of ECC step information
505 * @nstepinfos: number of ECC step information
506 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
508 struct nand_ecc_caps {
509 const struct nand_ecc_step_info *stepinfos;
511 int (*calc_ecc_bytes)(int step_size, int strength);
514 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
515 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
516 static const int __name##_strengths[] = { __VA_ARGS__ }; \
517 static const struct nand_ecc_step_info __name##_stepinfo = { \
518 .stepsize = __step, \
519 .strengths = __name##_strengths, \
520 .nstrengths = ARRAY_SIZE(__name##_strengths), \
522 static const struct nand_ecc_caps __name = { \
523 .stepinfos = &__name##_stepinfo, \
525 .calc_ecc_bytes = __calc, \
529 * struct nand_ecc_ctrl - Control structure for ECC
531 * @steps: number of ECC steps per page
532 * @size: data bytes per ECC step
533 * @bytes: ECC bytes per step
534 * @strength: max number of correctible bits per ECC step
535 * @total: total number of ECC bytes per page
536 * @prepad: padding information for syndrome based ECC generators
537 * @postpad: padding information for syndrome based ECC generators
538 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
539 * @layout: ECC layout control struct pointer
540 * @priv: pointer to private ECC control data
541 * @hwctl: function to control hardware ECC generator. Must only
542 * be provided if an hardware ECC is available
543 * @calculate: function for ECC calculation or readback from ECC hardware
544 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
545 * Should return a positive number representing the number of
546 * corrected bitflips, -EBADMSG if the number of bitflips exceed
547 * ECC strength, or any other error code if the error is not
548 * directly related to correction.
549 * If -EBADMSG is returned the input buffers should be left
551 * @read_page_raw: function to read a raw page without ECC. This function
552 * should hide the specific layout used by the ECC
553 * controller and always return contiguous in-band and
554 * out-of-band data even if they're not stored
555 * contiguously on the NAND chip (e.g.
556 * NAND_ECC_HW_SYNDROME interleaves in-band and
558 * @write_page_raw: function to write a raw page without ECC. This function
559 * should hide the specific layout used by the ECC
560 * controller and consider the passed data as contiguous
561 * in-band and out-of-band data. ECC controller is
562 * responsible for doing the appropriate transformations
563 * to adapt to its specific layout (e.g.
564 * NAND_ECC_HW_SYNDROME interleaves in-band and
566 * @read_page: function to read a page according to the ECC generator
567 * requirements; returns maximum number of bitflips corrected in
568 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
569 * @read_subpage: function to read parts of the page covered by ECC;
570 * returns same as read_page()
571 * @write_subpage: function to write parts of the page covered by ECC.
572 * @write_page: function to write a page according to the ECC generator
574 * @write_oob_raw: function to write chip OOB data without ECC
575 * @read_oob_raw: function to read chip OOB data without ECC
576 * @read_oob: function to read chip OOB data
577 * @write_oob: function to write chip OOB data
579 struct nand_ecc_ctrl {
580 nand_ecc_modes_t mode;
588 unsigned int options;
589 struct nand_ecclayout *layout;
591 void (*hwctl)(struct mtd_info *mtd, int mode);
592 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
594 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
596 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
597 uint8_t *buf, int oob_required, int page);
598 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
599 const uint8_t *buf, int oob_required, int page);
600 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
601 uint8_t *buf, int oob_required, int page);
602 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
603 uint32_t offs, uint32_t len, uint8_t *buf, int page);
604 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
605 uint32_t offset, uint32_t data_len,
606 const uint8_t *data_buf, int oob_required, int page);
607 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
608 const uint8_t *buf, int oob_required, int page);
609 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
611 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
613 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
614 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
618 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
620 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
624 * struct nand_buffers - buffer structure for read/write
625 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
626 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
627 * @databuf: buffer pointer for data, size is (page size + oobsize).
629 * Do not change the order of buffers. databuf and oobrbuf must be in
632 struct nand_buffers {
633 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
634 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
635 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
640 * struct nand_sdr_timings - SDR NAND chip timings
642 * This struct defines the timing requirements of a SDR NAND chip.
643 * These information can be found in every NAND datasheets and the timings
644 * meaning are described in the ONFI specifications:
645 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
648 * All these timings are expressed in picoseconds.
650 * @tBERS_max: Block erase time
651 * @tCCS_min: Change column setup time
652 * @tPROG_max: Page program time
653 * @tR_max: Page read time
654 * @tALH_min: ALE hold time
655 * @tADL_min: ALE to data loading time
656 * @tALS_min: ALE setup time
657 * @tAR_min: ALE to RE# delay
658 * @tCEA_max: CE# access time
659 * @tCEH_min: CE# high hold time
660 * @tCH_min: CE# hold time
661 * @tCHZ_max: CE# high to output hi-Z
662 * @tCLH_min: CLE hold time
663 * @tCLR_min: CLE to RE# delay
664 * @tCLS_min: CLE setup time
665 * @tCOH_min: CE# high to output hold
666 * @tCS_min: CE# setup time
667 * @tDH_min: Data hold time
668 * @tDS_min: Data setup time
669 * @tFEAT_max: Busy time for Set Features and Get Features
670 * @tIR_min: Output hi-Z to RE# low
671 * @tITC_max: Interface and Timing Mode Change time
672 * @tRC_min: RE# cycle time
673 * @tREA_max: RE# access time
674 * @tREH_min: RE# high hold time
675 * @tRHOH_min: RE# high to output hold
676 * @tRHW_min: RE# high to WE# low
677 * @tRHZ_max: RE# high to output hi-Z
678 * @tRLOH_min: RE# low to output hold
679 * @tRP_min: RE# pulse width
680 * @tRR_min: Ready to RE# low (data only)
681 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
682 * rising edge of R/B#.
683 * @tWB_max: WE# high to SR[6] low
684 * @tWC_min: WE# cycle time
685 * @tWH_min: WE# high hold time
686 * @tWHR_min: WE# high to RE# low
687 * @tWP_min: WE# pulse width
688 * @tWW_min: WP# transition to WE# low
690 struct nand_sdr_timings {
732 * enum nand_data_interface_type - NAND interface timing type
733 * @NAND_SDR_IFACE: Single Data Rate interface
735 enum nand_data_interface_type {
740 * struct nand_data_interface - NAND interface timing
741 * @type: type of the timing
742 * @timings: The timing, type according to @type
744 struct nand_data_interface {
745 enum nand_data_interface_type type;
747 struct nand_sdr_timings sdr;
752 * nand_get_sdr_timings - get SDR timing from data interface
753 * @conf: The data interface
755 static inline const struct nand_sdr_timings *
756 nand_get_sdr_timings(const struct nand_data_interface *conf)
758 if (conf->type != NAND_SDR_IFACE)
759 return ERR_PTR(-EINVAL);
761 return &conf->timings.sdr;
765 * struct nand_chip - NAND Private Flash Chip Data
766 * @mtd: MTD device registered to the MTD framework
767 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
769 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
771 * @flash_node: [BOARDSPECIFIC] device node describing this instance
772 * @read_byte: [REPLACEABLE] read one byte from the chip
773 * @read_word: [REPLACEABLE] read one word from the chip
774 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
776 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
777 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
778 * @select_chip: [REPLACEABLE] select chip nr
779 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
780 * @block_markbad: [REPLACEABLE] mark a block bad
781 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
782 * ALE/CLE/nCE. Also used to write command and address
783 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
784 * device ready/busy line. If set to NULL no access to
785 * ready/busy is available and the ready/busy information
786 * is read from the chip status register.
787 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
788 * commands to the chip.
789 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
791 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
792 * setting the read-retry mode. Mostly needed for MLC NAND.
793 * @ecc: [BOARDSPECIFIC] ECC control structure
794 * @buffers: buffer structure for read/write
795 * @buf_align: minimum buffer alignment required by a platform
796 * @hwcontrol: platform-specific hardware control structure
797 * @erase: [REPLACEABLE] erase function
798 * @scan_bbt: [REPLACEABLE] function to scan bad block table
799 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
800 * data from array to read regs (tR).
801 * @state: [INTERN] the current state of the NAND device
802 * @oob_poi: "poison value buffer," used for laying out OOB data
804 * @page_shift: [INTERN] number of address bits in a page (column
806 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
807 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
808 * @chip_shift: [INTERN] number of address bits in one chip
809 * @options: [BOARDSPECIFIC] various chip options. They can partly
810 * be set to inform nand_scan about special functionality.
811 * See the defines for further explanation.
812 * @bbt_options: [INTERN] bad block specific options. All options used
813 * here must come from bbm.h. By default, these options
814 * will be copied to the appropriate nand_bbt_descr's.
815 * @badblockpos: [INTERN] position of the bad block marker in the oob
817 * @badblockbits: [INTERN] minimum number of set bits in a good block's
818 * bad block marker position; i.e., BBM == 11110111b is
819 * not bad when badblockbits == 7
820 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
821 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
822 * Minimum amount of bit errors per @ecc_step_ds guaranteed
823 * to be correctable. If unknown, set to zero.
824 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
825 * also from the datasheet. It is the recommended ECC step
826 * size, if known; if unknown, set to zero.
827 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
828 * set to the actually used ONFI mode if the chip is
829 * ONFI compliant or deduced from the datasheet if
830 * the NAND chip is not ONFI compliant.
831 * @numchips: [INTERN] number of physical chips
832 * @chipsize: [INTERN] the size of one chip for multichip arrays
833 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
834 * @pagebuf: [INTERN] holds the pagenumber which is currently in
836 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
837 * currently in data_buf.
838 * @subpagesize: [INTERN] holds the subpagesize
839 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
840 * non 0 if ONFI supported.
841 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
842 * non 0 if JEDEC supported.
843 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
844 * supported, 0 otherwise.
845 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
846 * supported, 0 otherwise.
847 * @read_retries: [INTERN] the number of read retry modes supported
848 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
849 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
850 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
851 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
852 * means the configuration should not be applied but
854 * @bbt: [INTERN] bad block table pointer
855 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
857 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
858 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
860 * @controller: [REPLACEABLE] a pointer to a hardware controller
861 * structure which is shared among multiple independent
863 * @priv: [OPTIONAL] pointer to private chip data
864 * @write_page: [REPLACEABLE] High-level page write function
869 void __iomem *IO_ADDR_R;
870 void __iomem *IO_ADDR_W;
874 uint8_t (*read_byte)(struct mtd_info *mtd);
875 u16 (*read_word)(struct mtd_info *mtd);
876 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
877 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
878 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
879 void (*select_chip)(struct mtd_info *mtd, int chip);
880 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
881 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
882 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
883 int (*dev_ready)(struct mtd_info *mtd);
884 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
886 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
887 int (*erase)(struct mtd_info *mtd, int page);
888 int (*scan_bbt)(struct mtd_info *mtd);
889 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
890 uint32_t offset, int data_len, const uint8_t *buf,
891 int oob_required, int page, int raw);
892 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
893 int feature_addr, uint8_t *subfeature_para);
894 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
895 int feature_addr, uint8_t *subfeature_para);
896 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
897 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
898 const struct nand_data_interface *conf);
902 unsigned int options;
903 unsigned int bbt_options;
906 int phys_erase_shift;
913 unsigned int pagebuf_bitflips;
915 uint8_t bits_per_cell;
916 uint16_t ecc_strength_ds;
917 uint16_t ecc_step_ds;
918 int onfi_timing_mode_default;
924 struct nand_onfi_params onfi_params;
925 struct nand_jedec_params jedec_params;
927 struct nand_data_interface *data_interface;
934 struct nand_hw_control *controller;
935 struct nand_ecclayout *ecclayout;
937 struct nand_ecc_ctrl ecc;
938 struct nand_buffers *buffers;
939 unsigned long buf_align;
940 struct nand_hw_control hwcontrol;
943 struct nand_bbt_descr *bbt_td;
944 struct nand_bbt_descr *bbt_md;
946 struct nand_bbt_descr *badblock_pattern;
951 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
953 return container_of(mtd, struct nand_chip, mtd);
956 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
961 static inline void *nand_get_controller_data(struct nand_chip *chip)
966 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
972 * NAND Flash Manufacturer ID Codes
974 #define NAND_MFR_TOSHIBA 0x98
975 #define NAND_MFR_SAMSUNG 0xec
976 #define NAND_MFR_FUJITSU 0x04
977 #define NAND_MFR_NATIONAL 0x8f
978 #define NAND_MFR_RENESAS 0x07
979 #define NAND_MFR_STMICRO 0x20
980 #define NAND_MFR_HYNIX 0xad
981 #define NAND_MFR_MICRON 0x2c
982 #define NAND_MFR_AMD 0x01
983 #define NAND_MFR_MACRONIX 0xc2
984 #define NAND_MFR_EON 0x92
985 #define NAND_MFR_SANDISK 0x45
986 #define NAND_MFR_INTEL 0x89
987 #define NAND_MFR_ATO 0x9b
989 /* The maximum expected count of bytes in the NAND ID sequence */
990 #define NAND_MAX_ID_LEN 8
993 * A helper for defining older NAND chips where the second ID byte fully
994 * defined the chip, including the geometry (chip size, eraseblock size, page
995 * size). All these chips have 512 bytes NAND page size.
997 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
998 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
999 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1002 * A helper for defining newer chips which report their page size and
1003 * eraseblock size via the extended ID bytes.
1005 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1006 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1007 * device ID now only represented a particular total chip size (and voltage,
1008 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1009 * using the same device ID.
1011 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1012 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1015 #define NAND_ECC_INFO(_strength, _step) \
1016 { .strength_ds = (_strength), .step_ds = (_step) }
1017 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1018 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1021 * struct nand_flash_dev - NAND Flash Device ID Structure
1022 * @name: a human-readable name of the NAND chip
1023 * @dev_id: the device ID (the second byte of the full chip ID array)
1024 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1025 * memory address as @id[0])
1026 * @dev_id: device ID part of the full chip ID array (refers the same memory
1027 * address as @id[1])
1028 * @id: full device ID array
1029 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1030 * well as the eraseblock size) is determined from the extended NAND
1032 * @chipsize: total chip size in MiB
1033 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1034 * @options: stores various chip bit options
1035 * @id_len: The valid length of the @id.
1036 * @oobsize: OOB size
1037 * @ecc: ECC correctability and step information from the datasheet.
1038 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1039 * @ecc_strength_ds in nand_chip{}.
1040 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1041 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1042 * For example, the "4bit ECC for each 512Byte" can be set with
1043 * NAND_ECC_INFO(4, 512).
1044 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1045 * reset. Should be deduced from timings described
1049 struct nand_flash_dev {
1056 uint8_t id[NAND_MAX_ID_LEN];
1058 unsigned int pagesize;
1059 unsigned int chipsize;
1060 unsigned int erasesize;
1061 unsigned int options;
1065 uint16_t strength_ds;
1068 int onfi_timing_mode_default;
1072 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1073 * @name: Manufacturer name
1074 * @id: manufacturer ID code of device.
1076 struct nand_manufacturers {
1081 extern struct nand_flash_dev nand_flash_ids[];
1082 extern struct nand_manufacturers nand_manuf_ids[];
1084 int nand_default_bbt(struct mtd_info *mtd);
1085 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1086 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1087 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1088 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1090 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1091 size_t *retlen, uint8_t *buf);
1094 * Constants for oob configuration
1096 #define NAND_SMALL_BADBLOCK_POS 5
1097 #define NAND_LARGE_BADBLOCK_POS 0
1100 * struct platform_nand_chip - chip level device structure
1101 * @nr_chips: max. number of chips to scan for
1102 * @chip_offset: chip number offset
1103 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1104 * @partitions: mtd partition list
1105 * @chip_delay: R/B delay value in us
1106 * @options: Option flags, e.g. 16bit buswidth
1107 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1108 * @part_probe_types: NULL-terminated array of probe types
1110 struct platform_nand_chip {
1114 struct mtd_partition *partitions;
1116 unsigned int options;
1117 unsigned int bbt_options;
1118 const char **part_probe_types;
1121 /* Keep gcc happy */
1122 struct platform_device;
1125 * struct platform_nand_ctrl - controller level device structure
1126 * @probe: platform specific function to probe/setup hardware
1127 * @remove: platform specific function to remove/teardown hardware
1128 * @hwcontrol: platform specific hardware control structure
1129 * @dev_ready: platform specific function to read ready/busy pin
1130 * @select_chip: platform specific chip select function
1131 * @cmd_ctrl: platform specific function for controlling
1132 * ALE/CLE/nCE. Also used to write command and address
1133 * @write_buf: platform specific function for write buffer
1134 * @read_buf: platform specific function for read buffer
1135 * @read_byte: platform specific function to read one byte from chip
1136 * @priv: private data to transport driver specific settings
1138 * All fields are optional and depend on the hardware driver requirements
1140 struct platform_nand_ctrl {
1141 int (*probe)(struct platform_device *pdev);
1142 void (*remove)(struct platform_device *pdev);
1143 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1144 int (*dev_ready)(struct mtd_info *mtd);
1145 void (*select_chip)(struct mtd_info *mtd, int chip);
1146 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1147 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1148 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1149 unsigned char (*read_byte)(struct mtd_info *mtd);
1154 * struct platform_nand_data - container structure for platform-specific data
1155 * @chip: chip level chip structure
1156 * @ctrl: controller level device structure
1158 struct platform_nand_data {
1159 struct platform_nand_chip chip;
1160 struct platform_nand_ctrl ctrl;
1163 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1164 /* return the supported features. */
1165 static inline int onfi_feature(struct nand_chip *chip)
1167 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1170 /* return the supported asynchronous timing mode. */
1171 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1173 if (!chip->onfi_version)
1174 return ONFI_TIMING_MODE_UNKNOWN;
1175 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1178 /* return the supported synchronous timing mode. */
1179 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1181 if (!chip->onfi_version)
1182 return ONFI_TIMING_MODE_UNKNOWN;
1183 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1186 static inline int onfi_feature(struct nand_chip *chip)
1191 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1193 return ONFI_TIMING_MODE_UNKNOWN;
1196 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1198 return ONFI_TIMING_MODE_UNKNOWN;
1202 int onfi_init_data_interface(struct nand_chip *chip,
1203 struct nand_data_interface *iface,
1204 enum nand_data_interface_type type,
1208 * Check if it is a SLC nand.
1209 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1210 * We do not distinguish the MLC and TLC now.
1212 static inline bool nand_is_slc(struct nand_chip *chip)
1214 return chip->bits_per_cell == 1;
1218 * Check if the opcode's address should be sent only on the lower 8 bits
1219 * @command: opcode to check
1221 static inline int nand_opcode_8bits(unsigned int command)
1224 case NAND_CMD_READID:
1225 case NAND_CMD_PARAM:
1226 case NAND_CMD_GET_FEATURES:
1227 case NAND_CMD_SET_FEATURES:
1235 /* return the supported JEDEC features. */
1236 static inline int jedec_feature(struct nand_chip *chip)
1238 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1242 /* Standard NAND functions from nand_base.c */
1243 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1244 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1245 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1246 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1247 uint8_t nand_read_byte(struct mtd_info *mtd);
1249 /* get timing characteristics from ONFI timing mode. */
1250 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1251 /* get data interface from ONFI timing mode 0, used after reset. */
1252 const struct nand_data_interface *nand_get_default_data_interface(void);
1254 int nand_check_erased_ecc_chunk(void *data, int datalen,
1255 void *ecc, int ecclen,
1256 void *extraoob, int extraooblen,
1259 int nand_check_ecc_caps(struct nand_chip *chip,
1260 const struct nand_ecc_caps *caps, int oobavail);
1262 int nand_match_ecc_req(struct nand_chip *chip,
1263 const struct nand_ecc_caps *caps, int oobavail);
1265 int nand_maximize_ecc(struct nand_chip *chip,
1266 const struct nand_ecc_caps *caps, int oobavail);
1268 /* Reset and initialize a NAND device */
1269 int nand_reset(struct nand_chip *chip, int chipnr);
1271 #endif /* __LINUX_MTD_NAND_H */