2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
11 * Contains standard defines and IDs for NAND flash devices
16 #ifndef __LINUX_MTD_NAND_H
17 #define __LINUX_MTD_NAND_H
21 #include <linux/compat.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/flashchip.h>
24 #include <linux/mtd/bbm.h>
27 struct nand_flash_dev;
30 /* Scan and identify a NAND device */
31 int nand_scan(struct mtd_info *mtd, int max_chips);
33 * Separate phases of nand_scan(), allowing board driver to intervene
34 * and override command or ECC setup according to flash type.
36 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
37 struct nand_flash_dev *table);
38 int nand_scan_tail(struct mtd_info *mtd);
40 /* Free resources held by the NAND device */
41 void nand_release(struct mtd_info *mtd);
43 /* Internal helper for board drivers which need to override command function */
44 void nand_wait_ready(struct mtd_info *mtd);
47 * This constant declares the max. oobsize / page, which
48 * is supported now. If you add a chip with bigger oobsize/page
49 * adjust this accordingly.
51 #define NAND_MAX_OOBSIZE 1664
52 #define NAND_MAX_PAGESIZE 16384
55 * Constants for hardware specific CLE/ALE/NCE function
57 * These are bits which can be or'ed to set/clear multiple
60 /* Select the chip by setting nCE to low */
62 /* Select the command latch by setting CLE to high */
64 /* Select the address latch by setting ALE to high */
67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
69 #define NAND_CTRL_CHANGE 0x80
72 * Standard NAND flash commands
74 #define NAND_CMD_READ0 0
75 #define NAND_CMD_READ1 1
76 #define NAND_CMD_RNDOUT 5
77 #define NAND_CMD_PAGEPROG 0x10
78 #define NAND_CMD_READOOB 0x50
79 #define NAND_CMD_ERASE1 0x60
80 #define NAND_CMD_STATUS 0x70
81 #define NAND_CMD_SEQIN 0x80
82 #define NAND_CMD_RNDIN 0x85
83 #define NAND_CMD_READID 0x90
84 #define NAND_CMD_ERASE2 0xd0
85 #define NAND_CMD_PARAM 0xec
86 #define NAND_CMD_GET_FEATURES 0xee
87 #define NAND_CMD_SET_FEATURES 0xef
88 #define NAND_CMD_RESET 0xff
90 #define NAND_CMD_LOCK 0x2a
91 #define NAND_CMD_UNLOCK1 0x23
92 #define NAND_CMD_UNLOCK2 0x24
94 /* Extended commands for large page devices */
95 #define NAND_CMD_READSTART 0x30
96 #define NAND_CMD_RNDOUTSTART 0xE0
97 #define NAND_CMD_CACHEDPROG 0x15
99 /* Extended commands for AG-AND device */
101 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
102 * there is no way to distinguish that from NAND_CMD_READ0
103 * until the remaining sequence of commands has been completed
104 * so add a high order bit and mask it off in the command.
106 #define NAND_CMD_DEPLETE1 0x100
107 #define NAND_CMD_DEPLETE2 0x38
108 #define NAND_CMD_STATUS_MULTI 0x71
109 #define NAND_CMD_STATUS_ERROR 0x72
110 /* multi-bank error status (banks 0-3) */
111 #define NAND_CMD_STATUS_ERROR0 0x73
112 #define NAND_CMD_STATUS_ERROR1 0x74
113 #define NAND_CMD_STATUS_ERROR2 0x75
114 #define NAND_CMD_STATUS_ERROR3 0x76
115 #define NAND_CMD_STATUS_RESET 0x7f
116 #define NAND_CMD_STATUS_CLEAR 0xff
118 #define NAND_CMD_NONE -1
121 #define NAND_STATUS_FAIL 0x01
122 #define NAND_STATUS_FAIL_N1 0x02
123 #define NAND_STATUS_TRUE_READY 0x20
124 #define NAND_STATUS_READY 0x40
125 #define NAND_STATUS_WP 0x80
127 #define NAND_DATA_IFACE_CHECK_ONLY -1
130 * Constants for ECC_MODES
136 NAND_ECC_HW_SYNDROME,
137 NAND_ECC_HW_OOB_FIRST,
142 * Constants for Hardware ECC
144 /* Reset Hardware ECC for read */
145 #define NAND_ECC_READ 0
146 /* Reset Hardware ECC for write */
147 #define NAND_ECC_WRITE 1
148 /* Enable Hardware ECC before syndrome is read back from flash */
149 #define NAND_ECC_READSYN 2
152 * Enable generic NAND 'page erased' check. This check is only done when
153 * ecc.correct() returns -EBADMSG.
154 * Set this flag if your implementation does not fix bitflips in erased
155 * pages and you want to rely on the default implementation.
157 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
158 #define NAND_ECC_MAXIMIZE BIT(1)
160 * If your controller already sends the required NAND commands when
161 * reading or writing a page, then the framework is not supposed to
162 * send READ0 and SEQIN/PAGEPROG respectively.
164 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
166 /* Bit mask for flags passed to do_nand_read_ecc */
167 #define NAND_GET_DEVICE 0x80
171 * Option constants for bizarre disfunctionality and real
174 /* Buswidth is 16 bit */
175 #define NAND_BUSWIDTH_16 0x00000002
176 /* Device supports partial programming without padding */
177 #define NAND_NO_PADDING 0x00000004
178 /* Chip has cache program function */
179 #define NAND_CACHEPRG 0x00000008
180 /* Chip has copy back function */
181 #define NAND_COPYBACK 0x00000010
183 * Chip requires ready check on read (for auto-incremented sequential read).
184 * True only for small page devices; large page devices do not support
187 #define NAND_NEED_READRDY 0x00000100
189 /* Chip does not allow subpage writes */
190 #define NAND_NO_SUBPAGE_WRITE 0x00000200
192 /* Device is one of 'new' xD cards that expose fake nand command set */
193 #define NAND_BROKEN_XD 0x00000400
195 /* Device behaves just like nand, but is readonly */
196 #define NAND_ROM 0x00000800
198 /* Device supports subpage reads */
199 #define NAND_SUBPAGE_READ 0x00001000
202 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
205 #define NAND_NEED_SCRAMBLING 0x00002000
207 /* Device needs 3rd row address cycle */
208 #define NAND_ROW_ADDR_3 0x00004000
210 /* Options valid for Samsung large page devices */
211 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
213 /* Macros to identify the above */
214 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
215 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
216 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
218 /* Non chip related options */
219 /* This option skips the bbt scan during initialization. */
220 #define NAND_SKIP_BBTSCAN 0x00010000
222 * This option is defined if the board driver allocates its own buffers
223 * (e.g. because it needs them DMA-coherent).
225 #define NAND_OWN_BUFFERS 0x00020000
226 /* Chip may not exist, so silence any errors in scan */
227 #define NAND_SCAN_SILENT_NODEV 0x00040000
229 * Autodetect nand buswidth with readid/onfi.
230 * This suppose the driver will configure the hardware in 8 bits mode
231 * when calling nand_scan_ident, and update its configuration
232 * before calling nand_scan_tail.
234 #define NAND_BUSWIDTH_AUTO 0x00080000
236 * This option could be defined by controller drivers to protect against
237 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
239 #define NAND_USE_BOUNCE_BUFFER 0x00100000
241 /* Options set by nand scan */
242 /* bbt has already been read */
243 #define NAND_BBT_SCANNED 0x40000000
244 /* Nand scan has allocated controller struct */
245 #define NAND_CONTROLLER_ALLOC 0x80000000
247 /* Cell info constants */
248 #define NAND_CI_CHIPNR_MSK 0x03
249 #define NAND_CI_CELLTYPE_MSK 0x0C
250 #define NAND_CI_CELLTYPE_SHIFT 2
256 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
257 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
259 /* ONFI timing mode, used in both asynchronous and synchronous mode */
260 #define ONFI_TIMING_MODE_0 (1 << 0)
261 #define ONFI_TIMING_MODE_1 (1 << 1)
262 #define ONFI_TIMING_MODE_2 (1 << 2)
263 #define ONFI_TIMING_MODE_3 (1 << 3)
264 #define ONFI_TIMING_MODE_4 (1 << 4)
265 #define ONFI_TIMING_MODE_5 (1 << 5)
266 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
268 /* ONFI feature address */
269 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
271 /* Vendor-specific feature address (Micron) */
272 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
274 /* ONFI subfeature parameters length */
275 #define ONFI_SUBFEATURE_PARAM_LEN 4
277 /* ONFI optional commands SET/GET FEATURES supported? */
278 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
280 struct nand_onfi_params {
281 /* rev info and features block */
282 /* 'O' 'N' 'F' 'I' */
288 __le16 ext_param_page_length; /* since ONFI 2.1 */
289 u8 num_of_param_pages; /* since ONFI 2.1 */
292 /* manufacturer information block */
293 char manufacturer[12];
299 /* memory organization block */
300 __le32 byte_per_page;
301 __le16 spare_bytes_per_page;
302 __le32 data_bytes_per_ppage;
303 __le16 spare_bytes_per_ppage;
304 __le32 pages_per_block;
305 __le32 blocks_per_lun;
310 __le16 block_endurance;
311 u8 guaranteed_good_blocks;
312 __le16 guaranteed_block_endurance;
313 u8 programs_per_page;
320 /* electrical parameter block */
321 u8 io_pin_capacitance_max;
322 __le16 async_timing_mode;
323 __le16 program_cache_timing_mode;
328 __le16 src_sync_timing_mode;
329 u8 src_ssync_features;
330 __le16 clk_pin_capacitance_typ;
331 __le16 io_pin_capacitance_typ;
332 __le16 input_pin_capacitance_typ;
333 u8 input_pin_capacitance_max;
334 u8 driver_strength_support;
340 __le16 vendor_revision;
346 #define ONFI_CRC_BASE 0x4F4E
348 /* Extended ECC information Block Definition (since ONFI 2.1) */
349 struct onfi_ext_ecc_info {
353 __le16 block_endurance;
357 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
358 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
359 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
360 struct onfi_ext_section {
365 #define ONFI_EXT_SECTION_MAX 8
367 /* Extended Parameter Page Definition (since ONFI 2.1) */
368 struct onfi_ext_param_page {
370 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
372 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
375 * The actual size of the Extended Parameter Page is in
376 * @ext_param_page_length of nand_onfi_params{}.
377 * The following are the variable length sections.
378 * So we do not add any fields below. Please see the ONFI spec.
382 struct nand_onfi_vendor_micron {
387 u8 dq_imped_num_settings;
388 u8 dq_imped_feat_addr;
389 u8 rb_pulldown_strength;
390 u8 rb_pulldown_strength_feat_addr;
391 u8 rb_pulldown_strength_num_settings;
394 u8 otp_data_prot_addr;
397 u8 read_retry_options;
402 struct jedec_ecc_info {
406 __le16 block_endurance;
411 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
413 struct nand_jedec_params {
414 /* rev info and features block */
415 /* 'J' 'E' 'S' 'D' */
421 u8 num_of_param_pages;
424 /* manufacturer information block */
425 char manufacturer[12];
430 /* memory organization block */
431 __le32 byte_per_page;
432 __le16 spare_bytes_per_page;
434 __le32 pages_per_block;
435 __le32 blocks_per_lun;
439 u8 programs_per_page;
441 u8 multi_plane_op_attr;
444 /* electrical parameter block */
445 __le16 async_sdr_speed_grade;
446 __le16 toggle_ddr_speed_grade;
447 __le16 sync_ddr_speed_grade;
448 u8 async_sdr_features;
449 u8 toggle_ddr_features;
450 u8 sync_ddr_features;
454 __le16 t_r_multi_plane;
456 __le16 io_pin_capacitance_typ;
457 __le16 input_pin_capacitance_typ;
458 __le16 clk_pin_capacitance_typ;
459 u8 driver_strength_support;
463 /* ECC and endurance block */
464 u8 guaranteed_good_blocks;
465 __le16 guaranteed_block_endurance;
466 struct jedec_ecc_info ecc_info[4];
473 __le16 vendor_rev_num;
476 /* CRC for Parameter Page */
481 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
482 * @lock: protection lock
483 * @active: the mtd device which holds the controller currently
484 * @wq: wait queue to sleep on if a NAND operation is in
485 * progress used instead of the per chip wait queue
486 * when a hw controller is available.
488 struct nand_hw_control {
490 struct nand_chip *active;
494 * struct nand_ecc_step_info - ECC step information of ECC engine
495 * @stepsize: data bytes per ECC step
496 * @strengths: array of supported strengths
497 * @nstrengths: number of supported strengths
499 struct nand_ecc_step_info {
501 const int *strengths;
506 * struct nand_ecc_caps - capability of ECC engine
507 * @stepinfos: array of ECC step information
508 * @nstepinfos: number of ECC step information
509 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
511 struct nand_ecc_caps {
512 const struct nand_ecc_step_info *stepinfos;
514 int (*calc_ecc_bytes)(int step_size, int strength);
517 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
518 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
519 static const int __name##_strengths[] = { __VA_ARGS__ }; \
520 static const struct nand_ecc_step_info __name##_stepinfo = { \
521 .stepsize = __step, \
522 .strengths = __name##_strengths, \
523 .nstrengths = ARRAY_SIZE(__name##_strengths), \
525 static const struct nand_ecc_caps __name = { \
526 .stepinfos = &__name##_stepinfo, \
528 .calc_ecc_bytes = __calc, \
532 * struct nand_ecc_ctrl - Control structure for ECC
534 * @steps: number of ECC steps per page
535 * @size: data bytes per ECC step
536 * @bytes: ECC bytes per step
537 * @strength: max number of correctible bits per ECC step
538 * @total: total number of ECC bytes per page
539 * @prepad: padding information for syndrome based ECC generators
540 * @postpad: padding information for syndrome based ECC generators
541 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
542 * @layout: ECC layout control struct pointer
543 * @priv: pointer to private ECC control data
544 * @hwctl: function to control hardware ECC generator. Must only
545 * be provided if an hardware ECC is available
546 * @calculate: function for ECC calculation or readback from ECC hardware
547 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
548 * Should return a positive number representing the number of
549 * corrected bitflips, -EBADMSG if the number of bitflips exceed
550 * ECC strength, or any other error code if the error is not
551 * directly related to correction.
552 * If -EBADMSG is returned the input buffers should be left
554 * @read_page_raw: function to read a raw page without ECC. This function
555 * should hide the specific layout used by the ECC
556 * controller and always return contiguous in-band and
557 * out-of-band data even if they're not stored
558 * contiguously on the NAND chip (e.g.
559 * NAND_ECC_HW_SYNDROME interleaves in-band and
561 * @write_page_raw: function to write a raw page without ECC. This function
562 * should hide the specific layout used by the ECC
563 * controller and consider the passed data as contiguous
564 * in-band and out-of-band data. ECC controller is
565 * responsible for doing the appropriate transformations
566 * to adapt to its specific layout (e.g.
567 * NAND_ECC_HW_SYNDROME interleaves in-band and
569 * @read_page: function to read a page according to the ECC generator
570 * requirements; returns maximum number of bitflips corrected in
571 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
572 * @read_subpage: function to read parts of the page covered by ECC;
573 * returns same as read_page()
574 * @write_subpage: function to write parts of the page covered by ECC.
575 * @write_page: function to write a page according to the ECC generator
577 * @write_oob_raw: function to write chip OOB data without ECC
578 * @read_oob_raw: function to read chip OOB data without ECC
579 * @read_oob: function to read chip OOB data
580 * @write_oob: function to write chip OOB data
582 struct nand_ecc_ctrl {
583 nand_ecc_modes_t mode;
591 unsigned int options;
592 struct nand_ecclayout *layout;
594 void (*hwctl)(struct mtd_info *mtd, int mode);
595 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
597 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
599 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
600 uint8_t *buf, int oob_required, int page);
601 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
602 const uint8_t *buf, int oob_required, int page);
603 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
604 uint8_t *buf, int oob_required, int page);
605 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
606 uint32_t offs, uint32_t len, uint8_t *buf, int page);
607 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
608 uint32_t offset, uint32_t data_len,
609 const uint8_t *data_buf, int oob_required, int page);
610 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
611 const uint8_t *buf, int oob_required, int page);
612 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
614 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
616 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
617 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
621 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
623 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
627 * struct nand_buffers - buffer structure for read/write
628 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
629 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
630 * @databuf: buffer pointer for data, size is (page size + oobsize).
632 * Do not change the order of buffers. databuf and oobrbuf must be in
635 struct nand_buffers {
636 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
637 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
638 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
643 * struct nand_sdr_timings - SDR NAND chip timings
645 * This struct defines the timing requirements of a SDR NAND chip.
646 * These information can be found in every NAND datasheets and the timings
647 * meaning are described in the ONFI specifications:
648 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
651 * All these timings are expressed in picoseconds.
653 * @tBERS_max: Block erase time
654 * @tCCS_min: Change column setup time
655 * @tPROG_max: Page program time
656 * @tR_max: Page read time
657 * @tALH_min: ALE hold time
658 * @tADL_min: ALE to data loading time
659 * @tALS_min: ALE setup time
660 * @tAR_min: ALE to RE# delay
661 * @tCEA_max: CE# access time
662 * @tCEH_min: CE# high hold time
663 * @tCH_min: CE# hold time
664 * @tCHZ_max: CE# high to output hi-Z
665 * @tCLH_min: CLE hold time
666 * @tCLR_min: CLE to RE# delay
667 * @tCLS_min: CLE setup time
668 * @tCOH_min: CE# high to output hold
669 * @tCS_min: CE# setup time
670 * @tDH_min: Data hold time
671 * @tDS_min: Data setup time
672 * @tFEAT_max: Busy time for Set Features and Get Features
673 * @tIR_min: Output hi-Z to RE# low
674 * @tITC_max: Interface and Timing Mode Change time
675 * @tRC_min: RE# cycle time
676 * @tREA_max: RE# access time
677 * @tREH_min: RE# high hold time
678 * @tRHOH_min: RE# high to output hold
679 * @tRHW_min: RE# high to WE# low
680 * @tRHZ_max: RE# high to output hi-Z
681 * @tRLOH_min: RE# low to output hold
682 * @tRP_min: RE# pulse width
683 * @tRR_min: Ready to RE# low (data only)
684 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
685 * rising edge of R/B#.
686 * @tWB_max: WE# high to SR[6] low
687 * @tWC_min: WE# cycle time
688 * @tWH_min: WE# high hold time
689 * @tWHR_min: WE# high to RE# low
690 * @tWP_min: WE# pulse width
691 * @tWW_min: WP# transition to WE# low
693 struct nand_sdr_timings {
735 * enum nand_data_interface_type - NAND interface timing type
736 * @NAND_SDR_IFACE: Single Data Rate interface
738 enum nand_data_interface_type {
743 * struct nand_data_interface - NAND interface timing
744 * @type: type of the timing
745 * @timings: The timing, type according to @type
747 struct nand_data_interface {
748 enum nand_data_interface_type type;
750 struct nand_sdr_timings sdr;
755 * nand_get_sdr_timings - get SDR timing from data interface
756 * @conf: The data interface
758 static inline const struct nand_sdr_timings *
759 nand_get_sdr_timings(const struct nand_data_interface *conf)
761 if (conf->type != NAND_SDR_IFACE)
762 return ERR_PTR(-EINVAL);
764 return &conf->timings.sdr;
768 * struct nand_chip - NAND Private Flash Chip Data
769 * @mtd: MTD device registered to the MTD framework
770 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
772 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
774 * @flash_node: [BOARDSPECIFIC] device node describing this instance
775 * @read_byte: [REPLACEABLE] read one byte from the chip
776 * @read_word: [REPLACEABLE] read one word from the chip
777 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
779 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
780 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
781 * @select_chip: [REPLACEABLE] select chip nr
782 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
783 * @block_markbad: [REPLACEABLE] mark a block bad
784 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
785 * ALE/CLE/nCE. Also used to write command and address
786 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
787 * device ready/busy line. If set to NULL no access to
788 * ready/busy is available and the ready/busy information
789 * is read from the chip status register.
790 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
791 * commands to the chip.
792 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
794 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
795 * setting the read-retry mode. Mostly needed for MLC NAND.
796 * @ecc: [BOARDSPECIFIC] ECC control structure
797 * @buffers: buffer structure for read/write
798 * @buf_align: minimum buffer alignment required by a platform
799 * @hwcontrol: platform-specific hardware control structure
800 * @erase: [REPLACEABLE] erase function
801 * @scan_bbt: [REPLACEABLE] function to scan bad block table
802 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
803 * data from array to read regs (tR).
804 * @state: [INTERN] the current state of the NAND device
805 * @oob_poi: "poison value buffer," used for laying out OOB data
807 * @page_shift: [INTERN] number of address bits in a page (column
809 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
810 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
811 * @chip_shift: [INTERN] number of address bits in one chip
812 * @options: [BOARDSPECIFIC] various chip options. They can partly
813 * be set to inform nand_scan about special functionality.
814 * See the defines for further explanation.
815 * @bbt_options: [INTERN] bad block specific options. All options used
816 * here must come from bbm.h. By default, these options
817 * will be copied to the appropriate nand_bbt_descr's.
818 * @badblockpos: [INTERN] position of the bad block marker in the oob
820 * @badblockbits: [INTERN] minimum number of set bits in a good block's
821 * bad block marker position; i.e., BBM == 11110111b is
822 * not bad when badblockbits == 7
823 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
824 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
825 * Minimum amount of bit errors per @ecc_step_ds guaranteed
826 * to be correctable. If unknown, set to zero.
827 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
828 * also from the datasheet. It is the recommended ECC step
829 * size, if known; if unknown, set to zero.
830 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
831 * set to the actually used ONFI mode if the chip is
832 * ONFI compliant or deduced from the datasheet if
833 * the NAND chip is not ONFI compliant.
834 * @numchips: [INTERN] number of physical chips
835 * @chipsize: [INTERN] the size of one chip for multichip arrays
836 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
837 * @pagebuf: [INTERN] holds the pagenumber which is currently in
839 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
840 * currently in data_buf.
841 * @subpagesize: [INTERN] holds the subpagesize
842 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
843 * non 0 if ONFI supported.
844 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
845 * non 0 if JEDEC supported.
846 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
847 * supported, 0 otherwise.
848 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
849 * supported, 0 otherwise.
850 * @read_retries: [INTERN] the number of read retry modes supported
851 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
852 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
853 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
854 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
855 * means the configuration should not be applied but
857 * @bbt: [INTERN] bad block table pointer
858 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
860 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
861 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
863 * @controller: [REPLACEABLE] a pointer to a hardware controller
864 * structure which is shared among multiple independent
866 * @priv: [OPTIONAL] pointer to private chip data
867 * @write_page: [REPLACEABLE] High-level page write function
872 void __iomem *IO_ADDR_R;
873 void __iomem *IO_ADDR_W;
877 uint8_t (*read_byte)(struct mtd_info *mtd);
878 u16 (*read_word)(struct mtd_info *mtd);
879 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
880 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
881 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
882 void (*select_chip)(struct mtd_info *mtd, int chip);
883 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
884 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
885 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
886 int (*dev_ready)(struct mtd_info *mtd);
887 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
889 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
890 int (*erase)(struct mtd_info *mtd, int page);
891 int (*scan_bbt)(struct mtd_info *mtd);
892 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
893 uint32_t offset, int data_len, const uint8_t *buf,
894 int oob_required, int page, int raw);
895 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
896 int feature_addr, uint8_t *subfeature_para);
897 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
898 int feature_addr, uint8_t *subfeature_para);
899 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
900 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
901 const struct nand_data_interface *conf);
905 unsigned int options;
906 unsigned int bbt_options;
909 int phys_erase_shift;
916 unsigned int pagebuf_bitflips;
918 uint8_t bits_per_cell;
919 uint16_t ecc_strength_ds;
920 uint16_t ecc_step_ds;
921 int onfi_timing_mode_default;
927 struct nand_onfi_params onfi_params;
928 struct nand_jedec_params jedec_params;
930 struct nand_data_interface *data_interface;
937 struct nand_hw_control *controller;
938 struct nand_ecclayout *ecclayout;
940 struct nand_ecc_ctrl ecc;
941 struct nand_buffers *buffers;
942 unsigned long buf_align;
943 struct nand_hw_control hwcontrol;
946 struct nand_bbt_descr *bbt_td;
947 struct nand_bbt_descr *bbt_md;
949 struct nand_bbt_descr *badblock_pattern;
954 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
956 return container_of(mtd, struct nand_chip, mtd);
959 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
964 static inline void *nand_get_controller_data(struct nand_chip *chip)
969 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
975 * NAND Flash Manufacturer ID Codes
977 #define NAND_MFR_TOSHIBA 0x98
978 #define NAND_MFR_SAMSUNG 0xec
979 #define NAND_MFR_FUJITSU 0x04
980 #define NAND_MFR_NATIONAL 0x8f
981 #define NAND_MFR_RENESAS 0x07
982 #define NAND_MFR_STMICRO 0x20
983 #define NAND_MFR_HYNIX 0xad
984 #define NAND_MFR_MICRON 0x2c
985 #define NAND_MFR_AMD 0x01
986 #define NAND_MFR_MACRONIX 0xc2
987 #define NAND_MFR_EON 0x92
988 #define NAND_MFR_SANDISK 0x45
989 #define NAND_MFR_INTEL 0x89
990 #define NAND_MFR_ATO 0x9b
992 /* The maximum expected count of bytes in the NAND ID sequence */
993 #define NAND_MAX_ID_LEN 8
996 * A helper for defining older NAND chips where the second ID byte fully
997 * defined the chip, including the geometry (chip size, eraseblock size, page
998 * size). All these chips have 512 bytes NAND page size.
1000 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1001 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1002 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1005 * A helper for defining newer chips which report their page size and
1006 * eraseblock size via the extended ID bytes.
1008 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1009 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1010 * device ID now only represented a particular total chip size (and voltage,
1011 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1012 * using the same device ID.
1014 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1015 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1018 #define NAND_ECC_INFO(_strength, _step) \
1019 { .strength_ds = (_strength), .step_ds = (_step) }
1020 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1021 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1024 * struct nand_flash_dev - NAND Flash Device ID Structure
1025 * @name: a human-readable name of the NAND chip
1026 * @dev_id: the device ID (the second byte of the full chip ID array)
1027 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1028 * memory address as @id[0])
1029 * @dev_id: device ID part of the full chip ID array (refers the same memory
1030 * address as @id[1])
1031 * @id: full device ID array
1032 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1033 * well as the eraseblock size) is determined from the extended NAND
1035 * @chipsize: total chip size in MiB
1036 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1037 * @options: stores various chip bit options
1038 * @id_len: The valid length of the @id.
1039 * @oobsize: OOB size
1040 * @ecc: ECC correctability and step information from the datasheet.
1041 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1042 * @ecc_strength_ds in nand_chip{}.
1043 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1044 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1045 * For example, the "4bit ECC for each 512Byte" can be set with
1046 * NAND_ECC_INFO(4, 512).
1047 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1048 * reset. Should be deduced from timings described
1052 struct nand_flash_dev {
1059 uint8_t id[NAND_MAX_ID_LEN];
1061 unsigned int pagesize;
1062 unsigned int chipsize;
1063 unsigned int erasesize;
1064 unsigned int options;
1068 uint16_t strength_ds;
1071 int onfi_timing_mode_default;
1075 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1076 * @name: Manufacturer name
1077 * @id: manufacturer ID code of device.
1079 struct nand_manufacturers {
1084 extern struct nand_flash_dev nand_flash_ids[];
1085 extern struct nand_manufacturers nand_manuf_ids[];
1087 int nand_default_bbt(struct mtd_info *mtd);
1088 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1089 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1090 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1091 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1093 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1094 size_t *retlen, uint8_t *buf);
1097 * Constants for oob configuration
1099 #define NAND_SMALL_BADBLOCK_POS 5
1100 #define NAND_LARGE_BADBLOCK_POS 0
1103 * struct platform_nand_chip - chip level device structure
1104 * @nr_chips: max. number of chips to scan for
1105 * @chip_offset: chip number offset
1106 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1107 * @partitions: mtd partition list
1108 * @chip_delay: R/B delay value in us
1109 * @options: Option flags, e.g. 16bit buswidth
1110 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1111 * @part_probe_types: NULL-terminated array of probe types
1113 struct platform_nand_chip {
1117 struct mtd_partition *partitions;
1119 unsigned int options;
1120 unsigned int bbt_options;
1121 const char **part_probe_types;
1124 /* Keep gcc happy */
1125 struct platform_device;
1128 * struct platform_nand_ctrl - controller level device structure
1129 * @probe: platform specific function to probe/setup hardware
1130 * @remove: platform specific function to remove/teardown hardware
1131 * @hwcontrol: platform specific hardware control structure
1132 * @dev_ready: platform specific function to read ready/busy pin
1133 * @select_chip: platform specific chip select function
1134 * @cmd_ctrl: platform specific function for controlling
1135 * ALE/CLE/nCE. Also used to write command and address
1136 * @write_buf: platform specific function for write buffer
1137 * @read_buf: platform specific function for read buffer
1138 * @read_byte: platform specific function to read one byte from chip
1139 * @priv: private data to transport driver specific settings
1141 * All fields are optional and depend on the hardware driver requirements
1143 struct platform_nand_ctrl {
1144 int (*probe)(struct platform_device *pdev);
1145 void (*remove)(struct platform_device *pdev);
1146 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1147 int (*dev_ready)(struct mtd_info *mtd);
1148 void (*select_chip)(struct mtd_info *mtd, int chip);
1149 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1150 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1151 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1152 unsigned char (*read_byte)(struct mtd_info *mtd);
1157 * struct platform_nand_data - container structure for platform-specific data
1158 * @chip: chip level chip structure
1159 * @ctrl: controller level device structure
1161 struct platform_nand_data {
1162 struct platform_nand_chip chip;
1163 struct platform_nand_ctrl ctrl;
1166 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1167 /* return the supported features. */
1168 static inline int onfi_feature(struct nand_chip *chip)
1170 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1173 /* return the supported asynchronous timing mode. */
1174 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1176 if (!chip->onfi_version)
1177 return ONFI_TIMING_MODE_UNKNOWN;
1178 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1181 /* return the supported synchronous timing mode. */
1182 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1184 if (!chip->onfi_version)
1185 return ONFI_TIMING_MODE_UNKNOWN;
1186 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1189 static inline int onfi_feature(struct nand_chip *chip)
1194 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1196 return ONFI_TIMING_MODE_UNKNOWN;
1199 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1201 return ONFI_TIMING_MODE_UNKNOWN;
1205 int onfi_init_data_interface(struct nand_chip *chip,
1206 struct nand_data_interface *iface,
1207 enum nand_data_interface_type type,
1211 * Check if it is a SLC nand.
1212 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1213 * We do not distinguish the MLC and TLC now.
1215 static inline bool nand_is_slc(struct nand_chip *chip)
1217 return chip->bits_per_cell == 1;
1221 * Check if the opcode's address should be sent only on the lower 8 bits
1222 * @command: opcode to check
1224 static inline int nand_opcode_8bits(unsigned int command)
1227 case NAND_CMD_READID:
1228 case NAND_CMD_PARAM:
1229 case NAND_CMD_GET_FEATURES:
1230 case NAND_CMD_SET_FEATURES:
1238 /* return the supported JEDEC features. */
1239 static inline int jedec_feature(struct nand_chip *chip)
1241 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1245 /* Standard NAND functions from nand_base.c */
1246 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1247 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1248 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1249 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1250 uint8_t nand_read_byte(struct mtd_info *mtd);
1252 /* get timing characteristics from ONFI timing mode. */
1253 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1254 /* get data interface from ONFI timing mode 0, used after reset. */
1255 const struct nand_data_interface *nand_get_default_data_interface(void);
1257 int nand_check_erased_ecc_chunk(void *data, int datalen,
1258 void *ecc, int ecclen,
1259 void *extraoob, int extraooblen,
1262 int nand_check_ecc_caps(struct nand_chip *chip,
1263 const struct nand_ecc_caps *caps, int oobavail);
1265 int nand_match_ecc_req(struct nand_chip *chip,
1266 const struct nand_ecc_caps *caps, int oobavail);
1268 int nand_maximize_ecc(struct nand_chip *chip,
1269 const struct nand_ecc_caps *caps, int oobavail);
1271 /* Reset and initialize a NAND device */
1272 int nand_reset(struct nand_chip *chip, int chipnr);
1274 #endif /* __LINUX_MTD_NAND_H */