2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
11 * Contains standard defines and IDs for NAND flash devices
16 #ifndef __LINUX_MTD_NAND_H
17 #define __LINUX_MTD_NAND_H
21 #include "linux/compat.h"
22 #include "linux/mtd/mtd.h"
23 #include "linux/mtd/flashchip.h"
24 #include "linux/mtd/bbm.h"
27 struct nand_flash_dev;
28 /* Scan and identify a NAND device */
29 extern int nand_scan(struct mtd_info *mtd, int max_chips);
31 * Separate phases of nand_scan(), allowing board driver to intervene
32 * and override command or ECC setup according to flash type.
34 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
35 struct nand_flash_dev *table);
36 extern int nand_scan_tail(struct mtd_info *mtd);
38 /* Free resources held by the NAND device */
39 extern void nand_release(struct mtd_info *mtd);
41 /* Internal helper for board drivers which need to override command function */
42 extern void nand_wait_ready(struct mtd_info *mtd);
45 * This constant declares the max. oobsize / page, which
46 * is supported now. If you add a chip with bigger oobsize/page
47 * adjust this accordingly.
49 #define NAND_MAX_OOBSIZE 744
50 #define NAND_MAX_PAGESIZE 8192
53 * Constants for hardware specific CLE/ALE/NCE function
55 * These are bits which can be or'ed to set/clear multiple
58 /* Select the chip by setting nCE to low */
60 /* Select the command latch by setting CLE to high */
62 /* Select the address latch by setting ALE to high */
65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
67 #define NAND_CTRL_CHANGE 0x80
70 * Standard NAND flash commands
72 #define NAND_CMD_READ0 0
73 #define NAND_CMD_READ1 1
74 #define NAND_CMD_RNDOUT 5
75 #define NAND_CMD_PAGEPROG 0x10
76 #define NAND_CMD_READOOB 0x50
77 #define NAND_CMD_ERASE1 0x60
78 #define NAND_CMD_STATUS 0x70
79 #define NAND_CMD_SEQIN 0x80
80 #define NAND_CMD_RNDIN 0x85
81 #define NAND_CMD_READID 0x90
82 #define NAND_CMD_ERASE2 0xd0
83 #define NAND_CMD_PARAM 0xec
84 #define NAND_CMD_GET_FEATURES 0xee
85 #define NAND_CMD_SET_FEATURES 0xef
86 #define NAND_CMD_RESET 0xff
88 #define NAND_CMD_LOCK 0x2a
89 #define NAND_CMD_UNLOCK1 0x23
90 #define NAND_CMD_UNLOCK2 0x24
92 /* Extended commands for large page devices */
93 #define NAND_CMD_READSTART 0x30
94 #define NAND_CMD_RNDOUTSTART 0xE0
95 #define NAND_CMD_CACHEDPROG 0x15
97 /* Extended commands for AG-AND device */
99 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
100 * there is no way to distinguish that from NAND_CMD_READ0
101 * until the remaining sequence of commands has been completed
102 * so add a high order bit and mask it off in the command.
104 #define NAND_CMD_DEPLETE1 0x100
105 #define NAND_CMD_DEPLETE2 0x38
106 #define NAND_CMD_STATUS_MULTI 0x71
107 #define NAND_CMD_STATUS_ERROR 0x72
108 /* multi-bank error status (banks 0-3) */
109 #define NAND_CMD_STATUS_ERROR0 0x73
110 #define NAND_CMD_STATUS_ERROR1 0x74
111 #define NAND_CMD_STATUS_ERROR2 0x75
112 #define NAND_CMD_STATUS_ERROR3 0x76
113 #define NAND_CMD_STATUS_RESET 0x7f
114 #define NAND_CMD_STATUS_CLEAR 0xff
116 #define NAND_CMD_NONE -1
119 #define NAND_STATUS_FAIL 0x01
120 #define NAND_STATUS_FAIL_N1 0x02
121 #define NAND_STATUS_TRUE_READY 0x20
122 #define NAND_STATUS_READY 0x40
123 #define NAND_STATUS_WP 0x80
126 * Constants for ECC_MODES
132 NAND_ECC_HW_SYNDROME,
133 NAND_ECC_HW_OOB_FIRST,
138 * Constants for Hardware ECC
140 /* Reset Hardware ECC for read */
141 #define NAND_ECC_READ 0
142 /* Reset Hardware ECC for write */
143 #define NAND_ECC_WRITE 1
144 /* Enable Hardware ECC before syndrome is read back from flash */
145 #define NAND_ECC_READSYN 2
147 /* Bit mask for flags passed to do_nand_read_ecc */
148 #define NAND_GET_DEVICE 0x80
152 * Option constants for bizarre disfunctionality and real
155 /* Buswidth is 16 bit */
156 #define NAND_BUSWIDTH_16 0x00000002
157 /* Device supports partial programming without padding */
158 #define NAND_NO_PADDING 0x00000004
159 /* Chip has cache program function */
160 #define NAND_CACHEPRG 0x00000008
161 /* Chip has copy back function */
162 #define NAND_COPYBACK 0x00000010
164 * Chip requires ready check on read (for auto-incremented sequential read).
165 * True only for small page devices; large page devices do not support
168 #define NAND_NEED_READRDY 0x00000100
170 /* Chip does not allow subpage writes */
171 #define NAND_NO_SUBPAGE_WRITE 0x00000200
173 /* Device is one of 'new' xD cards that expose fake nand command set */
174 #define NAND_BROKEN_XD 0x00000400
176 /* Device behaves just like nand, but is readonly */
177 #define NAND_ROM 0x00000800
179 /* Device supports subpage reads */
180 #define NAND_SUBPAGE_READ 0x00001000
182 /* Options valid for Samsung large page devices */
183 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
185 /* Macros to identify the above */
186 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
187 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
189 /* Non chip related options */
190 /* This option skips the bbt scan during initialization. */
191 #define NAND_SKIP_BBTSCAN 0x00010000
193 * This option is defined if the board driver allocates its own buffers
194 * (e.g. because it needs them DMA-coherent).
196 #define NAND_OWN_BUFFERS 0x00020000
197 /* Chip may not exist, so silence any errors in scan */
198 #define NAND_SCAN_SILENT_NODEV 0x00040000
200 * Autodetect nand buswidth with readid/onfi.
201 * This suppose the driver will configure the hardware in 8 bits mode
202 * when calling nand_scan_ident, and update its configuration
203 * before calling nand_scan_tail.
205 #define NAND_BUSWIDTH_AUTO 0x00080000
207 /* Options set by nand scan */
208 /* bbt has already been read */
209 #define NAND_BBT_SCANNED 0x40000000
210 /* Nand scan has allocated controller struct */
211 #define NAND_CONTROLLER_ALLOC 0x80000000
213 /* Cell info constants */
214 #define NAND_CI_CHIPNR_MSK 0x03
215 #define NAND_CI_CELLTYPE_MSK 0x0C
216 #define NAND_CI_CELLTYPE_SHIFT 2
222 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
223 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
225 /* ONFI timing mode, used in both asynchronous and synchronous mode */
226 #define ONFI_TIMING_MODE_0 (1 << 0)
227 #define ONFI_TIMING_MODE_1 (1 << 1)
228 #define ONFI_TIMING_MODE_2 (1 << 2)
229 #define ONFI_TIMING_MODE_3 (1 << 3)
230 #define ONFI_TIMING_MODE_4 (1 << 4)
231 #define ONFI_TIMING_MODE_5 (1 << 5)
232 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
234 /* ONFI feature address */
235 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
237 /* Vendor-specific feature address (Micron) */
238 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
240 /* ONFI subfeature parameters length */
241 #define ONFI_SUBFEATURE_PARAM_LEN 4
243 /* ONFI optional commands SET/GET FEATURES supported? */
244 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
246 struct nand_onfi_params {
247 /* rev info and features block */
248 /* 'O' 'N' 'F' 'I' */
254 __le16 ext_param_page_length; /* since ONFI 2.1 */
255 u8 num_of_param_pages; /* since ONFI 2.1 */
258 /* manufacturer information block */
259 char manufacturer[12];
265 /* memory organization block */
266 __le32 byte_per_page;
267 __le16 spare_bytes_per_page;
268 __le32 data_bytes_per_ppage;
269 __le16 spare_bytes_per_ppage;
270 __le32 pages_per_block;
271 __le32 blocks_per_lun;
276 __le16 block_endurance;
277 u8 guaranteed_good_blocks;
278 __le16 guaranteed_block_endurance;
279 u8 programs_per_page;
286 /* electrical parameter block */
287 u8 io_pin_capacitance_max;
288 __le16 async_timing_mode;
289 __le16 program_cache_timing_mode;
294 __le16 src_sync_timing_mode;
295 __le16 src_ssync_features;
296 __le16 clk_pin_capacitance_typ;
297 __le16 io_pin_capacitance_typ;
298 __le16 input_pin_capacitance_typ;
299 u8 input_pin_capacitance_max;
300 u8 driver_strength_support;
306 __le16 vendor_revision;
312 #define ONFI_CRC_BASE 0x4F4E
314 /* Extended ECC information Block Definition (since ONFI 2.1) */
315 struct onfi_ext_ecc_info {
319 __le16 block_endurance;
323 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
324 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
325 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
326 struct onfi_ext_section {
331 #define ONFI_EXT_SECTION_MAX 8
333 /* Extended Parameter Page Definition (since ONFI 2.1) */
334 struct onfi_ext_param_page {
336 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
338 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
341 * The actual size of the Extended Parameter Page is in
342 * @ext_param_page_length of nand_onfi_params{}.
343 * The following are the variable length sections.
344 * So we do not add any fields below. Please see the ONFI spec.
348 struct nand_onfi_vendor_micron {
353 u8 dq_imped_num_settings;
354 u8 dq_imped_feat_addr;
355 u8 rb_pulldown_strength;
356 u8 rb_pulldown_strength_feat_addr;
357 u8 rb_pulldown_strength_num_settings;
360 u8 otp_data_prot_addr;
363 u8 read_retry_options;
368 struct jedec_ecc_info {
372 __le16 block_endurance;
377 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
379 struct nand_jedec_params {
380 /* rev info and features block */
381 /* 'J' 'E' 'S' 'D' */
387 u8 num_of_param_pages;
390 /* manufacturer information block */
391 char manufacturer[12];
396 /* memory organization block */
397 __le32 byte_per_page;
398 __le16 spare_bytes_per_page;
400 __le32 pages_per_block;
401 __le32 blocks_per_lun;
405 u8 programs_per_page;
407 u8 multi_plane_op_attr;
410 /* electrical parameter block */
411 __le16 async_sdr_speed_grade;
412 __le16 toggle_ddr_speed_grade;
413 __le16 sync_ddr_speed_grade;
414 u8 async_sdr_features;
415 u8 toggle_ddr_features;
416 u8 sync_ddr_features;
420 __le16 t_r_multi_plane;
422 __le16 io_pin_capacitance_typ;
423 __le16 input_pin_capacitance_typ;
424 __le16 clk_pin_capacitance_typ;
425 u8 driver_strength_support;
429 /* ECC and endurance block */
430 u8 guaranteed_good_blocks;
431 __le16 guaranteed_block_endurance;
432 struct jedec_ecc_info ecc_info[4];
439 __le16 vendor_rev_num;
442 /* CRC for Parameter Page */
447 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
448 * @lock: protection lock
449 * @active: the mtd device which holds the controller currently
450 * @wq: wait queue to sleep on if a NAND operation is in
451 * progress used instead of the per chip wait queue
452 * when a hw controller is available.
454 struct nand_hw_control {
456 struct nand_chip *active;
460 * struct nand_ecc_ctrl - Control structure for ECC
462 * @steps: number of ECC steps per page
463 * @size: data bytes per ECC step
464 * @bytes: ECC bytes per step
465 * @strength: max number of correctible bits per ECC step
466 * @total: total number of ECC bytes per page
467 * @prepad: padding information for syndrome based ECC generators
468 * @postpad: padding information for syndrome based ECC generators
469 * @layout: ECC layout control struct pointer
470 * @priv: pointer to private ECC control data
471 * @hwctl: function to control hardware ECC generator. Must only
472 * be provided if an hardware ECC is available
473 * @calculate: function for ECC calculation or readback from ECC hardware
474 * @correct: function for ECC correction, matching to ECC generator (sw/hw)
475 * @read_page_raw: function to read a raw page without ECC
476 * @write_page_raw: function to write a raw page without ECC
477 * @read_page: function to read a page according to the ECC generator
478 * requirements; returns maximum number of bitflips corrected in
479 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
480 * @read_subpage: function to read parts of the page covered by ECC;
481 * returns same as read_page()
482 * @write_subpage: function to write parts of the page covered by ECC.
483 * @write_page: function to write a page according to the ECC generator
485 * @write_oob_raw: function to write chip OOB data without ECC
486 * @read_oob_raw: function to read chip OOB data without ECC
487 * @read_oob: function to read chip OOB data
488 * @write_oob: function to write chip OOB data
490 struct nand_ecc_ctrl {
491 nand_ecc_modes_t mode;
499 struct nand_ecclayout *layout;
501 void (*hwctl)(struct mtd_info *mtd, int mode);
502 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
504 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
506 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
507 uint8_t *buf, int oob_required, int page);
508 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
509 const uint8_t *buf, int oob_required);
510 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
511 uint8_t *buf, int oob_required, int page);
512 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
513 uint32_t offs, uint32_t len, uint8_t *buf, int page);
514 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
515 uint32_t offset, uint32_t data_len,
516 const uint8_t *data_buf, int oob_required);
517 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
518 const uint8_t *buf, int oob_required);
519 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
521 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
523 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
524 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
529 * struct nand_buffers - buffer structure for read/write
530 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
531 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
532 * @databuf: buffer pointer for data, size is (page size + oobsize).
534 * Do not change the order of buffers. databuf and oobrbuf must be in
537 struct nand_buffers {
538 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
539 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
540 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
545 * struct nand_chip - NAND Private Flash Chip Data
546 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
548 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
550 * @read_byte: [REPLACEABLE] read one byte from the chip
551 * @read_word: [REPLACEABLE] read one word from the chip
552 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
554 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
555 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
556 * @select_chip: [REPLACEABLE] select chip nr
557 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
558 * @block_markbad: [REPLACEABLE] mark a block bad
559 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
560 * ALE/CLE/nCE. Also used to write command and address
561 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
562 * mtd->oobsize, mtd->writesize and so on.
563 * @id_data contains the 8 bytes values of NAND_CMD_READID.
564 * Return with the bus width.
565 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
566 * device ready/busy line. If set to NULL no access to
567 * ready/busy is available and the ready/busy information
568 * is read from the chip status register.
569 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
570 * commands to the chip.
571 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
573 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
574 * setting the read-retry mode. Mostly needed for MLC NAND.
575 * @ecc: [BOARDSPECIFIC] ECC control structure
576 * @buffers: buffer structure for read/write
577 * @hwcontrol: platform-specific hardware control structure
578 * @erase_cmd: [INTERN] erase command write function, selectable due
580 * @scan_bbt: [REPLACEABLE] function to scan bad block table
581 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
582 * data from array to read regs (tR).
583 * @state: [INTERN] the current state of the NAND device
584 * @oob_poi: "poison value buffer," used for laying out OOB data
586 * @page_shift: [INTERN] number of address bits in a page (column
588 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
589 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
590 * @chip_shift: [INTERN] number of address bits in one chip
591 * @options: [BOARDSPECIFIC] various chip options. They can partly
592 * be set to inform nand_scan about special functionality.
593 * See the defines for further explanation.
594 * @bbt_options: [INTERN] bad block specific options. All options used
595 * here must come from bbm.h. By default, these options
596 * will be copied to the appropriate nand_bbt_descr's.
597 * @badblockpos: [INTERN] position of the bad block marker in the oob
599 * @badblockbits: [INTERN] minimum number of set bits in a good block's
600 * bad block marker position; i.e., BBM == 11110111b is
601 * not bad when badblockbits == 7
602 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
603 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
604 * Minimum amount of bit errors per @ecc_step_ds guaranteed
605 * to be correctable. If unknown, set to zero.
606 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
607 * also from the datasheet. It is the recommended ECC step
608 * size, if known; if unknown, set to zero.
609 * @numchips: [INTERN] number of physical chips
610 * @chipsize: [INTERN] the size of one chip for multichip arrays
611 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
612 * @pagebuf: [INTERN] holds the pagenumber which is currently in
614 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
615 * currently in data_buf.
616 * @subpagesize: [INTERN] holds the subpagesize
617 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
618 * non 0 if ONFI supported.
619 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
620 * non 0 if JEDEC supported.
621 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
622 * supported, 0 otherwise.
623 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
624 * supported, 0 otherwise.
625 * @read_retries: [INTERN] the number of read retry modes supported
626 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
627 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
628 * @bbt: [INTERN] bad block table pointer
629 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
631 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
632 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
634 * @controller: [REPLACEABLE] a pointer to a hardware controller
635 * structure which is shared among multiple independent
637 * @priv: [OPTIONAL] pointer to private chip data
638 * @errstat: [OPTIONAL] hardware specific function to perform
639 * additional error status checks (determine if errors are
641 * @write_page: [REPLACEABLE] High-level page write function
645 void __iomem *IO_ADDR_R;
646 void __iomem *IO_ADDR_W;
648 uint8_t (*read_byte)(struct mtd_info *mtd);
649 u16 (*read_word)(struct mtd_info *mtd);
650 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
651 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
652 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
653 void (*select_chip)(struct mtd_info *mtd, int chip);
654 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
655 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
656 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
657 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
659 int (*dev_ready)(struct mtd_info *mtd);
660 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
662 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
663 void (*erase_cmd)(struct mtd_info *mtd, int page);
664 int (*scan_bbt)(struct mtd_info *mtd);
665 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
666 int status, int page);
667 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
668 uint32_t offset, int data_len, const uint8_t *buf,
669 int oob_required, int page, int cached, int raw);
670 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
671 int feature_addr, uint8_t *subfeature_para);
672 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
673 int feature_addr, uint8_t *subfeature_para);
674 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
677 unsigned int options;
678 unsigned int bbt_options;
681 int phys_erase_shift;
688 unsigned int pagebuf_bitflips;
690 uint8_t bits_per_cell;
691 uint16_t ecc_strength_ds;
692 uint16_t ecc_step_ds;
698 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
699 struct nand_onfi_params onfi_params;
701 struct nand_jedec_params jedec_params;
708 struct nand_hw_control *controller;
709 struct nand_ecclayout *ecclayout;
711 struct nand_ecc_ctrl ecc;
712 struct nand_buffers *buffers;
713 struct nand_hw_control hwcontrol;
716 struct nand_bbt_descr *bbt_td;
717 struct nand_bbt_descr *bbt_md;
719 struct nand_bbt_descr *badblock_pattern;
725 * NAND Flash Manufacturer ID Codes
727 #define NAND_MFR_TOSHIBA 0x98
728 #define NAND_MFR_SAMSUNG 0xec
729 #define NAND_MFR_FUJITSU 0x04
730 #define NAND_MFR_NATIONAL 0x8f
731 #define NAND_MFR_RENESAS 0x07
732 #define NAND_MFR_STMICRO 0x20
733 #define NAND_MFR_HYNIX 0xad
734 #define NAND_MFR_MICRON 0x2c
735 #define NAND_MFR_AMD 0x01
736 #define NAND_MFR_MACRONIX 0xc2
737 #define NAND_MFR_EON 0x92
738 #define NAND_MFR_SANDISK 0x45
739 #define NAND_MFR_INTEL 0x89
741 /* The maximum expected count of bytes in the NAND ID sequence */
742 #define NAND_MAX_ID_LEN 8
745 * A helper for defining older NAND chips where the second ID byte fully
746 * defined the chip, including the geometry (chip size, eraseblock size, page
747 * size). All these chips have 512 bytes NAND page size.
749 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
750 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
751 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
754 * A helper for defining newer chips which report their page size and
755 * eraseblock size via the extended ID bytes.
757 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
758 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
759 * device ID now only represented a particular total chip size (and voltage,
760 * buswidth), and the page size, eraseblock size, and OOB size could vary while
761 * using the same device ID.
763 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
764 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
767 #define NAND_ECC_INFO(_strength, _step) \
768 { .strength_ds = (_strength), .step_ds = (_step) }
769 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
770 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
773 * struct nand_flash_dev - NAND Flash Device ID Structure
774 * @name: a human-readable name of the NAND chip
775 * @dev_id: the device ID (the second byte of the full chip ID array)
776 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
777 * memory address as @id[0])
778 * @dev_id: device ID part of the full chip ID array (refers the same memory
780 * @id: full device ID array
781 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
782 * well as the eraseblock size) is determined from the extended NAND
784 * @chipsize: total chip size in MiB
785 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
786 * @options: stores various chip bit options
787 * @id_len: The valid length of the @id.
789 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
790 * @ecc_strength_ds in nand_chip{}.
791 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
792 * @ecc_step_ds in nand_chip{}, also from the datasheet.
793 * For example, the "4bit ECC for each 512Byte" can be set with
794 * NAND_ECC_INFO(4, 512).
796 struct nand_flash_dev {
803 uint8_t id[NAND_MAX_ID_LEN];
805 unsigned int pagesize;
806 unsigned int chipsize;
807 unsigned int erasesize;
808 unsigned int options;
812 uint16_t strength_ds;
818 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
819 * @name: Manufacturer name
820 * @id: manufacturer ID code of device.
822 struct nand_manufacturers {
827 extern struct nand_flash_dev nand_flash_ids[];
828 extern struct nand_manufacturers nand_manuf_ids[];
830 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
831 extern int nand_default_bbt(struct mtd_info *mtd);
832 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
833 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
834 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
835 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
837 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
838 size_t *retlen, uint8_t *buf);
841 * Constants for oob configuration
843 #define NAND_SMALL_BADBLOCK_POS 5
844 #define NAND_LARGE_BADBLOCK_POS 0
847 * struct platform_nand_chip - chip level device structure
848 * @nr_chips: max. number of chips to scan for
849 * @chip_offset: chip number offset
850 * @nr_partitions: number of partitions pointed to by partitions (or zero)
851 * @partitions: mtd partition list
852 * @chip_delay: R/B delay value in us
853 * @options: Option flags, e.g. 16bit buswidth
854 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
855 * @ecclayout: ECC layout info structure
856 * @part_probe_types: NULL-terminated array of probe types
858 struct platform_nand_chip {
862 struct mtd_partition *partitions;
863 struct nand_ecclayout *ecclayout;
865 unsigned int options;
866 unsigned int bbt_options;
867 const char **part_probe_types;
871 struct platform_device;
874 * struct platform_nand_ctrl - controller level device structure
875 * @probe: platform specific function to probe/setup hardware
876 * @remove: platform specific function to remove/teardown hardware
877 * @hwcontrol: platform specific hardware control structure
878 * @dev_ready: platform specific function to read ready/busy pin
879 * @select_chip: platform specific chip select function
880 * @cmd_ctrl: platform specific function for controlling
881 * ALE/CLE/nCE. Also used to write command and address
882 * @write_buf: platform specific function for write buffer
883 * @read_buf: platform specific function for read buffer
884 * @read_byte: platform specific function to read one byte from chip
885 * @priv: private data to transport driver specific settings
887 * All fields are optional and depend on the hardware driver requirements
889 struct platform_nand_ctrl {
890 int (*probe)(struct platform_device *pdev);
891 void (*remove)(struct platform_device *pdev);
892 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
893 int (*dev_ready)(struct mtd_info *mtd);
894 void (*select_chip)(struct mtd_info *mtd, int chip);
895 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
896 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
897 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
898 unsigned char (*read_byte)(struct mtd_info *mtd);
903 * struct platform_nand_data - container structure for platform-specific data
904 * @chip: chip level chip structure
905 * @ctrl: controller level device structure
907 struct platform_nand_data {
908 struct platform_nand_chip chip;
909 struct platform_nand_ctrl ctrl;
912 /* Some helpers to access the data structures */
914 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
916 struct nand_chip *chip = mtd->priv;
921 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
922 /* return the supported features. */
923 static inline int onfi_feature(struct nand_chip *chip)
925 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
928 /* return the supported asynchronous timing mode. */
929 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
931 if (!chip->onfi_version)
932 return ONFI_TIMING_MODE_UNKNOWN;
933 return le16_to_cpu(chip->onfi_params.async_timing_mode);
936 /* return the supported synchronous timing mode. */
937 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
939 if (!chip->onfi_version)
940 return ONFI_TIMING_MODE_UNKNOWN;
941 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
946 * Check if it is a SLC nand.
947 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
948 * We do not distinguish the MLC and TLC now.
950 static inline bool nand_is_slc(struct nand_chip *chip)
952 return chip->bits_per_cell == 1;
956 * Check if the opcode's address should be sent only on the lower 8 bits
957 * @command: opcode to check
959 static inline int nand_opcode_8bits(unsigned int command)
962 case NAND_CMD_READID:
964 case NAND_CMD_GET_FEATURES:
965 case NAND_CMD_SET_FEATURES:
973 /* return the supported JEDEC features. */
974 static inline int jedec_feature(struct nand_chip *chip)
976 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
980 /* Standard NAND functions from nand_base.c */
981 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
982 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
983 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
984 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
985 uint8_t nand_read_byte(struct mtd_info *mtd);
986 #endif /* __LINUX_MTD_NAND_H */