]> git.sur5r.net Git - u-boot/blob - include/linux/usb/dwc3.h
USB: XHCI: Add xHCI host controller support for Exynos5
[u-boot] / include / linux / usb / dwc3.h
1 /* include/linux/usb/dwc3.h
2  *
3  * Copyright (c) 2012 Samsung Electronics Co. Ltd
4  *
5  * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __DWC3_H_
11 #define __DWC3_H_
12
13 /* Global constants */
14 #define DWC3_ENDPOINTS_NUM                      32
15
16 #define DWC3_EVENT_BUFFERS_SIZE                 PAGE_SIZE
17 #define DWC3_EVENT_TYPE_MASK                    0xfe
18
19 #define DWC3_EVENT_TYPE_DEV                     0
20 #define DWC3_EVENT_TYPE_CARKIT                  3
21 #define DWC3_EVENT_TYPE_I2C                     4
22
23 #define DWC3_DEVICE_EVENT_DISCONNECT            0
24 #define DWC3_DEVICE_EVENT_RESET                 1
25 #define DWC3_DEVICE_EVENT_CONNECT_DONE          2
26 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE    3
27 #define DWC3_DEVICE_EVENT_WAKEUP                4
28 #define DWC3_DEVICE_EVENT_EOPF                  6
29 #define DWC3_DEVICE_EVENT_SOF                   7
30 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR         9
31 #define DWC3_DEVICE_EVENT_CMD_CMPL              10
32 #define DWC3_DEVICE_EVENT_OVERFLOW              11
33
34 #define DWC3_GEVNTCOUNT_MASK                    0xfffc
35 #define DWC3_GSNPSID_MASK                       0xffff0000
36 #define DWC3_GSNPSID_SHIFT                      16
37 #define DWC3_GSNPSREV_MASK                      0xffff
38
39 #define DWC3_REVISION_MASK                      0xffff
40
41 #define DWC3_REG_OFFSET                         0xC100
42
43 struct g_event_buffer {
44         u64 g_evntadr;
45         u32 g_evntsiz;
46         u32 g_evntcount;
47 };
48
49 struct d_physical_endpoint {
50         u32 d_depcmdpar2;
51         u32 d_depcmdpar1;
52         u32 d_depcmdpar0;
53         u32 d_depcmd;
54 };
55
56 struct dwc3 {                                   /* offset: 0xC100 */
57         u32 g_sbuscfg0;
58         u32 g_sbuscfg1;
59         u32 g_txthrcfg;
60         u32 g_rxthrcfg;
61         u32 g_ctl;
62
63         u32 reserved1;
64
65         u32 g_sts;
66
67         u32 reserved2;
68
69         u32 g_snpsid;
70         u32 g_gpio;
71         u32 g_uid;
72         u32 g_uctl;
73         u64 g_buserraddr;
74         u64 g_prtbimap;
75
76         u32 g_hwparams0;
77         u32 g_hwparams1;
78         u32 g_hwparams2;
79         u32 g_hwparams3;
80         u32 g_hwparams4;
81         u32 g_hwparams5;
82         u32 g_hwparams6;
83         u32 g_hwparams7;
84
85         u32 g_dbgfifospace;
86         u32 g_dbgltssm;
87         u32 g_dbglnmcc;
88         u32 g_dbgbmu;
89         u32 g_dbglspmux;
90         u32 g_dbglsp;
91         u32 g_dbgepinfo0;
92         u32 g_dbgepinfo1;
93
94         u64 g_prtbimap_hs;
95         u64 g_prtbimap_fs;
96
97         u32 reserved3[28];
98
99         u32 g_usb2phycfg[16];
100         u32 g_usb2i2cctl[16];
101         u32 g_usb2phyacc[16];
102         u32 g_usb3pipectl[16];
103
104         u32 g_txfifosiz[32];
105         u32 g_rxfifosiz[32];
106
107         struct g_event_buffer g_evnt_buf[32];
108
109         u32 g_hwparams8;
110
111         u32 reserved4[63];
112
113         u32 d_cfg;
114         u32 d_ctl;
115         u32 d_evten;
116         u32 d_sts;
117         u32 d_gcmdpar;
118         u32 d_gcmd;
119
120         u32 reserved5[2];
121
122         u32 d_alepena;
123
124         u32 reserved6[55];
125
126         struct d_physical_endpoint d_phy_ep_cmd[32];
127
128         u32 reserved7[128];
129
130         u32 o_cfg;
131         u32 o_ctl;
132         u32 o_evt;
133         u32 o_evten;
134         u32 o_sts;
135
136         u32 reserved8[3];
137
138         u32 adp_cfg;
139         u32 adp_ctl;
140         u32 adp_evt;
141         u32 adp_evten;
142
143         u32 bc_cfg;
144
145         u32 reserved9;
146
147         u32 bc_evt;
148         u32 bc_evten;
149 };
150
151 /* Global Configuration Register */
152 #define DWC3_GCTL_PWRDNSCALE(n)                 ((n) << 19)
153 #define DWC3_GCTL_U2RSTECN                      (1 << 16)
154 #define DWC3_GCTL_RAMCLKSEL(x)                  \
155                 (((x) & DWC3_GCTL_CLK_MASK) << 6)
156 #define DWC3_GCTL_CLK_BUS                       (0)
157 #define DWC3_GCTL_CLK_PIPE                      (1)
158 #define DWC3_GCTL_CLK_PIPEHALF                  (2)
159 #define DWC3_GCTL_CLK_MASK                      (3)
160 #define DWC3_GCTL_PRTCAP(n)                     (((n) & (3 << 12)) >> 12)
161 #define DWC3_GCTL_PRTCAPDIR(n)                  ((n) << 12)
162 #define DWC3_GCTL_PRTCAP_HOST                   1
163 #define DWC3_GCTL_PRTCAP_DEVICE                 2
164 #define DWC3_GCTL_PRTCAP_OTG                    3
165 #define DWC3_GCTL_CORESOFTRESET                 (1 << 11)
166 #define DWC3_GCTL_SCALEDOWN(n)                  ((n) << 4)
167 #define DWC3_GCTL_SCALEDOWN_MASK                DWC3_GCTL_SCALEDOWN(3)
168 #define DWC3_GCTL_DISSCRAMBLE                   (1 << 3)
169 #define DWC3_GCTL_DSBLCLKGTNG                   (1 << 0)
170
171 /* Global HWPARAMS1 Register */
172 #define DWC3_GHWPARAMS1_EN_PWROPT(n)            (((n) & (3 << 24)) >> 24)
173 #define DWC3_GHWPARAMS1_EN_PWROPT_NO            0
174 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK           1
175
176 /* Global USB2 PHY Configuration Register */
177 #define DWC3_GUSB2PHYCFG_PHYSOFTRST             (1 << 31)
178 #define DWC3_GUSB2PHYCFG_SUSPHY                 (1 << 6)
179
180 /* Global USB3 PIPE Control Register */
181 #define DWC3_GUSB3PIPECTL_PHYSOFTRST            (1 << 31)
182 #define DWC3_GUSB3PIPECTL_SUSPHY                (1 << 17)
183
184 /* Global TX Fifo Size Register */
185 #define DWC3_GTXFIFOSIZ_TXFDEF(n)               ((n) & 0xffff)
186 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)            ((n) & 0xffff0000)
187
188 #endif /* __DWC3_H_ */