3 * Texas Instruments Inc, <www.ti.com>
5 * Author: Dan Murphy <dmurphy@ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _ASM_ARCH_XHCI_OMAP_H_
11 #define _ASM_ARCH_XHCI_OMAP_H_
13 #define OMAP_XHCI_BASE 0x4a030000
14 #define OMAP_OCP1_SCP_BASE 0x4a084c00
15 #define OMAP_OTG_WRAPPER_BASE 0x4A020000
17 /* Phy register MACRO definitions */
18 #define PLL_REGM_MASK 0x001FFE00
19 #define PLL_REGM_SHIFT 0x9
20 #define PLL_REGM_F_MASK 0x0003FFFF
21 #define PLL_REGM_F_SHIFT 0x0
22 #define PLL_REGN_MASK 0x000001FE
23 #define PLL_REGN_SHIFT 0x1
24 #define PLL_SELFREQDCO_MASK 0x0000000E
25 #define PLL_SELFREQDCO_SHIFT 0x1
26 #define PLL_SD_MASK 0x0003FC00
27 #define PLL_SD_SHIFT 0x9
28 #define SET_PLL_GO 0x1
29 #define PLL_TICOPWDN 0x10000
33 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
34 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
35 #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6)
36 #define USB3_PHY_RX_POWERON (1 << 14)
37 #define USB3_PHY_TX_POWERON (1 << 15)
38 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
39 #define USB3_PWRCTL_CLK_CMD_SHIFT 14
40 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22
42 /* USBOTGSS_WRAPPER definitions */
43 #define USBOTGSS_WRAPRESET (1 << 17)
44 #define USBOTGSS_DMADISABLE (1 << 16)
45 #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
46 #define USBOTGSS_STANDBYMODE_SMRT (1 << 5)
47 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
48 #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
49 #define USBOTGSS_IDLEMODE_SMRT (1 << 3)
50 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
52 /* USBOTGSS_IRQENABLE_SET_0 bit */
53 #define USBOTGSS_COREIRQ_EN (1 << 0)
55 /* USBOTGSS_IRQENABLE_SET_1 bits */
56 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0)
57 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3)
58 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4)
59 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5)
60 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8)
61 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11)
62 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12)
63 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13)
64 #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16)
65 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17)
68 * USBOTGSS_WRAPPER registers
70 struct omap_dwc_wrapper {
75 u32 sysconfig; /* offset of 0x10 */
80 u32 irqstatus_raw_0; /* offset of 0x24 */
85 u32 irqstatus_raw_1; /* offset of 0x34 */
92 u32 utmi_otg_ctrl; /* offset of 0x80 */
97 u32 mram_offset; /* offset of 0x100 */
104 /* XHCI PHY register structure */
105 struct omap_usb3_phy {
112 u32 pll_ssc_config_1;
113 u32 pll_ssc_config_2;
118 struct omap_dwc_wrapper *otg_wrapper;
119 struct omap_usb3_phy *usb3_phy;
120 struct xhci_hccr *hcd;
121 struct dwc3 *dwc3_reg;
124 /* USB PHY functions */
125 void omap_enable_phy_clocks(struct omap_xhci *omap);
126 void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs);
127 void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
128 void usb3_phy_power(int on);
130 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */