git.sur5r.net Git - u-boot/blob - include/mb862xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
  26  */
  27
  28 #ifndef _MB862XX_H_
  29 #define _MB862XX_H_
  30
  31 #define PCI_VENDOR_ID_FUJITSU   0x10CF
  32 #define PCI_DEVICE_ID_CORAL_P   0x2019
  33 #define PCI_DEVICE_ID_CORAL_PA  0x201E
  34
  35 #define MB862XX_TYPE_LIME       0x1
  36
  37 #define GC_HOST_BASE            0x01fc0000
  38 #define GC_DISP_BASE            0x01fd0000
  39 #define GC_DRAW_BASE            0x01ff0000
  40
  41 /* Host interface registers */
  42 #define GC_SRST                 0x0000002c
  43 #define GC_CCF                  0x00000038
  44 #define GC_CID                  0x000000f0
  45 #define GC_MMR                  0x0000fffc
  46
  47 /*
  48  * Display Controller registers
  49  * _A means the offset is aligned, we use these for boards
  50  * with 8-/16-bit GDC access not working or buggy.
  51  */
  52 #define GC_DCM0                 0x00000000
  53 #define GC_HTP_A                0x00000004
  54 #define GC_HTP                  0x00000006
  55 #define GC_HDB_HDP_A            0x00000008
  56 #define GC_HDP                  0x00000008
  57 #define GC_HDB                  0x0000000a
  58 #define GC_VSW_HSW_HSP_A        0x0000000c
  59 #define GC_HSP                  0x0000000c
  60 #define GC_HSW                  0x0000000e
  61 #define GC_VSW                  0x0000000f
  62 #define GC_VTR_A                0x00000010
  63 #define GC_VTR                  0x00000012
  64 #define GC_VDP_VSP_A            0x00000014
  65 #define GC_VSP                  0x00000014
  66 #define GC_VDP                  0x00000016
  67 #define GC_WY_WX                0x00000018
  68 #define GC_WH_WW                0x0000001c
  69 #define GC_L0M                  0x00000020
  70 #define GC_L0OA0                0x00000024
  71 #define GC_L0DA0                0x00000028
  72 #define GC_L0DY_L0DX            0x0000002c
  73 #define GC_L2M                  0x00000040
  74 #define GC_L2OA0                0x00000044
  75 #define GC_L2DA0                0x00000048
  76 #define GC_L2OA1                0x0000004c
  77 #define GC_L2DA1                0x00000050
  78 #define GC_L2DX                 0x00000054
  79 #define GC_L2DY                 0x00000056
  80 #define GC_DCM1                 0x00000100
  81 #define GC_DCM2                 0x00000104
  82 #define GC_DCM3                 0x00000108
  83 #define GC_L0EM                 0x00000110
  84 #define GC_L0WY_L0WX            0x00000114
  85 #define GC_L0WH_L0WW            0x00000118
  86 #define GC_L2EM                 0x00000130
  87 #define GC_L2WX                 0x00000134
  88 #define GC_L2WY                 0x00000136
  89 #define GC_L2WW                 0x00000138
  90 #define GC_L2WH                 0x0000013a
  91 #define GC_L0PAL0               0x00000400
  92
  93 /* Drawing registers */
  94 #define GC_CTR                  0x00000400
  95 #define GC_IFCNT                0x00000408
  96 #define GC_FBR                  0x00000440
  97 #define GC_XRES                 0x00000444
  98 #define GC_CXMIN                0x00000454
  99 #define GC_CXMAX                0x00000458
 100 #define GC_CYMIN                0x0000045c
 101 #define GC_CYMAX                0x00000460
 102 #define GC_FC                   0x00000480
 103 #define GC_BC                   0x00000484
 104 #define GC_FIFO                 0x000004a0
 105 #define GC_REV                  0x00008084
 106 #define GC_GEO_FIFO             0x00008400
 107
 108 typedef struct {
 109         unsigned int index;
 110         unsigned int value;
 111 } gdc_regs;
 112
 113 int mb862xx_probe(unsigned int addr);
 114 const gdc_regs *board_get_regs (void);
 115 unsigned int board_video_init (void);
 116 void board_backlight_switch(int);
 117
 118 #endif /* _MB862XX_H_ */