git.sur5r.net Git - u-boot/blob - include/mb862xx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2007
   4  * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
   5  */
   6
   7 /*
   8  * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
   9  */
  10
  11 #ifndef _MB862XX_H_
  12 #define _MB862XX_H_
  13
  14 #define PCI_VENDOR_ID_FUJITSU   0x10CF
  15 #define PCI_DEVICE_ID_CORAL_P   0x2019
  16 #define PCI_DEVICE_ID_CORAL_PA  0x201E
  17
  18 #define MB862XX_TYPE_LIME       0x1
  19
  20 #define GC_HOST_BASE            0x01fc0000
  21 #define GC_DISP_BASE            0x01fd0000
  22 #define GC_DRAW_BASE            0x01ff0000
  23
  24 /* Host interface registers */
  25 #define GC_SRST                 0x0000002c
  26 #define GC_CCF                  0x00000038
  27 #define GC_CID                  0x000000f0
  28 #define GC_MMR                  0x0000fffc
  29
  30 /*
  31  * Display Controller registers
  32  * _A means the offset is aligned, we use these for boards
  33  * with 8-/16-bit GDC access not working or buggy.
  34  */
  35 #define GC_DCM0                 0x00000000
  36 #define GC_HTP_A                0x00000004
  37 #define GC_HTP                  0x00000006
  38 #define GC_HDB_HDP_A            0x00000008
  39 #define GC_HDP                  0x00000008
  40 #define GC_HDB                  0x0000000a
  41 #define GC_VSW_HSW_HSP_A        0x0000000c
  42 #define GC_HSP                  0x0000000c
  43 #define GC_HSW                  0x0000000e
  44 #define GC_VSW                  0x0000000f
  45 #define GC_VTR_A                0x00000010
  46 #define GC_VTR                  0x00000012
  47 #define GC_VDP_VSP_A            0x00000014
  48 #define GC_VSP                  0x00000014
  49 #define GC_VDP                  0x00000016
  50 #define GC_WY_WX                0x00000018
  51 #define GC_WH_WW                0x0000001c
  52 #define GC_L0M                  0x00000020
  53 #define GC_L0OA0                0x00000024
  54 #define GC_L0DA0                0x00000028
  55 #define GC_L0DY_L0DX            0x0000002c
  56 #define GC_L2M                  0x00000040
  57 #define GC_L2OA0                0x00000044
  58 #define GC_L2DA0                0x00000048
  59 #define GC_L2OA1                0x0000004c
  60 #define GC_L2DA1                0x00000050
  61 #define GC_L2DX                 0x00000054
  62 #define GC_L2DY                 0x00000056
  63 #define GC_DCM1                 0x00000100
  64 #define GC_DCM2                 0x00000104
  65 #define GC_DCM3                 0x00000108
  66 #define GC_L0EM                 0x00000110
  67 #define GC_L0WY_L0WX            0x00000114
  68 #define GC_L0WH_L0WW            0x00000118
  69 #define GC_L2EM                 0x00000130
  70 #define GC_L2WX                 0x00000134
  71 #define GC_L2WY                 0x00000136
  72 #define GC_L2WW                 0x00000138
  73 #define GC_L2WH                 0x0000013a
  74 #define GC_L0PAL0               0x00000400
  75
  76 /* Drawing registers */
  77 #define GC_CTR                  0x00000400
  78 #define GC_IFCNT                0x00000408
  79 #define GC_FBR                  0x00000440
  80 #define GC_XRES                 0x00000444
  81 #define GC_CXMIN                0x00000454
  82 #define GC_CXMAX                0x00000458
  83 #define GC_CYMIN                0x0000045c
  84 #define GC_CYMAX                0x00000460
  85 #define GC_FC                   0x00000480
  86 #define GC_BC                   0x00000484
  87 #define GC_FIFO                 0x000004a0
  88 #define GC_REV                  0x00008084
  89 #define GC_GEO_FIFO             0x00008400
  90
  91 typedef struct {
  92         unsigned int index;
  93         unsigned int value;
  94 } gdc_regs;
  95
  96 int mb862xx_probe(unsigned int addr);
  97 const gdc_regs *board_get_regs (void);
  98 unsigned int board_video_init (void);
  99 void board_backlight_switch(int);
 100
 101 #endif /* _MB862XX_H_ */