2 * include/asm-ppc/mpc5xxx.h
4 * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #ifndef __ASMPPC_MPC5XXX_H
31 #define __ASMPPC_MPC5XXX_H
34 #if defined(CONFIG_MPC5200)
35 #define CPU_ID_STR "MPC5200"
36 #elif defined(CONFIG_MGT5100)
37 #define CPU_ID_STR "MGT5100"
40 /* Exception offsets (PowerPC standard) */
41 #define EXC_OFF_SYS_RESET 0x0100
42 #define _START_OFFSET EXC_OFF_SYS_RESET
44 /* useful macros for manipulating CSx_START/STOP */
45 #if defined(CONFIG_MGT5100)
46 #define START_REG(start) ((start) >> 15)
47 #define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
48 #elif defined(CONFIG_MPC5200)
49 #define START_REG(start) ((start) >> 16)
50 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
53 /* Internal memory map */
55 #define MPC5XXX_CS0_START (CFG_MBAR + 0x0004)
56 #define MPC5XXX_CS0_STOP (CFG_MBAR + 0x0008)
57 #define MPC5XXX_CS1_START (CFG_MBAR + 0x000c)
58 #define MPC5XXX_CS1_STOP (CFG_MBAR + 0x0010)
59 #define MPC5XXX_CS2_START (CFG_MBAR + 0x0014)
60 #define MPC5XXX_CS2_STOP (CFG_MBAR + 0x0018)
61 #define MPC5XXX_CS3_START (CFG_MBAR + 0x001c)
62 #define MPC5XXX_CS3_STOP (CFG_MBAR + 0x0020)
63 #define MPC5XXX_CS4_START (CFG_MBAR + 0x0024)
64 #define MPC5XXX_CS4_STOP (CFG_MBAR + 0x0028)
65 #define MPC5XXX_CS5_START (CFG_MBAR + 0x002c)
66 #define MPC5XXX_CS5_STOP (CFG_MBAR + 0x0030)
67 #define MPC5XXX_BOOTCS_START (CFG_MBAR + 0x004c)
68 #define MPC5XXX_BOOTCS_STOP (CFG_MBAR + 0x0050)
69 #define MPC5XXX_ADDECR (CFG_MBAR + 0x0054)
71 #if defined(CONFIG_MGT5100)
72 #define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
73 #define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
74 #define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
75 #define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
76 #define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
77 #define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
78 #elif defined(CONFIG_MPC5200)
79 #define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
80 #define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
81 #define MPC5XXX_CS7_START (CFG_MBAR + 0x0060)
82 #define MPC5XXX_CS7_STOP (CFG_MBAR + 0x0064)
83 #define MPC5XXX_SDRAM_CS0CFG (CFG_MBAR + 0x0034)
84 #define MPC5XXX_SDRAM_CS1CFG (CFG_MBAR + 0x0038)
87 #define MPC5XXX_SDRAM (CFG_MBAR + 0x0100)
88 #define MPC5XXX_CDM (CFG_MBAR + 0x0200)
89 #define MPC5XXX_LPB (CFG_MBAR + 0x0300)
90 #define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
91 #define MPC5XXX_GPT (CFG_MBAR + 0x0600)
92 #define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
93 #define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00)
94 #define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
95 #define MPC5XXX_SPI (CFG_MBAR + 0x0f00)
96 #define MPC5XXX_USB (CFG_MBAR + 0x1000)
97 #define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
98 #define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
100 #if defined(CONFIG_MGT5100)
101 #define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
102 #define MPC5XXX_PSC2 (CFG_MBAR + 0x2400)
103 #define MPC5XXX_PSC3 (CFG_MBAR + 0x2800)
104 #elif defined(CONFIG_MPC5200)
105 #define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
106 #define MPC5XXX_PSC2 (CFG_MBAR + 0x2200)
107 #define MPC5XXX_PSC3 (CFG_MBAR + 0x2400)
108 #define MPC5XXX_PSC4 (CFG_MBAR + 0x2600)
109 #define MPC5XXX_PSC5 (CFG_MBAR + 0x2800)
110 #define MPC5XXX_PSC6 (CFG_MBAR + 0x2c00)
113 #define MPC5XXX_FEC (CFG_MBAR + 0x3000)
114 #define MPC5XXX_ATA (CFG_MBAR + 0x3A00)
116 #define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00)
117 #define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40)
119 #if defined(CONFIG_MGT5100)
120 #define MPC5XXX_SRAM (CFG_MBAR + 0x4000)
121 #define MPC5XXX_SRAM_SIZE (8*1024)
122 #elif defined(CONFIG_MPC5200)
123 #define MPC5XXX_SRAM (CFG_MBAR + 0x8000)
124 #define MPC5XXX_SRAM_SIZE (16*1024)
127 /* SDRAM Controller */
128 #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
129 #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
130 #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
131 #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
132 #if defined(CONFIG_MGT5100)
133 #define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
135 #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
137 /* Clock Distribution Module */
138 #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
139 #define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
140 #define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
141 #define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
142 #define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
144 /* Local Plus Bus interface */
145 #define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
146 #define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
147 #define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
148 #define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
149 #define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
150 #define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
151 #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
152 #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
153 #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
154 #if defined(CONFIG_MPC5200)
155 #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
156 #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
157 #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
158 #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
161 #if defined(CONFIG_MPC5200)
162 /* XLB Arbiter registers */
163 #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
164 #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
165 #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
169 #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
171 /* Standard GPIO registers (simple, output only and simple interrupt */
172 #define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
173 #define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008)
174 #define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c)
175 #define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010)
176 #define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014)
177 #define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018)
178 #define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C)
179 #define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020)
180 #define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024)
181 #define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028)
182 #define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C)
183 #define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030)
184 #define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034)
185 #define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038)
186 #define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C)
188 /* WakeUp GPIO registers */
189 #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
190 #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
191 #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
192 #define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
193 #define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
196 #define GPIO_WKUP_7 0x80000000UL
197 #define GPIO_PSC6_0 0x10000000UL
198 #define GPIO_PSC3_9 0x04000000UL
199 #define GPIO_PSC1_4 0x01000000UL
202 #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
203 #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
204 #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
205 #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
206 #if defined(CONFIG_MGT5100)
207 #define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
208 #define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
209 #define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
210 #define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
211 #define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
212 #define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
213 #elif defined(CONFIG_MPC5200)
214 #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
215 #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
216 #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
217 #define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
218 #define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
219 #define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
220 #define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
221 #define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
222 #define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
223 #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
224 #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
225 #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
228 /* Interrupt Controller registers */
229 #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
230 #define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
231 #define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
232 #define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
233 #define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
234 #define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
235 #define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
236 #define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
237 #define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
238 #define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
239 #define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
240 #define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
241 #define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
245 /* IRQ mapping - these are our logical IRQ numbers */
246 #define MPC5XXX_CRIT_IRQ_NUM 4
247 #define MPC5XXX_MAIN_IRQ_NUM 17
248 #define MPC5XXX_SDMA_IRQ_NUM 17
249 #define MPC5XXX_PERP_IRQ_NUM 23
251 #define MPC5XXX_CRIT_IRQ_BASE 1
252 #define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
253 #define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
254 #define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
256 #define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
257 #define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
258 #define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
259 #define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
261 #define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
262 #define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
263 #define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
264 #define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
265 #define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
266 #define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
267 #define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
268 #define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
269 #define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
270 #define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
271 #define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
272 #define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
273 #define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
274 #define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
275 #define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
277 #define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
278 #define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
279 #define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
280 #define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
281 #define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
282 #define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
283 #define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
284 #define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
285 #define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
286 #define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
287 #define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
288 #define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
289 #define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
290 #define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
291 #define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
292 #define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
293 #define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
294 #define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
295 #define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
296 #define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
297 #define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
298 #define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
299 #define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
300 #define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
302 /* General Purpose Timers registers */
303 #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
304 #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
305 #define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
306 #define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
307 #define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
308 #define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
309 #define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
310 #define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
311 #define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
312 #define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
313 #define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
314 #define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
315 #define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
316 #define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
317 #define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
318 #define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
319 #define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
320 #define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
321 #define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
322 #define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
323 #define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
324 #define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
325 #define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
326 #define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
328 #define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
330 #define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
333 #define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
334 #define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
335 #define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
336 #define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
338 /* I2Cn control register bits */
343 #define I2C_TXAK 0x08
344 #define I2C_RSTA 0x04
345 #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
347 /* I2Cn status register bits */
354 #define I2C_RXAK 0x01
356 /* Programmable Serial Controller (PSC) status register bits */
357 #define PSC_SR_CDE 0x0080
358 #define PSC_SR_RXRDY 0x0100
359 #define PSC_SR_RXFULL 0x0200
360 #define PSC_SR_TXRDY 0x0400
361 #define PSC_SR_TXEMP 0x0800
362 #define PSC_SR_OE 0x1000
363 #define PSC_SR_PE 0x2000
364 #define PSC_SR_FE 0x4000
365 #define PSC_SR_RB 0x8000
367 /* PSC Command values */
368 #define PSC_RX_ENABLE 0x0001
369 #define PSC_RX_DISABLE 0x0002
370 #define PSC_TX_ENABLE 0x0004
371 #define PSC_TX_DISABLE 0x0008
372 #define PSC_SEL_MODE_REG_1 0x0010
373 #define PSC_RST_RX 0x0020
374 #define PSC_RST_TX 0x0030
375 #define PSC_RST_ERR_STAT 0x0040
376 #define PSC_RST_BRK_CHG_INT 0x0050
377 #define PSC_START_BRK 0x0060
378 #define PSC_STOP_BRK 0x0070
380 /* PSC Rx FIFO status bits */
381 #define PSC_RX_FIFO_ERR 0x0040
382 #define PSC_RX_FIFO_UF 0x0020
383 #define PSC_RX_FIFO_OF 0x0010
384 #define PSC_RX_FIFO_FR 0x0008
385 #define PSC_RX_FIFO_FULL 0x0004
386 #define PSC_RX_FIFO_ALARM 0x0002
387 #define PSC_RX_FIFO_EMPTY 0x0001
389 /* PSC interrupt mask bits */
390 #define PSC_IMR_TXRDY 0x0100
391 #define PSC_IMR_RXRDY 0x0200
392 #define PSC_IMR_DB 0x0400
393 #define PSC_IMR_IPC 0x8000
395 /* PSC input port change bits */
396 #define PSC_IPCR_CTS 0x01
397 #define PSC_IPCR_DCD 0x02
399 /* PSC mode fields */
400 #define PSC_MODE_5_BITS 0x00
401 #define PSC_MODE_6_BITS 0x01
402 #define PSC_MODE_7_BITS 0x02
403 #define PSC_MODE_8_BITS 0x03
404 #define PSC_MODE_PAREVEN 0x00
405 #define PSC_MODE_PARODD 0x04
406 #define PSC_MODE_PARFORCE 0x08
407 #define PSC_MODE_PARNONE 0x10
408 #define PSC_MODE_ERR 0x20
409 #define PSC_MODE_FFULL 0x40
410 #define PSC_MODE_RXRTS 0x80
412 #define PSC_MODE_ONE_STOP_5_BITS 0x00
413 #define PSC_MODE_ONE_STOP 0x07
414 #define PSC_MODE_TWO_STOP 0x0f
416 /* ATA config fields */
417 #define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
419 #define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
420 #define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
422 #define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
427 volatile u8 mode; /* PSC + 0x00 */
428 volatile u8 reserved0[3];
429 union { /* PSC + 0x04 */
431 volatile u16 clock_select;
433 #define psc_status sr_csr.status
434 #define psc_clock_select sr_csr.clock_select
435 volatile u16 reserved1;
436 volatile u8 command; /* PSC + 0x08 */
437 volatile u8 reserved2[3];
438 union { /* PSC + 0x0c */
439 volatile u8 buffer_8;
440 volatile u16 buffer_16;
441 volatile u32 buffer_32;
443 #define psc_buffer_8 buffer.buffer_8
444 #define psc_buffer_16 buffer.buffer_16
445 #define psc_buffer_32 buffer.buffer_32
446 union { /* PSC + 0x10 */
450 #define psc_ipcr ipcr_acr.ipcr
451 #define psc_acr ipcr_acr.acr
452 volatile u8 reserved3[3];
453 union { /* PSC + 0x14 */
457 #define psc_isr isr_imr.isr
458 #define psc_imr isr_imr.imr
459 volatile u16 reserved4;
460 volatile u8 ctur; /* PSC + 0x18 */
461 volatile u8 reserved5[3];
462 volatile u8 ctlr; /* PSC + 0x1c */
463 volatile u8 reserved6[3];
464 volatile u16 ccr; /* PSC + 0x20 */
465 volatile u8 reserved7[14];
466 volatile u8 ivr; /* PSC + 0x30 */
467 volatile u8 reserved8[3];
468 volatile u8 ip; /* PSC + 0x34 */
469 volatile u8 reserved9[3];
470 volatile u8 op1; /* PSC + 0x38 */
471 volatile u8 reserved10[3];
472 volatile u8 op0; /* PSC + 0x3c */
473 volatile u8 reserved11[3];
474 volatile u32 sicr; /* PSC + 0x40 */
475 volatile u8 ircr1; /* PSC + 0x44 */
476 volatile u8 reserved12[3];
477 volatile u8 ircr2; /* PSC + 0x44 */
478 volatile u8 reserved13[3];
479 volatile u8 irsdr; /* PSC + 0x4c */
480 volatile u8 reserved14[3];
481 volatile u8 irmdr; /* PSC + 0x50 */
482 volatile u8 reserved15[3];
483 volatile u8 irfdr; /* PSC + 0x54 */
484 volatile u8 reserved16[3];
485 volatile u16 rfnum; /* PSC + 0x58 */
486 volatile u16 reserved17;
487 volatile u16 tfnum; /* PSC + 0x5c */
488 volatile u16 reserved18;
489 volatile u32 rfdata; /* PSC + 0x60 */
490 volatile u16 rfstat; /* PSC + 0x64 */
491 volatile u16 reserved20;
492 volatile u8 rfcntl; /* PSC + 0x68 */
493 volatile u8 reserved21[5];
494 volatile u16 rfalarm; /* PSC + 0x6e */
495 volatile u16 reserved22;
496 volatile u16 rfrptr; /* PSC + 0x72 */
497 volatile u16 reserved23;
498 volatile u16 rfwptr; /* PSC + 0x76 */
499 volatile u16 reserved24;
500 volatile u16 rflrfptr; /* PSC + 0x7a */
501 volatile u16 reserved25;
502 volatile u16 rflwfptr; /* PSC + 0x7e */
503 volatile u32 tfdata; /* PSC + 0x80 */
504 volatile u16 tfstat; /* PSC + 0x84 */
505 volatile u16 reserved26;
506 volatile u8 tfcntl; /* PSC + 0x88 */
507 volatile u8 reserved27[5];
508 volatile u16 tfalarm; /* PSC + 0x8e */
509 volatile u16 reserved28;
510 volatile u16 tfrptr; /* PSC + 0x92 */
511 volatile u16 reserved29;
512 volatile u16 tfwptr; /* PSC + 0x96 */
513 volatile u16 reserved30;
514 volatile u16 tflrfptr; /* PSC + 0x9a */
515 volatile u16 reserved31;
516 volatile u16 tflwfptr; /* PSC + 0x9e */
519 struct mpc5xxx_intr {
520 volatile u32 per_mask; /* INTR + 0x00 */
521 volatile u32 per_pri1; /* INTR + 0x04 */
522 volatile u32 per_pri2; /* INTR + 0x08 */
523 volatile u32 per_pri3; /* INTR + 0x0c */
524 volatile u32 ctrl; /* INTR + 0x10 */
525 volatile u32 main_mask; /* INTR + 0x14 */
526 volatile u32 main_pri1; /* INTR + 0x18 */
527 volatile u32 main_pri2; /* INTR + 0x1c */
528 volatile u32 reserved1; /* INTR + 0x20 */
529 volatile u32 enc_status; /* INTR + 0x24 */
530 volatile u32 crit_status; /* INTR + 0x28 */
531 volatile u32 main_status; /* INTR + 0x2c */
532 volatile u32 per_status; /* INTR + 0x30 */
533 volatile u32 reserved2; /* INTR + 0x34 */
534 volatile u32 per_error; /* INTR + 0x38 */
537 struct mpc5xxx_gpio {
538 volatile u32 port_config; /* GPIO + 0x00 */
539 volatile u32 simple_gpioe; /* GPIO + 0x04 */
540 volatile u32 simple_ode; /* GPIO + 0x08 */
541 volatile u32 simple_ddr; /* GPIO + 0x0c */
542 volatile u32 simple_dvo; /* GPIO + 0x10 */
543 volatile u32 simple_ival; /* GPIO + 0x14 */
544 volatile u8 outo_gpioe; /* GPIO + 0x18 */
545 volatile u8 reserved1[3]; /* GPIO + 0x19 */
546 volatile u8 outo_dvo; /* GPIO + 0x1c */
547 volatile u8 reserved2[3]; /* GPIO + 0x1d */
548 volatile u8 sint_gpioe; /* GPIO + 0x20 */
549 volatile u8 reserved3[3]; /* GPIO + 0x21 */
550 volatile u8 sint_ode; /* GPIO + 0x24 */
551 volatile u8 reserved4[3]; /* GPIO + 0x25 */
552 volatile u8 sint_ddr; /* GPIO + 0x28 */
553 volatile u8 reserved5[3]; /* GPIO + 0x29 */
554 volatile u8 sint_dvo; /* GPIO + 0x2c */
555 volatile u8 reserved6[3]; /* GPIO + 0x2d */
556 volatile u8 sint_inten; /* GPIO + 0x30 */
557 volatile u8 reserved7[3]; /* GPIO + 0x31 */
558 volatile u16 sint_itype; /* GPIO + 0x34 */
559 volatile u16 reserved8; /* GPIO + 0x36 */
560 volatile u8 gpio_control; /* GPIO + 0x38 */
561 volatile u8 reserved9[3]; /* GPIO + 0x39 */
562 volatile u8 sint_istat; /* GPIO + 0x3c */
563 volatile u8 sint_ival; /* GPIO + 0x3d */
564 volatile u8 bus_errs; /* GPIO + 0x3e */
565 volatile u8 reserved10; /* GPIO + 0x3f */
568 struct mpc5xxx_sdma {
569 volatile u32 taskBar; /* SDMA + 0x00 */
570 volatile u32 currentPointer; /* SDMA + 0x04 */
571 volatile u32 endPointer; /* SDMA + 0x08 */
572 volatile u32 variablePointer; /* SDMA + 0x0c */
574 volatile u8 IntVect1; /* SDMA + 0x10 */
575 volatile u8 IntVect2; /* SDMA + 0x11 */
576 volatile u16 PtdCntrl; /* SDMA + 0x12 */
578 volatile u32 IntPend; /* SDMA + 0x14 */
579 volatile u32 IntMask; /* SDMA + 0x18 */
581 volatile u16 tcr_0; /* SDMA + 0x1c */
582 volatile u16 tcr_1; /* SDMA + 0x1e */
583 volatile u16 tcr_2; /* SDMA + 0x20 */
584 volatile u16 tcr_3; /* SDMA + 0x22 */
585 volatile u16 tcr_4; /* SDMA + 0x24 */
586 volatile u16 tcr_5; /* SDMA + 0x26 */
587 volatile u16 tcr_6; /* SDMA + 0x28 */
588 volatile u16 tcr_7; /* SDMA + 0x2a */
589 volatile u16 tcr_8; /* SDMA + 0x2c */
590 volatile u16 tcr_9; /* SDMA + 0x2e */
591 volatile u16 tcr_a; /* SDMA + 0x30 */
592 volatile u16 tcr_b; /* SDMA + 0x32 */
593 volatile u16 tcr_c; /* SDMA + 0x34 */
594 volatile u16 tcr_d; /* SDMA + 0x36 */
595 volatile u16 tcr_e; /* SDMA + 0x38 */
596 volatile u16 tcr_f; /* SDMA + 0x3a */
598 volatile u8 IPR0; /* SDMA + 0x3c */
599 volatile u8 IPR1; /* SDMA + 0x3d */
600 volatile u8 IPR2; /* SDMA + 0x3e */
601 volatile u8 IPR3; /* SDMA + 0x3f */
602 volatile u8 IPR4; /* SDMA + 0x40 */
603 volatile u8 IPR5; /* SDMA + 0x41 */
604 volatile u8 IPR6; /* SDMA + 0x42 */
605 volatile u8 IPR7; /* SDMA + 0x43 */
606 volatile u8 IPR8; /* SDMA + 0x44 */
607 volatile u8 IPR9; /* SDMA + 0x45 */
608 volatile u8 IPR10; /* SDMA + 0x46 */
609 volatile u8 IPR11; /* SDMA + 0x47 */
610 volatile u8 IPR12; /* SDMA + 0x48 */
611 volatile u8 IPR13; /* SDMA + 0x49 */
612 volatile u8 IPR14; /* SDMA + 0x4a */
613 volatile u8 IPR15; /* SDMA + 0x4b */
614 volatile u8 IPR16; /* SDMA + 0x4c */
615 volatile u8 IPR17; /* SDMA + 0x4d */
616 volatile u8 IPR18; /* SDMA + 0x4e */
617 volatile u8 IPR19; /* SDMA + 0x4f */
618 volatile u8 IPR20; /* SDMA + 0x50 */
619 volatile u8 IPR21; /* SDMA + 0x51 */
620 volatile u8 IPR22; /* SDMA + 0x52 */
621 volatile u8 IPR23; /* SDMA + 0x53 */
622 volatile u8 IPR24; /* SDMA + 0x54 */
623 volatile u8 IPR25; /* SDMA + 0x55 */
624 volatile u8 IPR26; /* SDMA + 0x56 */
625 volatile u8 IPR27; /* SDMA + 0x57 */
626 volatile u8 IPR28; /* SDMA + 0x58 */
627 volatile u8 IPR29; /* SDMA + 0x59 */
628 volatile u8 IPR30; /* SDMA + 0x5a */
629 volatile u8 IPR31; /* SDMA + 0x5b */
631 volatile u32 res1; /* SDMA + 0x5c */
632 volatile u32 res2; /* SDMA + 0x60 */
633 volatile u32 res3; /* SDMA + 0x64 */
634 volatile u32 MDEDebug; /* SDMA + 0x68 */
635 volatile u32 ADSDebug; /* SDMA + 0x6c */
636 volatile u32 Value1; /* SDMA + 0x70 */
637 volatile u32 Value2; /* SDMA + 0x74 */
638 volatile u32 Control; /* SDMA + 0x78 */
639 volatile u32 Status; /* SDMA + 0x7c */
640 volatile u32 EU00; /* SDMA + 0x80 */
641 volatile u32 EU01; /* SDMA + 0x84 */
642 volatile u32 EU02; /* SDMA + 0x88 */
643 volatile u32 EU03; /* SDMA + 0x8c */
644 volatile u32 EU04; /* SDMA + 0x90 */
645 volatile u32 EU05; /* SDMA + 0x94 */
646 volatile u32 EU06; /* SDMA + 0x98 */
647 volatile u32 EU07; /* SDMA + 0x9c */
648 volatile u32 EU10; /* SDMA + 0xa0 */
649 volatile u32 EU11; /* SDMA + 0xa4 */
650 volatile u32 EU12; /* SDMA + 0xa8 */
651 volatile u32 EU13; /* SDMA + 0xac */
652 volatile u32 EU14; /* SDMA + 0xb0 */
653 volatile u32 EU15; /* SDMA + 0xb4 */
654 volatile u32 EU16; /* SDMA + 0xb8 */
655 volatile u32 EU17; /* SDMA + 0xbc */
656 volatile u32 EU20; /* SDMA + 0xc0 */
657 volatile u32 EU21; /* SDMA + 0xc4 */
658 volatile u32 EU22; /* SDMA + 0xc8 */
659 volatile u32 EU23; /* SDMA + 0xcc */
660 volatile u32 EU24; /* SDMA + 0xd0 */
661 volatile u32 EU25; /* SDMA + 0xd4 */
662 volatile u32 EU26; /* SDMA + 0xd8 */
663 volatile u32 EU27; /* SDMA + 0xdc */
664 volatile u32 EU30; /* SDMA + 0xe0 */
665 volatile u32 EU31; /* SDMA + 0xe4 */
666 volatile u32 EU32; /* SDMA + 0xe8 */
667 volatile u32 EU33; /* SDMA + 0xec */
668 volatile u32 EU34; /* SDMA + 0xf0 */
669 volatile u32 EU35; /* SDMA + 0xf4 */
670 volatile u32 EU36; /* SDMA + 0xf8 */
671 volatile u32 EU37; /* SDMA + 0xfc */
675 volatile u32 madr; /* I2Cn + 0x00 */
676 volatile u32 mfdr; /* I2Cn + 0x04 */
677 volatile u32 mcr; /* I2Cn + 0x08 */
678 volatile u32 msr; /* I2Cn + 0x0C */
679 volatile u32 mdr; /* I2Cn + 0x10 */
683 volatile u8 cr1; /* SPI + 0x0F00 */
684 volatile u8 cr2; /* SPI + 0x0F01 */
685 volatile u8 reserved1[2];
686 volatile u8 brr; /* SPI + 0x0F04 */
687 volatile u8 sr; /* SPI + 0x0F05 */
688 volatile u8 reserved2[3];
689 volatile u8 dr; /* SPI + 0x0F09 */
690 volatile u8 reserved3[3];
691 volatile u8 pdr; /* SPI + 0x0F0D */
692 volatile u8 reserved4[2];
693 volatile u8 ddr; /* SPI + 0x0F10 */
698 volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */
699 volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */
700 volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */
701 volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */
704 struct mpc5xxx_gpt_0_7 {
705 struct mpc5xxx_gpt gpt0;
706 struct mpc5xxx_gpt gpt1;
707 struct mpc5xxx_gpt gpt2;
708 struct mpc5xxx_gpt gpt3;
709 struct mpc5xxx_gpt gpt4;
710 struct mpc5xxx_gpt gpt5;
711 struct mpc5xxx_gpt gpt6;
712 struct mpc5xxx_gpt gpt7;
715 struct mscan_buffer {
716 volatile u8 idr[0x8]; /* 0x00 */
717 volatile u8 dsr[0x10]; /* 0x08 */
718 volatile u8 dlr; /* 0x18 */
719 volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
720 volatile u16 rsrv1; /* 0x1A */
721 volatile u8 tsrh; /* 0x1C */
722 volatile u8 tsrl; /* 0x1D */
723 volatile u16 rsrv2; /* 0x1E */
726 struct mpc5xxx_mscan {
727 volatile u8 canctl0; /* MSCAN + 0x00 */
728 volatile u8 canctl1; /* MSCAN + 0x01 */
729 volatile u16 rsrv1; /* MSCAN + 0x02 */
730 volatile u8 canbtr0; /* MSCAN + 0x04 */
731 volatile u8 canbtr1; /* MSCAN + 0x05 */
732 volatile u16 rsrv2; /* MSCAN + 0x06 */
733 volatile u8 canrflg; /* MSCAN + 0x08 */
734 volatile u8 canrier; /* MSCAN + 0x09 */
735 volatile u16 rsrv3; /* MSCAN + 0x0A */
736 volatile u8 cantflg; /* MSCAN + 0x0C */
737 volatile u8 cantier; /* MSCAN + 0x0D */
738 volatile u16 rsrv4; /* MSCAN + 0x0E */
739 volatile u8 cantarq; /* MSCAN + 0x10 */
740 volatile u8 cantaak; /* MSCAN + 0x11 */
741 volatile u16 rsrv5; /* MSCAN + 0x12 */
742 volatile u8 cantbsel; /* MSCAN + 0x14 */
743 volatile u8 canidac; /* MSCAN + 0x15 */
744 volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
745 volatile u8 canrxerr; /* MSCAN + 0x1C */
746 volatile u8 cantxerr; /* MSCAN + 0x1D */
747 volatile u16 rsrv7; /* MSCAN + 0x1E */
748 volatile u8 canidar0; /* MSCAN + 0x20 */
749 volatile u8 canidar1; /* MSCAN + 0x21 */
750 volatile u16 rsrv8; /* MSCAN + 0x22 */
751 volatile u8 canidar2; /* MSCAN + 0x24 */
752 volatile u8 canidar3; /* MSCAN + 0x25 */
753 volatile u16 rsrv9; /* MSCAN + 0x26 */
754 volatile u8 canidmr0; /* MSCAN + 0x28 */
755 volatile u8 canidmr1; /* MSCAN + 0x29 */
756 volatile u16 rsrv10; /* MSCAN + 0x2A */
757 volatile u8 canidmr2; /* MSCAN + 0x2C */
758 volatile u8 canidmr3; /* MSCAN + 0x2D */
759 volatile u16 rsrv11; /* MSCAN + 0x2E */
760 volatile u8 canidar4; /* MSCAN + 0x30 */
761 volatile u8 canidar5; /* MSCAN + 0x31 */
762 volatile u16 rsrv12; /* MSCAN + 0x32 */
763 volatile u8 canidar6; /* MSCAN + 0x34 */
764 volatile u8 canidar7; /* MSCAN + 0x35 */
765 volatile u16 rsrv13; /* MSCAN + 0x36 */
766 volatile u8 canidmr4; /* MSCAN + 0x38 */
767 volatile u8 canidmr5; /* MSCAN + 0x39 */
768 volatile u16 rsrv14; /* MSCAN + 0x3A */
769 volatile u8 canidmr6; /* MSCAN + 0x3C */
770 volatile u8 canidmr7; /* MSCAN + 0x3D */
771 volatile u16 rsrv15; /* MSCAN + 0x3E */
773 struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
774 struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
777 /* function prototypes */
778 void loadtask(int basetask, int tasks);
780 #endif /* __ASSEMBLY__ */
782 #endif /* __ASMPPC_MPC5XXX_H */