git.sur5r.net Git - u-boot/blob - include/mpc83xx.h

   1 /*
   2  * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __MPC83XX_H__
   8 #define __MPC83XX_H__
   9
  10 #include <config.h>
  11 #include <asm/fsl_lbc.h>
  12 #if defined(CONFIG_E300)
  13 #include <asm/e300.h>
  14 #endif
  15
  16 /*
  17  * MPC83xx cpu provide RCR register to do reset thing specially
  18  */
  19 #define MPC83xx_RESET
  20
  21 /*
  22  * System reset offset (PowerPC standard)
  23  */
  24 #define EXC_OFF_SYS_RESET               0x0100
  25 #define _START_OFFSET                   EXC_OFF_SYS_RESET
  26
  27 /*
  28  * IMMRBAR - Internal Memory Register Base Address
  29  */
  30 #ifndef CONFIG_DEFAULT_IMMR
  31 /* Default IMMR base address */
  32 #define CONFIG_DEFAULT_IMMR             0xFF400000
  33 #endif
  34 /* Register offset to immr */
  35 #define IMMRBAR                         0x0000
  36 #define IMMRBAR_BASE_ADDR               0xFFF00000      /* Base addr. mask */
  37 #define IMMRBAR_RES                     ~(IMMRBAR_BASE_ADDR)
  38
  39 /*
  40  * LAWBAR - Local Access Window Base Address Register
  41  */
  42 /* Register offset to immr */
  43 #define LBLAWBAR0                       0x0020
  44 #define LBLAWAR0                        0x0024
  45 #define LBLAWBAR1                       0x0028
  46 #define LBLAWAR1                        0x002C
  47 #define LBLAWBAR2                       0x0030
  48 #define LBLAWAR2                        0x0034
  49 #define LBLAWBAR3                       0x0038
  50 #define LBLAWAR3                        0x003C
  51 #define LAWBAR_BAR                      0xFFFFF000      /* Base addr. mask */
  52
  53 /*
  54  * SPRIDR - System Part and Revision ID Register
  55  */
  56 #define SPRIDR_PARTID                   0xFFFF0000      /* Part Id */
  57 #define SPRIDR_REVID                    0x0000FFFF      /* Revision Id */
  58
  59 #if defined(CONFIG_MPC834x)
  60 #define REVID_MAJOR(spridr)             ((spridr & 0x0000FF00) >> 8)
  61 #define REVID_MINOR(spridr)             (spridr & 0x000000FF)
  62 #else
  63 #define REVID_MAJOR(spridr)             ((spridr & 0x000000F0) >> 4)
  64 #define REVID_MINOR(spridr)             (spridr & 0x0000000F)
  65 #endif
  66
  67 #define PARTID_NO_E(spridr)             ((spridr & 0xFFFE0000) >> 16)
  68 #define SPR_FAMILY(spridr)              ((spridr & 0xFFF00000) >> 20)
  69
  70 #define SPR_8308                        0x8100
  71 #define SPR_8309                        0x8110
  72 #define SPR_831X_FAMILY                 0x80B
  73 #define SPR_8311                        0x80B2
  74 #define SPR_8313                        0x80B0
  75 #define SPR_8314                        0x80B6
  76 #define SPR_8315                        0x80B4
  77 #define SPR_832X_FAMILY                 0x806
  78 #define SPR_8321                        0x8066
  79 #define SPR_8323                        0x8062
  80 #define SPR_834X_FAMILY                 0x803
  81 #define SPR_8343                        0x8036
  82 #define SPR_8347_TBGA_                  0x8032
  83 #define SPR_8347_PBGA_                  0x8034
  84 #define SPR_8349                        0x8030
  85 #define SPR_836X_FAMILY                 0x804
  86 #define SPR_8358_TBGA_                  0x804A
  87 #define SPR_8358_PBGA_                  0x804E
  88 #define SPR_8360                        0x8048
  89 #define SPR_837X_FAMILY                 0x80C
  90 #define SPR_8377                        0x80C6
  91 #define SPR_8378                        0x80C4
  92 #define SPR_8379                        0x80C2
  93
  94 /*
  95  * SPCR - System Priority Configuration Register
  96  */
  97 /* PCI Highest Priority Enable */
  98 #define SPCR_PCIHPE                     0x10000000
  99 #define SPCR_PCIHPE_SHIFT               (31-3)
 100 /* PCI bridge system bus request priority */
 101 #define SPCR_PCIPR                      0x03000000
 102 #define SPCR_PCIPR_SHIFT                (31-7)
 103 #define SPCR_OPT                        0x00800000      /* Optimize */
 104 #define SPCR_OPT_SHIFT                  (31-8)
 105 /* E300 PowerPC core time base unit enable */
 106 #define SPCR_TBEN                       0x00400000
 107 #define SPCR_TBEN_SHIFT                 (31-9)
 108 /* E300 PowerPC Core system bus request priority */
 109 #define SPCR_COREPR                     0x00300000
 110 #define SPCR_COREPR_SHIFT               (31-11)
 111
 112 #if defined(CONFIG_MPC834x)
 113 /* SPCR bits - MPC8349 specific */
 114 /* TSEC1 data priority */
 115 #define SPCR_TSEC1DP                    0x00003000
 116 #define SPCR_TSEC1DP_SHIFT              (31-19)
 117 /* TSEC1 buffer descriptor priority */
 118 #define SPCR_TSEC1BDP                   0x00000C00
 119 #define SPCR_TSEC1BDP_SHIFT             (31-21)
 120 /* TSEC1 emergency priority */
 121 #define SPCR_TSEC1EP                    0x00000300
 122 #define SPCR_TSEC1EP_SHIFT              (31-23)
 123 /* TSEC2 data priority */
 124 #define SPCR_TSEC2DP                    0x00000030
 125 #define SPCR_TSEC2DP_SHIFT              (31-27)
 126 /* TSEC2 buffer descriptor priority */
 127 #define SPCR_TSEC2BDP                   0x0000000C
 128 #define SPCR_TSEC2BDP_SHIFT             (31-29)
 129 /* TSEC2 emergency priority */
 130 #define SPCR_TSEC2EP                    0x00000003
 131 #define SPCR_TSEC2EP_SHIFT              (31-31)
 132
 133 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 134         defined(CONFIG_MPC837x)
 135 /* SPCR bits - MPC8308, MPC831x and MPC837x specific */
 136 /* TSEC data priority */
 137 #define SPCR_TSECDP                     0x00003000
 138 #define SPCR_TSECDP_SHIFT               (31-19)
 139 /* TSEC buffer descriptor priority */
 140 #define SPCR_TSECBDP                    0x00000C00
 141 #define SPCR_TSECBDP_SHIFT              (31-21)
 142 /* TSEC emergency priority */
 143 #define SPCR_TSECEP                     0x00000300
 144 #define SPCR_TSECEP_SHIFT               (31-23)
 145 #endif
 146
 147 /* SICRL/H - System I/O Configuration Register Low/High
 148  */
 149 #if defined(CONFIG_MPC834x)
 150 /* SICRL bits - MPC8349 specific */
 151 #define SICRL_LDP_A                     0x80000000
 152 #define SICRL_USB1                      0x40000000
 153 #define SICRL_USB0                      0x20000000
 154 #define SICRL_UART                      0x0C000000
 155 #define SICRL_GPIO1_A                   0x02000000
 156 #define SICRL_GPIO1_B                   0x01000000
 157 #define SICRL_GPIO1_C                   0x00800000
 158 #define SICRL_GPIO1_D                   0x00400000
 159 #define SICRL_GPIO1_E                   0x00200000
 160 #define SICRL_GPIO1_F                   0x00180000
 161 #define SICRL_GPIO1_G                   0x00040000
 162 #define SICRL_GPIO1_H                   0x00020000
 163 #define SICRL_GPIO1_I                   0x00010000
 164 #define SICRL_GPIO1_J                   0x00008000
 165 #define SICRL_GPIO1_K                   0x00004000
 166 #define SICRL_GPIO1_L                   0x00003000
 167
 168 /* SICRH bits - MPC8349 specific */
 169 #define SICRH_DDR                       0x80000000
 170 #define SICRH_TSEC1_A                   0x10000000
 171 #define SICRH_TSEC1_B                   0x08000000
 172 #define SICRH_TSEC1_C                   0x04000000
 173 #define SICRH_TSEC1_D                   0x02000000
 174 #define SICRH_TSEC1_E                   0x01000000
 175 #define SICRH_TSEC1_F                   0x00800000
 176 #define SICRH_TSEC2_A                   0x00400000
 177 #define SICRH_TSEC2_B                   0x00200000
 178 #define SICRH_TSEC2_C                   0x00100000
 179 #define SICRH_TSEC2_D                   0x00080000
 180 #define SICRH_TSEC2_E                   0x00040000
 181 #define SICRH_TSEC2_F                   0x00020000
 182 #define SICRH_TSEC2_G                   0x00010000
 183 #define SICRH_TSEC2_H                   0x00008000
 184 #define SICRH_GPIO2_A                   0x00004000
 185 #define SICRH_GPIO2_B                   0x00002000
 186 #define SICRH_GPIO2_C                   0x00001000
 187 #define SICRH_GPIO2_D                   0x00000800
 188 #define SICRH_GPIO2_E                   0x00000400
 189 #define SICRH_GPIO2_F                   0x00000200
 190 #define SICRH_GPIO2_G                   0x00000180
 191 #define SICRH_GPIO2_H                   0x00000060
 192 #define SICRH_TSOBI1                    0x00000002
 193 #define SICRH_TSOBI2                    0x00000001
 194
 195 #elif defined(CONFIG_MPC8360)
 196 /* SICRL bits - MPC8360 specific */
 197 #define SICRL_LDP_A                     0xC0000000
 198 #define SICRL_LCLK_1                    0x10000000
 199 #define SICRL_LCLK_2                    0x08000000
 200 #define SICRL_SRCID_A                   0x03000000
 201 #define SICRL_IRQ_CKSTP_A               0x00C00000
 202
 203 /* SICRH bits - MPC8360 specific */
 204 #define SICRH_DDR                       0x80000000
 205 #define SICRH_SECONDARY_DDR             0x40000000
 206 #define SICRH_SDDROE                    0x20000000
 207 #define SICRH_IRQ3                      0x10000000
 208 #define SICRH_UC1EOBI                   0x00000004
 209 #define SICRH_UC2E1OBI                  0x00000002
 210 #define SICRH_UC2E2OBI                  0x00000001
 211
 212 #elif defined(CONFIG_MPC832x)
 213 /* SICRL bits - MPC832x specific */
 214 #define SICRL_LDP_LCS_A                 0x80000000
 215 #define SICRL_IRQ_CKS                   0x20000000
 216 #define SICRL_PCI_MSRC                  0x10000000
 217 #define SICRL_URT_CTPR                  0x06000000
 218 #define SICRL_IRQ_CTPR                  0x00C00000
 219
 220 #elif defined(CONFIG_MPC8313)
 221 /* SICRL bits - MPC8313 specific */
 222 #define SICRL_LBC                       0x30000000
 223 #define SICRL_UART                      0x0C000000
 224 #define SICRL_SPI_A                     0x03000000
 225 #define SICRL_SPI_B                     0x00C00000
 226 #define SICRL_SPI_C                     0x00300000
 227 #define SICRL_SPI_D                     0x000C0000
 228 #define SICRL_USBDR_11                  0x00000C00
 229 #define SICRL_USBDR_10                  0x00000800
 230 #define SICRL_USBDR_01                  0x00000400
 231 #define SICRL_USBDR_00                  0x00000000
 232 #define SICRL_ETSEC1_A                  0x0000000C
 233 #define SICRL_ETSEC2_A                  0x00000003
 234
 235 /* SICRH bits - MPC8313 specific */
 236 #define SICRH_INTR_A                    0x02000000
 237 #define SICRH_INTR_B                    0x00C00000
 238 #define SICRH_IIC                       0x00300000
 239 #define SICRH_ETSEC2_B                  0x000C0000
 240 #define SICRH_ETSEC2_C                  0x00030000
 241 #define SICRH_ETSEC2_D                  0x0000C000
 242 #define SICRH_ETSEC2_E                  0x00003000
 243 #define SICRH_ETSEC2_F                  0x00000C00
 244 #define SICRH_ETSEC2_G                  0x00000300
 245 #define SICRH_ETSEC1_B                  0x00000080
 246 #define SICRH_ETSEC1_C                  0x00000060
 247 #define SICRH_GTX1_DLY                  0x00000008
 248 #define SICRH_GTX2_DLY                  0x00000004
 249 #define SICRH_TSOBI1                    0x00000002
 250 #define SICRH_TSOBI2                    0x00000001
 251
 252 #elif defined(CONFIG_MPC8315)
 253 /* SICRL bits - MPC8315 specific */
 254 #define SICRL_DMA_CH0                   0xc0000000
 255 #define SICRL_DMA_SPI                   0x30000000
 256 #define SICRL_UART                      0x0c000000
 257 #define SICRL_IRQ4                      0x02000000
 258 #define SICRL_IRQ5                      0x01800000
 259 #define SICRL_IRQ6_7                    0x00400000
 260 #define SICRL_IIC1                      0x00300000
 261 #define SICRL_TDM                       0x000c0000
 262 #define SICRL_TDM_SHARED                0x00030000
 263 #define SICRL_PCI_A                     0x0000c000
 264 #define SICRL_ELBC_A                    0x00003000
 265 #define SICRL_ETSEC1_A                  0x000000c0
 266 #define SICRL_ETSEC1_B                  0x00000030
 267 #define SICRL_ETSEC1_C                  0x0000000c
 268 #define SICRL_TSEXPOBI                  0x00000001
 269
 270 /* SICRH bits - MPC8315 specific */
 271 #define SICRH_GPIO_0                    0xc0000000
 272 #define SICRH_GPIO_1                    0x30000000
 273 #define SICRH_GPIO_2                    0x0c000000
 274 #define SICRH_GPIO_3                    0x03000000
 275 #define SICRH_GPIO_4                    0x00c00000
 276 #define SICRH_GPIO_5                    0x00300000
 277 #define SICRH_GPIO_6                    0x000c0000
 278 #define SICRH_GPIO_7                    0x00030000
 279 #define SICRH_GPIO_8                    0x0000c000
 280 #define SICRH_GPIO_9                    0x00003000
 281 #define SICRH_GPIO_10                   0x00000c00
 282 #define SICRH_GPIO_11                   0x00000300
 283 #define SICRH_ETSEC2_A                  0x000000c0
 284 #define SICRH_TSOBI1                    0x00000002
 285 #define SICRH_TSOBI2                    0x00000001
 286
 287 #elif defined(CONFIG_MPC837x)
 288 /* SICRL bits - MPC837x specific */
 289 #define SICRL_USB_A                     0xC0000000
 290 #define SICRL_USB_B                     0x30000000
 291 #define SICRL_USB_B_SD                  0x20000000
 292 #define SICRL_UART                      0x0C000000
 293 #define SICRL_GPIO_A                    0x02000000
 294 #define SICRL_GPIO_B                    0x01000000
 295 #define SICRL_GPIO_C                    0x00800000
 296 #define SICRL_GPIO_D                    0x00400000
 297 #define SICRL_GPIO_E                    0x00200000
 298 #define SICRL_GPIO_F                    0x00180000
 299 #define SICRL_GPIO_G                    0x00040000
 300 #define SICRL_GPIO_H                    0x00020000
 301 #define SICRL_GPIO_I                    0x00010000
 302 #define SICRL_GPIO_J                    0x00008000
 303 #define SICRL_GPIO_K                    0x00004000
 304 #define SICRL_GPIO_L                    0x00003000
 305 #define SICRL_DMA_A                     0x00000800
 306 #define SICRL_DMA_B                     0x00000400
 307 #define SICRL_DMA_C                     0x00000200
 308 #define SICRL_DMA_D                     0x00000100
 309 #define SICRL_DMA_E                     0x00000080
 310 #define SICRL_DMA_F                     0x00000040
 311 #define SICRL_DMA_G                     0x00000020
 312 #define SICRL_DMA_H                     0x00000010
 313 #define SICRL_DMA_I                     0x00000008
 314 #define SICRL_DMA_J                     0x00000004
 315 #define SICRL_LDP_A                     0x00000002
 316 #define SICRL_LDP_B                     0x00000001
 317
 318 /* SICRH bits - MPC837x specific */
 319 #define SICRH_DDR                       0x80000000
 320 #define SICRH_TSEC1_A                   0x10000000
 321 #define SICRH_TSEC1_B                   0x08000000
 322 #define SICRH_TSEC2_A                   0x00400000
 323 #define SICRH_TSEC2_B                   0x00200000
 324 #define SICRH_TSEC2_C                   0x00100000
 325 #define SICRH_TSEC2_D                   0x00080000
 326 #define SICRH_TSEC2_E                   0x00040000
 327 #define SICRH_TMR                       0x00010000
 328 #define SICRH_GPIO2_A                   0x00008000
 329 #define SICRH_GPIO2_B                   0x00004000
 330 #define SICRH_GPIO2_C                   0x00002000
 331 #define SICRH_GPIO2_D                   0x00001000
 332 #define SICRH_GPIO2_E                   0x00000C00
 333 #define SICRH_GPIO2_E_SD                0x00000800
 334 #define SICRH_GPIO2_F                   0x00000300
 335 #define SICRH_GPIO2_G                   0x000000C0
 336 #define SICRH_GPIO2_H                   0x00000030
 337 #define SICRH_SPI                       0x00000003
 338 #define SICRH_SPI_SD                    0x00000001
 339
 340 #elif defined(CONFIG_MPC8308)
 341 /* SICRL bits - MPC8308 specific */
 342 #define SICRL_SPI_PF0                   (0 << 28)
 343 #define SICRL_SPI_PF1                   (1 << 28)
 344 #define SICRL_SPI_PF3                   (3 << 28)
 345 #define SICRL_UART_PF0                  (0 << 26)
 346 #define SICRL_UART_PF1                  (1 << 26)
 347 #define SICRL_UART_PF3                  (3 << 26)
 348 #define SICRL_IRQ_PF0                   (0 << 24)
 349 #define SICRL_IRQ_PF1                   (1 << 24)
 350 #define SICRL_I2C2_PF0                  (0 << 20)
 351 #define SICRL_I2C2_PF1                  (1 << 20)
 352 #define SICRL_ETSEC1_TX_CLK             (0 << 6)
 353 #define SICRL_ETSEC1_GTX_CLK125         (1 << 6)
 354
 355 /* SICRH bits - MPC8308 specific */
 356 #define SICRH_ESDHC_A_SD                (0 << 30)
 357 #define SICRH_ESDHC_A_GTM               (1 << 30)
 358 #define SICRH_ESDHC_A_GPIO              (3 << 30)
 359 #define SICRH_ESDHC_B_SD                (0 << 28)
 360 #define SICRH_ESDHC_B_GTM               (1 << 28)
 361 #define SICRH_ESDHC_B_GPIO              (3 << 28)
 362 #define SICRH_ESDHC_C_SD                (0 << 26)
 363 #define SICRH_ESDHC_C_GTM               (1 << 26)
 364 #define SICRH_ESDHC_C_GPIO              (3 << 26)
 365 #define SICRH_GPIO_A_GPIO               (0 << 24)
 366 #define SICRH_GPIO_A_TSEC2              (1 << 24)
 367 #define SICRH_GPIO_B_GPIO               (0 << 22)
 368 #define SICRH_GPIO_B_TSEC2_TX_CLK       (1 << 22)
 369 #define SICRH_GPIO_B_TSEC2_GTX_CLK125   (2 << 22)
 370 #define SICRH_IEEE1588_A_TMR            (1 << 20)
 371 #define SICRH_IEEE1588_A_GPIO           (3 << 20)
 372 #define SICRH_USB                       (1 << 18)
 373 #define SICRH_GTM_GTM                   (1 << 16)
 374 #define SICRH_GTM_GPIO                  (3 << 16)
 375 #define SICRH_IEEE1588_B_TMR            (1 << 14)
 376 #define SICRH_IEEE1588_B_GPIO           (3 << 14)
 377 #define SICRH_ETSEC2_CRS                (1 << 12)
 378 #define SICRH_ETSEC2_GPIO               (3 << 12)
 379 #define SICRH_GPIOSEL_0                 (0 << 8)
 380 #define SICRH_GPIOSEL_1                 (1 << 8)
 381 #define SICRH_TMROBI_V3P3               (0 << 4)
 382 #define SICRH_TMROBI_V2P5               (1 << 4)
 383 #define SICRH_TSOBI1_V3P3               (0 << 1)
 384 #define SICRH_TSOBI1_V2P5               (1 << 1)
 385 #define SICRH_TSOBI2_V3P3               (0 << 0)
 386 #define SICRH_TSOBI2_V2P5               (1 << 0)
 387
 388 #elif defined(CONFIG_MPC8309)
 389 /* SICR_1 */
 390 #define SICR_1_UART1_UART1S             (0 << (30-2))
 391 #define SICR_1_UART1_UART1RTS           (1 << (30-2))
 392 #define SICR_1_I2C_I2C                  (0 << (30-4))
 393 #define SICR_1_I2C_CKSTOP               (1 << (30-4))
 394 #define SICR_1_IRQ_A_IRQ                (0 << (30-6))
 395 #define SICR_1_IRQ_A_MCP                (1 << (30-6))
 396 #define SICR_1_IRQ_B_IRQ                (0 << (30-8))
 397 #define SICR_1_IRQ_B_CKSTOP             (1 << (30-8))
 398 #define SICR_1_GPIO_A_GPIO              (0 << (30-10))
 399 #define SICR_1_GPIO_A_SD                (2 << (30-10))
 400 #define SICR_1_GPIO_A_DDR               (3 << (30-10))
 401 #define SICR_1_GPIO_B_GPIO              (0 << (30-12))
 402 #define SICR_1_GPIO_B_SD                (2 << (30-12))
 403 #define SICR_1_GPIO_B_QE                (3 << (30-12))
 404 #define SICR_1_GPIO_C_GPIO              (0 << (30-14))
 405 #define SICR_1_GPIO_C_CAN               (1 << (30-14))
 406 #define SICR_1_GPIO_C_DDR               (2 << (30-14))
 407 #define SICR_1_GPIO_C_LCS               (3 << (30-14))
 408 #define SICR_1_GPIO_D_GPIO              (0 << (30-16))
 409 #define SICR_1_GPIO_D_CAN               (1 << (30-16))
 410 #define SICR_1_GPIO_D_DDR               (2 << (30-16))
 411 #define SICR_1_GPIO_D_LCS               (3 << (30-16))
 412 #define SICR_1_GPIO_E_GPIO              (0 << (30-18))
 413 #define SICR_1_GPIO_E_CAN               (1 << (30-18))
 414 #define SICR_1_GPIO_E_DDR               (2 << (30-18))
 415 #define SICR_1_GPIO_E_LCS               (3 << (30-18))
 416 #define SICR_1_GPIO_F_GPIO              (0 << (30-20))
 417 #define SICR_1_GPIO_F_CAN               (1 << (30-20))
 418 #define SICR_1_GPIO_F_CK                (2 << (30-20))
 419 #define SICR_1_USB_A_USBDR              (0 << (30-22))
 420 #define SICR_1_USB_A_UART2S             (1 << (30-22))
 421 #define SICR_1_USB_B_USBDR              (0 << (30-24))
 422 #define SICR_1_USB_B_UART2S             (1 << (30-24))
 423 #define SICR_1_USB_B_UART2RTS           (2 << (30-24))
 424 #define SICR_1_USB_C_USBDR              (0 << (30-26))
 425 #define SICR_1_USB_C_QE_EXT             (3 << (30-26))
 426 #define SICR_1_FEC1_FEC1                (0 << (30-28))
 427 #define SICR_1_FEC1_GTM                 (1 << (30-28))
 428 #define SICR_1_FEC1_GPIO                (2 << (30-28))
 429 #define SICR_1_FEC2_FEC2                (0 << (30-30))
 430 #define SICR_1_FEC2_GTM                 (1 << (30-30))
 431 #define SICR_1_FEC2_GPIO                (2 << (30-30))
 432 /* SICR_2 */
 433 #define SICR_2_FEC3_FEC3                (0 << (30-0))
 434 #define SICR_2_FEC3_TMR                 (1 << (30-0))
 435 #define SICR_2_FEC3_GPIO                (2 << (30-0))
 436 #define SICR_2_HDLC1_A_HDLC1            (0 << (30-2))
 437 #define SICR_2_HDLC1_A_GPIO             (1 << (30-2))
 438 #define SICR_2_HDLC1_A_TDM1             (2 << (30-2))
 439 #define SICR_2_ELBC_A_LA                (0 << (30-4))
 440 #define SICR_2_ELBC_B_LCLK              (0 << (30-6))
 441 #define SICR_2_HDLC2_A_HDLC2            (0 << (30-8))
 442 #define SICR_2_HDLC2_A_GPIO             (0 << (30-8))
 443 #define SICR_2_HDLC2_A_TDM2             (0 << (30-8))
 444 /* bits 10-11 unused */
 445 #define SICR_2_USB_D_USBDR              (0 << (30-12))
 446 #define SICR_2_USB_D_GPIO               (2 << (30-12))
 447 #define SICR_2_USB_D_QE_BRG             (3 << (30-12))
 448 #define SICR_2_PCI_PCI                  (0 << (30-14))
 449 #define SICR_2_PCI_CPCI_HS              (2 << (30-14))
 450 #define SICR_2_HDLC1_B_HDLC1            (0 << (30-16))
 451 #define SICR_2_HDLC1_B_GPIO             (1 << (30-16))
 452 #define SICR_2_HDLC1_B_QE_BRG           (2 << (30-16))
 453 #define SICR_2_HDLC1_B_TDM1             (3 << (30-16))
 454 #define SICR_2_HDLC1_C_HDLC1            (0 << (30-18))
 455 #define SICR_2_HDLC1_C_GPIO             (1 << (30-18))
 456 #define SICR_2_HDLC1_C_TDM1             (2 << (30-18))
 457 #define SICR_2_HDLC2_B_HDLC2            (0 << (30-20))
 458 #define SICR_2_HDLC2_B_GPIO             (1 << (30-20))
 459 #define SICR_2_HDLC2_B_QE_BRG           (2 << (30-20))
 460 #define SICR_2_HDLC2_B_TDM2             (3 << (30-20))
 461 #define SICR_2_HDLC2_C_HDLC2            (0 << (30-22))
 462 #define SICR_2_HDLC2_C_GPIO             (1 << (30-22))
 463 #define SICR_2_HDLC2_C_TDM2             (2 << (30-22))
 464 #define SICR_2_HDLC2_C_QE_BRG           (3 << (30-22))
 465 #define SICR_2_QUIESCE_B                (0 << (30-24))
 466
 467 #endif
 468
 469 /*
 470  * SWCRR - System Watchdog Control Register
 471  */
 472 /* Register offset to immr */
 473 #define SWCRR                           0x0204
 474 /* Software Watchdog Time Count */
 475 #define SWCRR_SWTC                      0xFFFF0000
 476 /* Watchdog Enable bit */
 477 #define SWCRR_SWEN                      0x00000004
 478 /* Software Watchdog Reset/Interrupt Select bit */
 479 #define SWCRR_SWRI                      0x00000002
 480 /* Software Watchdog Counter Prescale bit */
 481 #define SWCRR_SWPR                      0x00000001
 482 #define SWCRR_RES                       (~(SWCRR_SWTC | SWCRR_SWEN | \
 483                                                 SWCRR_SWRI | SWCRR_SWPR))
 484
 485 /*
 486  * SWCNR - System Watchdog Counter Register
 487  */
 488 /* Register offset to immr */
 489 #define SWCNR                           0x0208
 490 /* Software Watchdog Count mask */
 491 #define SWCNR_SWCN                      0x0000FFFF
 492 #define SWCNR_RES                       ~(SWCNR_SWCN)
 493
 494 /*
 495  * SWSRR - System Watchdog Service Register
 496  */
 497 /* Register offset to immr */
 498 #define SWSRR                           0x020E
 499
 500 /*
 501  * ACR - Arbiter Configuration Register
 502  */
 503 #define ACR_COREDIS                     0x10000000      /* Core disable */
 504 #define ACR_COREDIS_SHIFT               (31-7)
 505 #define ACR_PIPE_DEP                    0x00070000      /* Pipeline depth */
 506 #define ACR_PIPE_DEP_SHIFT              (31-15)
 507 #define ACR_PCI_RPTCNT                  0x00007000      /* PCI repeat count */
 508 #define ACR_PCI_RPTCNT_SHIFT            (31-19)
 509 #define ACR_RPTCNT                      0x00000700      /* Repeat count */
 510 #define ACR_RPTCNT_SHIFT                (31-23)
 511 #define ACR_APARK                       0x00000030      /* Address parking */
 512 #define ACR_APARK_SHIFT                 (31-27)
 513 #define ACR_PARKM                       0x0000000F      /* Parking master */
 514 #define ACR_PARKM_SHIFT                 (31-31)
 515
 516 /*
 517  * ATR - Arbiter Timers Register
 518  */
 519 #define ATR_DTO                         0x00FF0000      /* Data time out */
 520 #define ATR_DTO_SHIFT                   16
 521 #define ATR_ATO                         0x000000FF      /* Address time out */
 522 #define ATR_ATO_SHIFT                   0
 523
 524 /*
 525  * AER - Arbiter Event Register
 526  */
 527 #define AER_ETEA                        0x00000020      /* Transfer error */
 528 /* Reserved transfer type */
 529 #define AER_RES                         0x00000010
 530 /* External control word transfer type */
 531 #define AER_ECW                         0x00000008
 532 /* Address Only transfer type */
 533 #define AER_AO                          0x00000004
 534 #define AER_DTO                         0x00000002      /* Data time out */
 535 #define AER_ATO                         0x00000001      /* Address time out */
 536
 537 /*
 538  * AEATR - Arbiter Event Address Register
 539  */
 540 #define AEATR_EVENT                     0x07000000      /* Event type */
 541 #define AEATR_EVENT_SHIFT               24
 542 #define AEATR_MSTR_ID                   0x001F0000      /* Master Id */
 543 #define AEATR_MSTR_ID_SHIFT             16
 544 #define AEATR_TBST                      0x00000800      /* Transfer burst */
 545 #define AEATR_TBST_SHIFT                11
 546 #define AEATR_TSIZE                     0x00000700      /* Transfer Size */
 547 #define AEATR_TSIZE_SHIFT               8
 548 #define AEATR_TTYPE                     0x0000001F      /* Transfer Type */
 549 #define AEATR_TTYPE_SHIFT               0
 550
 551 /*
 552  * HRCWL - Hard Reset Configuration Word Low
 553  */
 554 #define HRCWL_LBIUCM                    0x80000000
 555 #define HRCWL_LBIUCM_SHIFT              31
 556 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1    0x00000000
 557 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1    0x80000000
 558
 559 #define HRCWL_DDRCM                     0x40000000
 560 #define HRCWL_DDRCM_SHIFT               30
 561 #define HRCWL_DDR_TO_SCB_CLK_1X1        0x00000000
 562 #define HRCWL_DDR_TO_SCB_CLK_2X1        0x40000000
 563
 564 #define HRCWL_SPMF                      0x0f000000
 565 #define HRCWL_SPMF_SHIFT                24
 566 #define HRCWL_CSB_TO_CLKIN_16X1         0x00000000
 567 #define HRCWL_CSB_TO_CLKIN_1X1          0x01000000
 568 #define HRCWL_CSB_TO_CLKIN_2X1          0x02000000
 569 #define HRCWL_CSB_TO_CLKIN_3X1          0x03000000
 570 #define HRCWL_CSB_TO_CLKIN_4X1          0x04000000
 571 #define HRCWL_CSB_TO_CLKIN_5X1          0x05000000
 572 #define HRCWL_CSB_TO_CLKIN_6X1          0x06000000
 573 #define HRCWL_CSB_TO_CLKIN_7X1          0x07000000
 574 #define HRCWL_CSB_TO_CLKIN_8X1          0x08000000
 575 #define HRCWL_CSB_TO_CLKIN_9X1          0x09000000
 576 #define HRCWL_CSB_TO_CLKIN_10X1         0x0A000000
 577 #define HRCWL_CSB_TO_CLKIN_11X1         0x0B000000
 578 #define HRCWL_CSB_TO_CLKIN_12X1         0x0C000000
 579 #define HRCWL_CSB_TO_CLKIN_13X1         0x0D000000
 580 #define HRCWL_CSB_TO_CLKIN_14X1         0x0E000000
 581 #define HRCWL_CSB_TO_CLKIN_15X1         0x0F000000
 582
 583 #define HRCWL_VCO_BYPASS                0x00000000
 584 #define HRCWL_VCO_1X2                   0x00000000
 585 #define HRCWL_VCO_1X4                   0x00200000
 586 #define HRCWL_VCO_1X8                   0x00400000
 587
 588 #define HRCWL_COREPLL                   0x007F0000
 589 #define HRCWL_COREPLL_SHIFT             16
 590 #define HRCWL_CORE_TO_CSB_BYPASS        0x00000000
 591 #define HRCWL_CORE_TO_CSB_1X1           0x00020000
 592 #define HRCWL_CORE_TO_CSB_1_5X1         0x00030000
 593 #define HRCWL_CORE_TO_CSB_2X1           0x00040000
 594 #define HRCWL_CORE_TO_CSB_2_5X1         0x00050000
 595 #define HRCWL_CORE_TO_CSB_3X1           0x00060000
 596
 597 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 598 #define HRCWL_CEVCOD                    0x000000C0
 599 #define HRCWL_CEVCOD_SHIFT              6
 600 #define HRCWL_CE_PLL_VCO_DIV_4          0x00000000
 601 #define HRCWL_CE_PLL_VCO_DIV_8          0x00000040
 602 #define HRCWL_CE_PLL_VCO_DIV_2          0x00000080
 603
 604 #define HRCWL_CEPDF                     0x00000020
 605 #define HRCWL_CEPDF_SHIFT               5
 606 #define HRCWL_CE_PLL_DIV_1X1            0x00000000
 607 #define HRCWL_CE_PLL_DIV_2X1            0x00000020
 608
 609 #define HRCWL_CEPMF                     0x0000001F
 610 #define HRCWL_CEPMF_SHIFT               0
 611 #define HRCWL_CE_TO_PLL_1X16_           0x00000000
 612 #define HRCWL_CE_TO_PLL_1X2             0x00000002
 613 #define HRCWL_CE_TO_PLL_1X3             0x00000003
 614 #define HRCWL_CE_TO_PLL_1X4             0x00000004
 615 #define HRCWL_CE_TO_PLL_1X5             0x00000005
 616 #define HRCWL_CE_TO_PLL_1X6             0x00000006
 617 #define HRCWL_CE_TO_PLL_1X7             0x00000007
 618 #define HRCWL_CE_TO_PLL_1X8             0x00000008
 619 #define HRCWL_CE_TO_PLL_1X9             0x00000009
 620 #define HRCWL_CE_TO_PLL_1X10            0x0000000A
 621 #define HRCWL_CE_TO_PLL_1X11            0x0000000B
 622 #define HRCWL_CE_TO_PLL_1X12            0x0000000C
 623 #define HRCWL_CE_TO_PLL_1X13            0x0000000D
 624 #define HRCWL_CE_TO_PLL_1X14            0x0000000E
 625 #define HRCWL_CE_TO_PLL_1X15            0x0000000F
 626 #define HRCWL_CE_TO_PLL_1X16            0x00000010
 627 #define HRCWL_CE_TO_PLL_1X17            0x00000011
 628 #define HRCWL_CE_TO_PLL_1X18            0x00000012
 629 #define HRCWL_CE_TO_PLL_1X19            0x00000013
 630 #define HRCWL_CE_TO_PLL_1X20            0x00000014
 631 #define HRCWL_CE_TO_PLL_1X21            0x00000015
 632 #define HRCWL_CE_TO_PLL_1X22            0x00000016
 633 #define HRCWL_CE_TO_PLL_1X23            0x00000017
 634 #define HRCWL_CE_TO_PLL_1X24            0x00000018
 635 #define HRCWL_CE_TO_PLL_1X25            0x00000019
 636 #define HRCWL_CE_TO_PLL_1X26            0x0000001A
 637 #define HRCWL_CE_TO_PLL_1X27            0x0000001B
 638 #define HRCWL_CE_TO_PLL_1X28            0x0000001C
 639 #define HRCWL_CE_TO_PLL_1X29            0x0000001D
 640 #define HRCWL_CE_TO_PLL_1X30            0x0000001E
 641 #define HRCWL_CE_TO_PLL_1X31            0x0000001F
 642
 643 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 644 #define HRCWL_SVCOD                     0x30000000
 645 #define HRCWL_SVCOD_SHIFT               28
 646 #define HRCWL_SVCOD_DIV_2               0x00000000
 647 #define HRCWL_SVCOD_DIV_4               0x10000000
 648 #define HRCWL_SVCOD_DIV_8               0x20000000
 649 #define HRCWL_SVCOD_DIV_1               0x30000000
 650
 651 #elif defined(CONFIG_MPC837x)
 652 #define HRCWL_SVCOD                     0x30000000
 653 #define HRCWL_SVCOD_SHIFT               28
 654 #define HRCWL_SVCOD_DIV_4               0x00000000
 655 #define HRCWL_SVCOD_DIV_8               0x10000000
 656 #define HRCWL_SVCOD_DIV_2               0x20000000
 657 #define HRCWL_SVCOD_DIV_1               0x30000000
 658 #elif defined(CONFIG_MPC8309)
 659
 660 #define HRCWL_CEVCOD                    0x000000C0
 661 #define HRCWL_CEVCOD_SHIFT              6
 662 /*
 663  * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
 664  * these are different than with 8360, 832x
 665  */
 666 #define HRCWL_CE_PLL_VCO_DIV_2          0x00000000
 667 #define HRCWL_CE_PLL_VCO_DIV_4          0x00000040
 668 #define HRCWL_CE_PLL_VCO_DIV_8          0x00000080
 669
 670 #define HRCWL_CEPDF                     0x00000020
 671 #define HRCWL_CEPDF_SHIFT               5
 672 #define HRCWL_CE_PLL_DIV_1X1            0x00000000
 673 #define HRCWL_CE_PLL_DIV_2X1            0x00000020
 674
 675 #define HRCWL_CEPMF                     0x0000001F
 676 #define HRCWL_CEPMF_SHIFT               0
 677 #define HRCWL_CE_TO_PLL_1X16_           0x00000000
 678 #define HRCWL_CE_TO_PLL_1X2             0x00000002
 679 #define HRCWL_CE_TO_PLL_1X3             0x00000003
 680 #define HRCWL_CE_TO_PLL_1X4             0x00000004
 681 #define HRCWL_CE_TO_PLL_1X5             0x00000005
 682 #define HRCWL_CE_TO_PLL_1X6             0x00000006
 683 #define HRCWL_CE_TO_PLL_1X7             0x00000007
 684 #define HRCWL_CE_TO_PLL_1X8             0x00000008
 685 #define HRCWL_CE_TO_PLL_1X9             0x00000009
 686 #define HRCWL_CE_TO_PLL_1X10            0x0000000A
 687 #define HRCWL_CE_TO_PLL_1X11            0x0000000B
 688 #define HRCWL_CE_TO_PLL_1X12            0x0000000C
 689 #define HRCWL_CE_TO_PLL_1X13            0x0000000D
 690 #define HRCWL_CE_TO_PLL_1X14            0x0000000E
 691 #define HRCWL_CE_TO_PLL_1X15            0x0000000F
 692 #define HRCWL_CE_TO_PLL_1X16            0x00000010
 693 #define HRCWL_CE_TO_PLL_1X17            0x00000011
 694 #define HRCWL_CE_TO_PLL_1X18            0x00000012
 695 #define HRCWL_CE_TO_PLL_1X19            0x00000013
 696 #define HRCWL_CE_TO_PLL_1X20            0x00000014
 697 #define HRCWL_CE_TO_PLL_1X21            0x00000015
 698 #define HRCWL_CE_TO_PLL_1X22            0x00000016
 699 #define HRCWL_CE_TO_PLL_1X23            0x00000017
 700 #define HRCWL_CE_TO_PLL_1X24            0x00000018
 701 #define HRCWL_CE_TO_PLL_1X25            0x00000019
 702 #define HRCWL_CE_TO_PLL_1X26            0x0000001A
 703 #define HRCWL_CE_TO_PLL_1X27            0x0000001B
 704 #define HRCWL_CE_TO_PLL_1X28            0x0000001C
 705 #define HRCWL_CE_TO_PLL_1X29            0x0000001D
 706 #define HRCWL_CE_TO_PLL_1X30            0x0000001E
 707 #define HRCWL_CE_TO_PLL_1X31            0x0000001F
 708
 709 #define HRCWL_SVCOD                     0x30000000
 710 #define HRCWL_SVCOD_SHIFT               28
 711 #define HRCWL_SVCOD_DIV_2               0x00000000
 712 #define HRCWL_SVCOD_DIV_4               0x10000000
 713 #define HRCWL_SVCOD_DIV_8               0x20000000
 714 #define HRCWL_SVCOD_DIV_1               0x30000000
 715 #endif
 716
 717 /*
 718  * HRCWH - Hardware Reset Configuration Word High
 719  */
 720 #define HRCWH_PCI_HOST                  0x80000000
 721 #define HRCWH_PCI_HOST_SHIFT            31
 722 #define HRCWH_PCI_AGENT                 0x00000000
 723
 724 #if defined(CONFIG_MPC834x)
 725 #define HRCWH_32_BIT_PCI                0x00000000
 726 #define HRCWH_64_BIT_PCI                0x40000000
 727 #endif
 728
 729 #define HRCWH_PCI1_ARBITER_DISABLE      0x00000000
 730 #define HRCWH_PCI1_ARBITER_ENABLE       0x20000000
 731
 732 #define HRCWH_PCI_ARBITER_DISABLE       0x00000000
 733 #define HRCWH_PCI_ARBITER_ENABLE        0x20000000
 734
 735 #if defined(CONFIG_MPC834x)
 736 #define HRCWH_PCI2_ARBITER_DISABLE      0x00000000
 737 #define HRCWH_PCI2_ARBITER_ENABLE       0x10000000
 738
 739 #elif defined(CONFIG_MPC8360)
 740 #define HRCWH_PCICKDRV_DISABLE          0x00000000
 741 #define HRCWH_PCICKDRV_ENABLE           0x10000000
 742 #endif
 743
 744 #define HRCWH_CORE_DISABLE              0x08000000
 745 #define HRCWH_CORE_ENABLE               0x00000000
 746
 747 #define HRCWH_FROM_0X00000100           0x00000000
 748 #define HRCWH_FROM_0XFFF00100           0x04000000
 749
 750 #define HRCWH_BOOTSEQ_DISABLE           0x00000000
 751 #define HRCWH_BOOTSEQ_NORMAL            0x01000000
 752 #define HRCWH_BOOTSEQ_EXTENDED          0x02000000
 753
 754 #define HRCWH_SW_WATCHDOG_DISABLE       0x00000000
 755 #define HRCWH_SW_WATCHDOG_ENABLE        0x00800000
 756
 757 #define HRCWH_ROM_LOC_DDR_SDRAM         0x00000000
 758 #define HRCWH_ROM_LOC_PCI1              0x00100000
 759 #if defined(CONFIG_MPC834x)
 760 #define HRCWH_ROM_LOC_PCI2              0x00200000
 761 #endif
 762 #if defined(CONFIG_MPC837x)
 763 #define HRCWH_ROM_LOC_ON_CHIP_ROM       0x00300000
 764 #endif
 765 #define HRCWH_ROM_LOC_LOCAL_8BIT        0x00500000
 766 #define HRCWH_ROM_LOC_LOCAL_16BIT       0x00600000
 767 #define HRCWH_ROM_LOC_LOCAL_32BIT       0x00700000
 768
 769 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 770         defined(CONFIG_MPC837x)
 771 #define HRCWH_ROM_LOC_NAND_SP_8BIT      0x00100000
 772 #define HRCWH_ROM_LOC_NAND_SP_16BIT     0x00200000
 773 #define HRCWH_ROM_LOC_NAND_LP_8BIT      0x00500000
 774 #define HRCWH_ROM_LOC_NAND_LP_16BIT     0x00600000
 775
 776 #define HRCWH_RL_EXT_LEGACY             0x00000000
 777 #define HRCWH_RL_EXT_NAND               0x00040000
 778
 779 #define HRCWH_TSEC1M_MASK               0x0000E000
 780 #define HRCWH_TSEC1M_IN_MII             0x00000000
 781 #define HRCWH_TSEC1M_IN_RMII            0x00002000
 782 #define HRCWH_TSEC1M_IN_RGMII           0x00006000
 783 #define HRCWH_TSEC1M_IN_RTBI            0x0000A000
 784 #define HRCWH_TSEC1M_IN_SGMII           0x0000C000
 785
 786 #define HRCWH_TSEC2M_MASK               0x00001C00
 787 #define HRCWH_TSEC2M_IN_MII             0x00000000
 788 #define HRCWH_TSEC2M_IN_RMII            0x00000400
 789 #define HRCWH_TSEC2M_IN_RGMII           0x00000C00
 790 #define HRCWH_TSEC2M_IN_RTBI            0x00001400
 791 #define HRCWH_TSEC2M_IN_SGMII           0x00001800
 792 #endif
 793
 794 #if defined(CONFIG_MPC834x)
 795 #define HRCWH_TSEC1M_IN_RGMII           0x00000000
 796 #define HRCWH_TSEC1M_IN_RTBI            0x00004000
 797 #define HRCWH_TSEC1M_IN_GMII            0x00008000
 798 #define HRCWH_TSEC1M_IN_TBI             0x0000C000
 799 #define HRCWH_TSEC2M_IN_RGMII           0x00000000
 800 #define HRCWH_TSEC2M_IN_RTBI            0x00001000
 801 #define HRCWH_TSEC2M_IN_GMII            0x00002000
 802 #define HRCWH_TSEC2M_IN_TBI             0x00003000
 803 #endif
 804
 805 #if defined(CONFIG_MPC8360)
 806 #define HRCWH_SECONDARY_DDR_DISABLE     0x00000000
 807 #define HRCWH_SECONDARY_DDR_ENABLE      0x00000010
 808 #endif
 809
 810 #define HRCWH_BIG_ENDIAN                0x00000000
 811 #define HRCWH_LITTLE_ENDIAN             0x00000008
 812
 813 #define HRCWH_LALE_NORMAL               0x00000000
 814 #define HRCWH_LALE_EARLY                0x00000004
 815
 816 #define HRCWH_LDP_SET                   0x00000000
 817 #define HRCWH_LDP_CLEAR                 0x00000002
 818
 819 /*
 820  * RSR - Reset Status Register
 821  */
 822 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 823         defined(CONFIG_MPC837x)
 824 #define RSR_RSTSRC                      0xF0000000      /* Reset source */
 825 #define RSR_RSTSRC_SHIFT                28
 826 #else
 827 #define RSR_RSTSRC                      0xE0000000      /* Reset source */
 828 #define RSR_RSTSRC_SHIFT                29
 829 #endif
 830 #define RSR_BSF                         0x00010000      /* Boot seq. fail */
 831 #define RSR_BSF_SHIFT                   16
 832 /* software soft reset */
 833 #define RSR_SWSR                        0x00002000
 834 #define RSR_SWSR_SHIFT                  13
 835 /* software hard reset */
 836 #define RSR_SWHR                        0x00001000
 837 #define RSR_SWHR_SHIFT                  12
 838 #define RSR_JHRS                        0x00000200      /* jtag hreset */
 839 #define RSR_JHRS_SHIFT                  9
 840 /* jtag sreset status */
 841 #define RSR_JSRS                        0x00000100
 842 #define RSR_JSRS_SHIFT                  8
 843 /* checkstop reset status */
 844 #define RSR_CSHR                        0x00000010
 845 #define RSR_CSHR_SHIFT                  4
 846 /* software watchdog reset status */
 847 #define RSR_SWRS                        0x00000008
 848 #define RSR_SWRS_SHIFT                  3
 849 /* bus monitop reset status */
 850 #define RSR_BMRS                        0x00000004
 851 #define RSR_BMRS_SHIFT                  2
 852 #define RSR_SRS                         0x00000002      /* soft reset status */
 853 #define RSR_SRS_SHIFT                   1
 854 #define RSR_HRS                         0x00000001      /* hard reset status */
 855 #define RSR_HRS_SHIFT                   0
 856 #define RSR_RES                         (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
 857                                                 RSR_SWHR | RSR_JHRS | \
 858                                                 RSR_JSRS | RSR_CSHR | \
 859                                                 RSR_SWRS | RSR_BMRS | \
 860                                                 RSR_SRS | RSR_HRS))
 861 /*
 862  * RMR - Reset Mode Register
 863  */
 864 /* checkstop reset enable */
 865 #define RMR_CSRE                        0x00000001
 866 #define RMR_CSRE_SHIFT                  0
 867 #define RMR_RES                         ~(RMR_CSRE)
 868
 869 /*
 870  * RCR - Reset Control Register
 871  */
 872 /* software hard reset */
 873 #define RCR_SWHR                        0x00000002
 874 /* software soft reset */
 875 #define RCR_SWSR                        0x00000001
 876 #define RCR_RES                         ~(RCR_SWHR | RCR_SWSR)
 877
 878 /*
 879  * RCER - Reset Control Enable Register
 880  */
 881 /* software hard reset */
 882 #define RCER_CRE                        0x00000001
 883 #define RCER_RES                        ~(RCER_CRE)
 884
 885 /*
 886  * SPMR - System PLL Mode Register
 887  */
 888 #define SPMR_LBIUCM                     0x80000000
 889 #define SPMR_LBIUCM_SHIFT               31
 890 #define SPMR_DDRCM                      0x40000000
 891 #define SPMR_DDRCM_SHIFT                30
 892 #define SPMR_SPMF                       0x0F000000
 893 #define SPMR_SPMF_SHIFT         24
 894 #define SPMR_CKID                       0x00800000
 895 #define SPMR_CKID_SHIFT                 23
 896 #define SPMR_COREPLL                    0x007F0000
 897 #define SPMR_COREPLL_SHIFT              16
 898 #define SPMR_CEVCOD                     0x000000C0
 899 #define SPMR_CEVCOD_SHIFT               6
 900 #define SPMR_CEPDF                      0x00000020
 901 #define SPMR_CEPDF_SHIFT                5
 902 #define SPMR_CEPMF                      0x0000001F
 903 #define SPMR_CEPMF_SHIFT                0
 904
 905 /*
 906  * OCCR - Output Clock Control Register
 907  */
 908 #define OCCR_PCICOE0                    0x80000000
 909 #define OCCR_PCICOE1                    0x40000000
 910 #define OCCR_PCICOE2                    0x20000000
 911 #define OCCR_PCICOE3                    0x10000000
 912 #define OCCR_PCICOE4                    0x08000000
 913 #define OCCR_PCICOE5                    0x04000000
 914 #define OCCR_PCICOE6                    0x02000000
 915 #define OCCR_PCICOE7                    0x01000000
 916 #define OCCR_PCICD0                     0x00800000
 917 #define OCCR_PCICD1                     0x00400000
 918 #define OCCR_PCICD2                     0x00200000
 919 #define OCCR_PCICD3                     0x00100000
 920 #define OCCR_PCICD4                     0x00080000
 921 #define OCCR_PCICD5                     0x00040000
 922 #define OCCR_PCICD6                     0x00020000
 923 #define OCCR_PCICD7                     0x00010000
 924 #define OCCR_PCI1CR                     0x00000002
 925 #define OCCR_PCI2CR                     0x00000001
 926 #define OCCR_PCICR                      OCCR_PCI1CR
 927
 928 /*
 929  * SCCR - System Clock Control Register
 930  */
 931 #define SCCR_ENCCM                      0x03000000
 932 #define SCCR_ENCCM_SHIFT                24
 933 #define SCCR_ENCCM_0                    0x00000000
 934 #define SCCR_ENCCM_1                    0x01000000
 935 #define SCCR_ENCCM_2                    0x02000000
 936 #define SCCR_ENCCM_3                    0x03000000
 937
 938 #define SCCR_PCICM                      0x00010000
 939 #define SCCR_PCICM_SHIFT                16
 940
 941 #if defined(CONFIG_MPC834x)
 942 /* SCCR bits - MPC834x specific */
 943 #define SCCR_TSEC1CM                    0xc0000000
 944 #define SCCR_TSEC1CM_SHIFT              30
 945 #define SCCR_TSEC1CM_0                  0x00000000
 946 #define SCCR_TSEC1CM_1                  0x40000000
 947 #define SCCR_TSEC1CM_2                  0x80000000
 948 #define SCCR_TSEC1CM_3                  0xC0000000
 949
 950 #define SCCR_TSEC2CM                    0x30000000
 951 #define SCCR_TSEC2CM_SHIFT              28
 952 #define SCCR_TSEC2CM_0                  0x00000000
 953 #define SCCR_TSEC2CM_1                  0x10000000
 954 #define SCCR_TSEC2CM_2                  0x20000000
 955 #define SCCR_TSEC2CM_3                  0x30000000
 956
 957 /* The MPH must have the same clock ratio as DR, unless its clock disabled */
 958 #define SCCR_USBMPHCM                   0x00c00000
 959 #define SCCR_USBMPHCM_SHIFT             22
 960 #define SCCR_USBDRCM                    0x00300000
 961 #define SCCR_USBDRCM_SHIFT              20
 962 #define SCCR_USBCM                      0x00f00000
 963 #define SCCR_USBCM_SHIFT                20
 964 #define SCCR_USBCM_0                    0x00000000
 965 #define SCCR_USBCM_1                    0x00500000
 966 #define SCCR_USBCM_2                    0x00A00000
 967 #define SCCR_USBCM_3                    0x00F00000
 968
 969 #elif defined(CONFIG_MPC8313)
 970 /* TSEC1 bits are for TSEC2 as well */
 971 #define SCCR_TSEC1CM                    0xc0000000
 972 #define SCCR_TSEC1CM_SHIFT              30
 973 #define SCCR_TSEC1CM_0                  0x00000000
 974 #define SCCR_TSEC1CM_1                  0x40000000
 975 #define SCCR_TSEC1CM_2                  0x80000000
 976 #define SCCR_TSEC1CM_3                  0xC0000000
 977
 978 #define SCCR_TSEC1ON                    0x20000000
 979 #define SCCR_TSEC1ON_SHIFT              29
 980 #define SCCR_TSEC2ON                    0x10000000
 981 #define SCCR_TSEC2ON_SHIFT              28
 982
 983 #define SCCR_USBDRCM                    0x00300000
 984 #define SCCR_USBDRCM_SHIFT              20
 985 #define SCCR_USBDRCM_0                  0x00000000
 986 #define SCCR_USBDRCM_1                  0x00100000
 987 #define SCCR_USBDRCM_2                  0x00200000
 988 #define SCCR_USBDRCM_3                  0x00300000
 989
 990 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 991 /* SCCR bits - MPC8315/MPC8308 specific */
 992 #define SCCR_TSEC1CM                    0xc0000000
 993 #define SCCR_TSEC1CM_SHIFT              30
 994 #define SCCR_TSEC1CM_0                  0x00000000
 995 #define SCCR_TSEC1CM_1                  0x40000000
 996 #define SCCR_TSEC1CM_2                  0x80000000
 997 #define SCCR_TSEC1CM_3                  0xC0000000
 998
 999 #define SCCR_TSEC2CM                    0x30000000
1000 #define SCCR_TSEC2CM_SHIFT              28
1001 #define SCCR_TSEC2CM_0                  0x00000000
1002 #define SCCR_TSEC2CM_1                  0x10000000
1003 #define SCCR_TSEC2CM_2                  0x20000000
1004 #define SCCR_TSEC2CM_3                  0x30000000
1005
1006 #define SCCR_SDHCCM                     0x0c000000
1007 #define SCCR_SDHCCM_SHIFT               26
1008 #define SCCR_SDHCCM_0                   0x00000000
1009 #define SCCR_SDHCCM_1                   0x04000000
1010 #define SCCR_SDHCCM_2                   0x08000000
1011 #define SCCR_SDHCCM_3                   0x0c000000
1012
1013 #define SCCR_USBDRCM                    0x00c00000
1014 #define SCCR_USBDRCM_SHIFT              22
1015 #define SCCR_USBDRCM_0                  0x00000000
1016 #define SCCR_USBDRCM_1                  0x00400000
1017 #define SCCR_USBDRCM_2                  0x00800000
1018 #define SCCR_USBDRCM_3                  0x00c00000
1019
1020 #define SCCR_SATA1CM                    0x00003000
1021 #define SCCR_SATA1CM_SHIFT              12
1022 #define SCCR_SATACM                     0x00003c00
1023 #define SCCR_SATACM_SHIFT               10
1024 #define SCCR_SATACM_0                   0x00000000
1025 #define SCCR_SATACM_1                   0x00001400
1026 #define SCCR_SATACM_2                   0x00002800
1027 #define SCCR_SATACM_3                   0x00003c00
1028
1029 #define SCCR_TDMCM                      0x00000030
1030 #define SCCR_TDMCM_SHIFT                4
1031 #define SCCR_TDMCM_0                    0x00000000
1032 #define SCCR_TDMCM_1                    0x00000010
1033 #define SCCR_TDMCM_2                    0x00000020
1034 #define SCCR_TDMCM_3                    0x00000030
1035
1036 #elif defined(CONFIG_MPC837x)
1037 /* SCCR bits - MPC837x specific */
1038 #define SCCR_TSEC1CM                    0xc0000000
1039 #define SCCR_TSEC1CM_SHIFT              30
1040 #define SCCR_TSEC1CM_0                  0x00000000
1041 #define SCCR_TSEC1CM_1                  0x40000000
1042 #define SCCR_TSEC1CM_2                  0x80000000
1043 #define SCCR_TSEC1CM_3                  0xC0000000
1044
1045 #define SCCR_TSEC2CM                    0x30000000
1046 #define SCCR_TSEC2CM_SHIFT              28
1047 #define SCCR_TSEC2CM_0                  0x00000000
1048 #define SCCR_TSEC2CM_1                  0x10000000
1049 #define SCCR_TSEC2CM_2                  0x20000000
1050 #define SCCR_TSEC2CM_3                  0x30000000
1051
1052 #define SCCR_SDHCCM                     0x0c000000
1053 #define SCCR_SDHCCM_SHIFT               26
1054 #define SCCR_SDHCCM_0                   0x00000000
1055 #define SCCR_SDHCCM_1                   0x04000000
1056 #define SCCR_SDHCCM_2                   0x08000000
1057 #define SCCR_SDHCCM_3                   0x0c000000
1058
1059 #define SCCR_USBDRCM                    0x00c00000
1060 #define SCCR_USBDRCM_SHIFT              22
1061 #define SCCR_USBDRCM_0                  0x00000000
1062 #define SCCR_USBDRCM_1                  0x00400000
1063 #define SCCR_USBDRCM_2                  0x00800000
1064 #define SCCR_USBDRCM_3                  0x00c00000
1065
1066 /* All of the four SATA controllers must have the same clock ratio */
1067 #define SCCR_SATA1CM                    0x000000c0
1068 #define SCCR_SATA1CM_SHIFT              6
1069 #define SCCR_SATACM                     0x000000ff
1070 #define SCCR_SATACM_SHIFT               0
1071 #define SCCR_SATACM_0                   0x00000000
1072 #define SCCR_SATACM_1                   0x00000055
1073 #define SCCR_SATACM_2                   0x000000aa
1074 #define SCCR_SATACM_3                   0x000000ff
1075 #elif defined(CONFIG_MPC8309)
1076 /* SCCR bits - MPC8309 specific */
1077 #define SCCR_SDHCCM                     0x0c000000
1078 #define SCCR_SDHCCM_SHIFT               26
1079 #define SCCR_SDHCCM_0                   0x00000000
1080 #define SCCR_SDHCCM_1                   0x04000000
1081 #define SCCR_SDHCCM_2                   0x08000000
1082 #define SCCR_SDHCCM_3                   0x0c000000
1083
1084 #define SCCR_USBDRCM                    0x00c00000
1085 #define SCCR_USBDRCM_SHIFT              22
1086 #define SCCR_USBDRCM_0                  0x00000000
1087 #define SCCR_USBDRCM_1                  0x00400000
1088 #define SCCR_USBDRCM_2                  0x00800000
1089 #define SCCR_USBDRCM_3                  0x00c00000
1090 #endif
1091
1092 #define SCCR_PCIEXP1CM                  0x00300000
1093 #define SCCR_PCIEXP1CM_SHIFT            20
1094 #define SCCR_PCIEXP1CM_0                0x00000000
1095 #define SCCR_PCIEXP1CM_1                0x00100000
1096 #define SCCR_PCIEXP1CM_2                0x00200000
1097 #define SCCR_PCIEXP1CM_3                0x00300000
1098
1099 #define SCCR_PCIEXP2CM                  0x000c0000
1100 #define SCCR_PCIEXP2CM_SHIFT            18
1101 #define SCCR_PCIEXP2CM_0                0x00000000
1102 #define SCCR_PCIEXP2CM_1                0x00040000
1103 #define SCCR_PCIEXP2CM_2                0x00080000
1104 #define SCCR_PCIEXP2CM_3                0x000c0000
1105
1106 /*
1107  * CSn_BDNS - Chip Select memory Bounds Register
1108  */
1109 #define CSBNDS_SA                       0x00FF0000
1110 #define CSBNDS_SA_SHIFT                 8
1111 #define CSBNDS_EA                       0x000000FF
1112 #define CSBNDS_EA_SHIFT                 24
1113
1114 /*
1115  * CSn_CONFIG - Chip Select Configuration Register
1116  */
1117 #define CSCONFIG_EN                     0x80000000
1118 #define CSCONFIG_AP                     0x00800000
1119 #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
1120 #define CSCONFIG_ODT_RD_NEVER           0x00000000
1121 #define CSCONFIG_ODT_RD_ONLY_CURRENT    0x00100000
1122 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS   0x00200000
1123 #define CSCONFIG_ODT_RD_ALL             0x00400000
1124 #define CSCONFIG_ODT_WR_NEVER           0x00000000
1125 #define CSCONFIG_ODT_WR_ONLY_CURRENT    0x00010000
1126 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS   0x00020000
1127 #define CSCONFIG_ODT_WR_ALL             0x00040000
1128 #elif defined(CONFIG_MPC832x)
1129 #define CSCONFIG_ODT_RD_CFG             0x00400000
1130 #define CSCONFIG_ODT_WR_CFG             0x00040000
1131 #elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
1132 #define CSCONFIG_ODT_RD_NEVER           0x00000000
1133 #define CSCONFIG_ODT_RD_ONLY_CURRENT    0x00100000
1134 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS   0x00200000
1135 #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
1136 #define CSCONFIG_ODT_RD_ALL             0x00400000
1137 #define CSCONFIG_ODT_WR_NEVER           0x00000000
1138 #define CSCONFIG_ODT_WR_ONLY_CURRENT    0x00010000
1139 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS   0x00020000
1140 #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
1141 #define CSCONFIG_ODT_WR_ALL             0x00040000
1142 #endif
1143 #define CSCONFIG_BANK_BIT_3             0x00004000
1144 #define CSCONFIG_ROW_BIT                0x00000700
1145 #define CSCONFIG_ROW_BIT_12             0x00000000
1146 #define CSCONFIG_ROW_BIT_13             0x00000100
1147 #define CSCONFIG_ROW_BIT_14             0x00000200
1148 #define CSCONFIG_COL_BIT                0x00000007
1149 #define CSCONFIG_COL_BIT_8              0x00000000
1150 #define CSCONFIG_COL_BIT_9              0x00000001
1151 #define CSCONFIG_COL_BIT_10             0x00000002
1152 #define CSCONFIG_COL_BIT_11             0x00000003
1153
1154 /*
1155  * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
1156  */
1157 #define TIMING_CFG0_RWT                 0xC0000000
1158 #define TIMING_CFG0_RWT_SHIFT           30
1159 #define TIMING_CFG0_WRT                 0x30000000
1160 #define TIMING_CFG0_WRT_SHIFT           28
1161 #define TIMING_CFG0_RRT                 0x0C000000
1162 #define TIMING_CFG0_RRT_SHIFT           26
1163 #define TIMING_CFG0_WWT                 0x03000000
1164 #define TIMING_CFG0_WWT_SHIFT           24
1165 #define TIMING_CFG0_ACT_PD_EXIT         0x00700000
1166 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT   20
1167 #define TIMING_CFG0_PRE_PD_EXIT         0x00070000
1168 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT   16
1169 #define TIMING_CFG0_ODT_PD_EXIT         0x00000F00
1170 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT   8
1171 #define TIMING_CFG0_MRS_CYC             0x0000000F
1172 #define TIMING_CFG0_MRS_CYC_SHIFT       0
1173
1174 /*
1175  * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
1176  */
1177 #define TIMING_CFG1_PRETOACT            0x70000000
1178 #define TIMING_CFG1_PRETOACT_SHIFT      28
1179 #define TIMING_CFG1_ACTTOPRE            0x0F000000
1180 #define TIMING_CFG1_ACTTOPRE_SHIFT      24
1181 #define TIMING_CFG1_ACTTORW             0x00700000
1182 #define TIMING_CFG1_ACTTORW_SHIFT       20
1183 #define TIMING_CFG1_CASLAT              0x00070000
1184 #define TIMING_CFG1_CASLAT_SHIFT        16
1185 #define TIMING_CFG1_REFREC              0x0000F000
1186 #define TIMING_CFG1_REFREC_SHIFT        12
1187 #define TIMING_CFG1_WRREC               0x00000700
1188 #define TIMING_CFG1_WRREC_SHIFT         8
1189 #define TIMING_CFG1_ACTTOACT            0x00000070
1190 #define TIMING_CFG1_ACTTOACT_SHIFT      4
1191 #define TIMING_CFG1_WRTORD              0x00000007
1192 #define TIMING_CFG1_WRTORD_SHIFT        0
1193 #define TIMING_CFG1_CASLAT_20           0x00030000      /* CAS latency = 2.0 */
1194 #define TIMING_CFG1_CASLAT_25           0x00040000      /* CAS latency = 2.5 */
1195 #define TIMING_CFG1_CASLAT_30           0x00050000      /* CAS latency = 3.0 */
1196 #define TIMING_CFG1_CASLAT_35           0x00060000      /* CAS latency = 3.5 */
1197 #define TIMING_CFG1_CASLAT_40           0x00070000      /* CAS latency = 4.0 */
1198 #define TIMING_CFG1_CASLAT_45           0x00080000      /* CAS latency = 4.5 */
1199 #define TIMING_CFG1_CASLAT_50           0x00090000      /* CAS latency = 5.0 */
1200
1201 /*
1202  * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
1203  */
1204 #define TIMING_CFG2_CPO                 0x0F800000
1205 #define TIMING_CFG2_CPO_SHIFT           23
1206 #define TIMING_CFG2_ACSM                0x00080000
1207 #define TIMING_CFG2_WR_DATA_DELAY       0x00001C00
1208 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
1209 /* default (= CASLAT + 1) */
1210 #define TIMING_CFG2_CPO_DEF             0x00000000
1211
1212 #define TIMING_CFG2_ADD_LAT             0x70000000
1213 #define TIMING_CFG2_ADD_LAT_SHIFT       28
1214 #define TIMING_CFG2_WR_LAT_DELAY        0x00380000
1215 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT  19
1216 #define TIMING_CFG2_RD_TO_PRE           0x0000E000
1217 #define TIMING_CFG2_RD_TO_PRE_SHIFT     13
1218 #define TIMING_CFG2_CKE_PLS             0x000001C0
1219 #define TIMING_CFG2_CKE_PLS_SHIFT       6
1220 #define TIMING_CFG2_FOUR_ACT            0x0000003F
1221 #define TIMING_CFG2_FOUR_ACT_SHIFT      0
1222
1223 /*
1224  * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
1225  */
1226 #define TIMING_CFG3_EXT_REFREC          0x00070000
1227 #define TIMING_CFG3_EXT_REFREC_SHIFT    16
1228
1229 /*
1230  * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
1231  */
1232 #define SDRAM_CFG_MEM_EN                0x80000000
1233 #define SDRAM_CFG_SREN                  0x40000000
1234 #define SDRAM_CFG_ECC_EN                0x20000000
1235 #define SDRAM_CFG_RD_EN                 0x10000000
1236 #define SDRAM_CFG_SDRAM_TYPE_DDR1       0x02000000
1237 #define SDRAM_CFG_SDRAM_TYPE_DDR2       0x03000000
1238 #define SDRAM_CFG_SDRAM_TYPE_MASK       0x07000000
1239 #define SDRAM_CFG_SDRAM_TYPE_SHIFT      24
1240 #define SDRAM_CFG_DYN_PWR               0x00200000
1241 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
1242 #define SDRAM_CFG_DBW_MASK              0x00180000
1243 #define SDRAM_CFG_DBW_16                0x00100000
1244 #define SDRAM_CFG_DBW_32                0x00080000
1245 #else
1246 #define SDRAM_CFG_32_BE                 0x00080000
1247 #endif
1248 #if !defined(CONFIG_MPC8308)
1249 #define SDRAM_CFG_8_BE                  0x00040000
1250 #endif
1251 #define SDRAM_CFG_NCAP                  0x00020000
1252 #define SDRAM_CFG_2T_EN                 0x00008000
1253 #define SDRAM_CFG_HSE                   0x00000008
1254 #define SDRAM_CFG_BI                    0x00000001
1255
1256 /*
1257  * DDR_SDRAM_MODE - DDR SDRAM Mode Register
1258  */
1259 #define SDRAM_MODE_ESD                  0xFFFF0000
1260 #define SDRAM_MODE_ESD_SHIFT            16
1261 #define SDRAM_MODE_SD                   0x0000FFFF
1262 #define SDRAM_MODE_SD_SHIFT             0
1263 /* select extended mode reg */
1264 #define DDR_MODE_EXT_MODEREG            0x4000
1265 /* operating mode, mask */
1266 #define DDR_MODE_EXT_OPMODE             0x3FF8
1267 #define DDR_MODE_EXT_OP_NORMAL          0x0000          /* normal operation */
1268 /* QFC / compatibility, mask */
1269 #define DDR_MODE_QFC                    0x0004
1270 /* compatible to older SDRAMs */
1271 #define DDR_MODE_QFC_COMP               0x0000
1272 /* weak drivers */
1273 #define DDR_MODE_WEAK                   0x0002
1274 /* disable DLL */
1275 #define DDR_MODE_DLL_DIS                0x0001
1276 /* CAS latency, mask */
1277 #define DDR_MODE_CASLAT                 0x0070
1278 #define DDR_MODE_CASLAT_15              0x0010          /* CAS latency 1.5 */
1279 #define DDR_MODE_CASLAT_20              0x0020          /* CAS latency 2 */
1280 #define DDR_MODE_CASLAT_25              0x0060          /* CAS latency 2.5 */
1281 #define DDR_MODE_CASLAT_30              0x0030          /* CAS latency 3 */
1282 /* sequential burst */
1283 #define DDR_MODE_BTYPE_SEQ              0x0000
1284 /* interleaved burst */
1285 #define DDR_MODE_BTYPE_ILVD             0x0008
1286 #define DDR_MODE_BLEN_2                 0x0001          /* burst length 2 */
1287 #define DDR_MODE_BLEN_4                 0x0002          /* burst length 4 */
1288 /* exact value for 7.8125us */
1289 #define DDR_REFINT_166MHZ_7US           1302
1290 /* use 256 cycles as a starting point */
1291 #define DDR_BSTOPRE                     256
1292 /* select mode register */
1293 #define DDR_MODE_MODEREG                0x0000
1294
1295 /*
1296  * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
1297  */
1298 #define SDRAM_INTERVAL_REFINT           0x3FFF0000
1299 #define SDRAM_INTERVAL_REFINT_SHIFT     16
1300 #define SDRAM_INTERVAL_BSTOPRE          0x00003FFF
1301 #define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
1302
1303 /*
1304  * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
1305  */
1306 #define DDR_SDRAM_CLK_CNTL_SS_EN                0x80000000
1307 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025       0x01000000
1308 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05        0x02000000
1309 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075       0x03000000
1310 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1         0x04000000
1311
1312 /*
1313  * ECC_ERR_INJECT - Memory data path error injection mask ECC
1314  */
1315 /* ECC Mirror Byte */
1316 #define ECC_ERR_INJECT_EMB              (0x80000000 >> 22)
1317 /* Error Injection Enable */
1318 #define ECC_ERR_INJECT_EIEN             (0x80000000 >> 23)
1319 /* ECC Erroe Injection Enable */
1320 #define ECC_ERR_INJECT_EEIM             (0xff000000 >> 24)
1321 #define ECC_ERR_INJECT_EEIM_SHIFT       0
1322
1323 /*
1324  * CAPTURE_ECC - Memory data path read capture ECC
1325  */
1326 #define CAPTURE_ECC_ECE                 (0xff000000 >> 24)
1327 #define CAPTURE_ECC_ECE_SHIFT           0
1328
1329 /*
1330  * ERR_DETECT - Memory error detect
1331  */
1332 /* Multiple Memory Errors */
1333 #define ECC_ERROR_DETECT_MME            (0x80000000 >> 0)
1334 /* Multiple-Bit Error */
1335 #define ECC_ERROR_DETECT_MBE            (0x80000000 >> 28)
1336 /* Single-Bit ECC Error Pickup */
1337 #define ECC_ERROR_DETECT_SBE            (0x80000000 >> 29)
1338 /* Memory Select Error */
1339 #define ECC_ERROR_DETECT_MSE            (0x80000000 >> 31)
1340
1341 /*
1342  * ERR_DISABLE - Memory error disable
1343  */
1344 /* Multiple-Bit ECC Error Disable */
1345 #define ECC_ERROR_DISABLE_MBED          (0x80000000 >> 28)
1346 /* Sinle-Bit ECC Error disable */
1347 #define ECC_ERROR_DISABLE_SBED          (0x80000000 >> 29)
1348 /* Memory Select Error Disable */
1349 #define ECC_ERROR_DISABLE_MSED          (0x80000000 >> 31)
1350 #define ECC_ERROR_ENABLE                (~(ECC_ERROR_DISABLE_MSED | \
1351                                                 ECC_ERROR_DISABLE_SBED | \
1352                                                 ECC_ERROR_DISABLE_MBED))
1353
1354 /*
1355  * ERR_INT_EN - Memory error interrupt enable
1356  */
1357 /* Multiple-Bit ECC Error Interrupt Enable */
1358 #define ECC_ERR_INT_EN_MBEE             (0x80000000 >> 28)
1359 /* Single-Bit ECC Error Interrupt Enable */
1360 #define ECC_ERR_INT_EN_SBEE             (0x80000000 >> 29)
1361 /* Memory Select Error Interrupt Enable */
1362 #define ECC_ERR_INT_EN_MSEE             (0x80000000 >> 31)
1363 #define ECC_ERR_INT_DISABLE             (~(ECC_ERR_INT_EN_MBEE | \
1364                                                 ECC_ERR_INT_EN_SBEE | \
1365                                                 ECC_ERR_INT_EN_MSEE))
1366
1367 /*
1368  * CAPTURE_ATTRIBUTES - Memory error attributes capture
1369  */
1370 /* Data Beat Num */
1371 #define ECC_CAPT_ATTR_BNUM              (0xe0000000 >> 1)
1372 #define ECC_CAPT_ATTR_BNUM_SHIFT        28
1373 /* Transaction Size */
1374 #define ECC_CAPT_ATTR_TSIZ              (0xc0000000 >> 6)
1375 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW      0
1376 #define ECC_CAPT_ATTR_TSIZ_ONE_DW       1
1377 #define ECC_CAPT_ATTR_TSIZ_TWO_DW       2
1378 #define ECC_CAPT_ATTR_TSIZ_THREE_DW     3
1379 #define ECC_CAPT_ATTR_TSIZ_SHIFT        24
1380 /* Transaction Source */
1381 #define ECC_CAPT_ATTR_TSRC              (0xf8000000 >> 11)
1382 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
1383 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1384 #define ECC_CAPT_ATTR_TSRC_TSEC1        0x4
1385 #define ECC_CAPT_ATTR_TSRC_TSEC2        0x5
1386 #define ECC_CAPT_ATTR_TSRC_USB          (0x06|0x07)
1387 #define ECC_CAPT_ATTR_TSRC_ENCRYPT      0x8
1388 #define ECC_CAPT_ATTR_TSRC_I2C          0x9
1389 #define ECC_CAPT_ATTR_TSRC_JTAG         0xA
1390 #define ECC_CAPT_ATTR_TSRC_PCI1         0xD
1391 #define ECC_CAPT_ATTR_TSRC_PCI2         0xE
1392 #define ECC_CAPT_ATTR_TSRC_DMA          0xF
1393 #define ECC_CAPT_ATTR_TSRC_SHIFT        16
1394 /* Transaction Type */
1395 #define ECC_CAPT_ATTR_TTYP              (0xe0000000 >> 18)
1396 #define ECC_CAPT_ATTR_TTYP_WRITE        0x1
1397 #define ECC_CAPT_ATTR_TTYP_READ         0x2
1398 #define ECC_CAPT_ATTR_TTYP_R_M_W        0x3
1399 #define ECC_CAPT_ATTR_TTYP_SHIFT        12
1400 #define ECC_CAPT_ATTR_VLD               (0x80000000 >> 31)      /* Valid */
1401
1402 /*
1403  * ERR_SBE - Single bit ECC memory error management
1404  */
1405 /* Single-Bit Error Threshold 0..255 */
1406 #define ECC_ERROR_MAN_SBET              (0xff000000 >> 8)
1407 #define ECC_ERROR_MAN_SBET_SHIFT        16
1408 /* Single Bit Error Counter 0..255 */
1409 #define ECC_ERROR_MAN_SBEC              (0xff000000 >> 24)
1410 #define ECC_ERROR_MAN_SBEC_SHIFT        0
1411
1412 /*
1413  * CONFIG_ADDRESS - PCI Config Address Register
1414  */
1415 #define PCI_CONFIG_ADDRESS_EN           0x80000000
1416 #define PCI_CONFIG_ADDRESS_BN_SHIFT     16
1417 #define PCI_CONFIG_ADDRESS_BN_MASK      0x00ff0000
1418 #define PCI_CONFIG_ADDRESS_DN_SHIFT     11
1419 #define PCI_CONFIG_ADDRESS_DN_MASK      0x0000f800
1420 #define PCI_CONFIG_ADDRESS_FN_SHIFT     8
1421 #define PCI_CONFIG_ADDRESS_FN_MASK      0x00000700
1422 #define PCI_CONFIG_ADDRESS_RN_SHIFT     0
1423 #define PCI_CONFIG_ADDRESS_RN_MASK      0x000000fc
1424
1425 /*
1426  * POTAR - PCI Outbound Translation Address Register
1427  */
1428 #define POTAR_TA_MASK                   0x000fffff
1429
1430 /*
1431  * POBAR - PCI Outbound Base Address Register
1432  */
1433 #define POBAR_BA_MASK                   0x000fffff
1434
1435 /*
1436  * POCMR - PCI Outbound Comparision Mask Register
1437  */
1438 #define POCMR_EN                        0x80000000
1439 /* 0-memory space 1-I/O space */
1440 #define POCMR_IO                        0x40000000
1441 #define POCMR_SE                        0x20000000      /* streaming enable */
1442 #define POCMR_DST                       0x10000000      /* 0-PCI1 1-PCI2 */
1443 #define POCMR_CM_MASK                   0x000fffff
1444 #define POCMR_CM_4G                     0x00000000
1445 #define POCMR_CM_2G                     0x00080000
1446 #define POCMR_CM_1G                     0x000C0000
1447 #define POCMR_CM_512M                   0x000E0000
1448 #define POCMR_CM_256M                   0x000F0000
1449 #define POCMR_CM_128M                   0x000F8000
1450 #define POCMR_CM_64M                    0x000FC000
1451 #define POCMR_CM_32M                    0x000FE000
1452 #define POCMR_CM_16M                    0x000FF000
1453 #define POCMR_CM_8M                     0x000FF800
1454 #define POCMR_CM_4M                     0x000FFC00
1455 #define POCMR_CM_2M                     0x000FFE00
1456 #define POCMR_CM_1M                     0x000FFF00
1457 #define POCMR_CM_512K                   0x000FFF80
1458 #define POCMR_CM_256K                   0x000FFFC0
1459 #define POCMR_CM_128K                   0x000FFFE0
1460 #define POCMR_CM_64K                    0x000FFFF0
1461 #define POCMR_CM_32K                    0x000FFFF8
1462 #define POCMR_CM_16K                    0x000FFFFC
1463 #define POCMR_CM_8K                     0x000FFFFE
1464 #define POCMR_CM_4K                     0x000FFFFF
1465
1466 /*
1467  * PITAR - PCI Inbound Translation Address Register
1468  */
1469 #define PITAR_TA_MASK                   0x000fffff
1470
1471 /*
1472  * PIBAR - PCI Inbound Base/Extended Address Register
1473  */
1474 #define PIBAR_MASK                      0xffffffff
1475 #define PIEBAR_EBA_MASK                 0x000fffff
1476
1477 /*
1478  * PIWAR - PCI Inbound Windows Attributes Register
1479  */
1480 #define PIWAR_EN                        0x80000000
1481 #define PIWAR_PF                        0x20000000
1482 #define PIWAR_RTT_MASK                  0x000f0000
1483 #define PIWAR_RTT_NO_SNOOP              0x00040000
1484 #define PIWAR_RTT_SNOOP                 0x00050000
1485 #define PIWAR_WTT_MASK                  0x0000f000
1486 #define PIWAR_WTT_NO_SNOOP              0x00004000
1487 #define PIWAR_WTT_SNOOP                 0x00005000
1488 #define PIWAR_IWS_MASK                  0x0000003F
1489 #define PIWAR_IWS_4K                    0x0000000B
1490 #define PIWAR_IWS_8K                    0x0000000C
1491 #define PIWAR_IWS_16K                   0x0000000D
1492 #define PIWAR_IWS_32K                   0x0000000E
1493 #define PIWAR_IWS_64K                   0x0000000F
1494 #define PIWAR_IWS_128K                  0x00000010
1495 #define PIWAR_IWS_256K                  0x00000011
1496 #define PIWAR_IWS_512K                  0x00000012
1497 #define PIWAR_IWS_1M                    0x00000013
1498 #define PIWAR_IWS_2M                    0x00000014
1499 #define PIWAR_IWS_4M                    0x00000015
1500 #define PIWAR_IWS_8M                    0x00000016
1501 #define PIWAR_IWS_16M                   0x00000017
1502 #define PIWAR_IWS_32M                   0x00000018
1503 #define PIWAR_IWS_64M                   0x00000019
1504 #define PIWAR_IWS_128M                  0x0000001A
1505 #define PIWAR_IWS_256M                  0x0000001B
1506 #define PIWAR_IWS_512M                  0x0000001C
1507 #define PIWAR_IWS_1G                    0x0000001D
1508 #define PIWAR_IWS_2G                    0x0000001E
1509
1510 /*
1511  * PMCCR1 - PCI Configuration Register 1
1512  */
1513 #define PMCCR1_POWER_OFF                0x00000020
1514
1515 /*
1516  * DDRCDR - DDR Control Driver Register
1517  */
1518 #define DDRCDR_DHC_EN           0x80000000
1519 #define DDRCDR_EN               0x40000000
1520 #define DDRCDR_PZ               0x3C000000
1521 #define DDRCDR_PZ_MAXZ          0x00000000
1522 #define DDRCDR_PZ_HIZ           0x20000000
1523 #define DDRCDR_PZ_NOMZ          0x30000000
1524 #define DDRCDR_PZ_LOZ           0x38000000
1525 #define DDRCDR_PZ_MINZ          0x3C000000
1526 #define DDRCDR_NZ               0x3C000000
1527 #define DDRCDR_NZ_MAXZ          0x00000000
1528 #define DDRCDR_NZ_HIZ           0x02000000
1529 #define DDRCDR_NZ_NOMZ          0x03000000
1530 #define DDRCDR_NZ_LOZ           0x03800000
1531 #define DDRCDR_NZ_MINZ          0x03C00000
1532 #define DDRCDR_ODT              0x00080000
1533 #define DDRCDR_DDR_CFG          0x00040000
1534 #define DDRCDR_M_ODR            0x00000002
1535 #define DDRCDR_Q_DRN            0x00000001
1536
1537 /*
1538  * PCIE Bridge Register
1539  */
1540 #define PEX_CSB_CTRL_OBPIOE     0x00000001
1541 #define PEX_CSB_CTRL_IBPIOE     0x00000002
1542 #define PEX_CSB_CTRL_WDMAE      0x00000004
1543 #define PEX_CSB_CTRL_RDMAE      0x00000008
1544
1545 #define PEX_CSB_OBCTRL_PIOE     0x00000001
1546 #define PEX_CSB_OBCTRL_MEMWE    0x00000002
1547 #define PEX_CSB_OBCTRL_IOWE     0x00000004
1548 #define PEX_CSB_OBCTRL_CFGWE    0x00000008
1549
1550 #define PEX_CSB_IBCTRL_PIOE     0x00000001
1551
1552 #define PEX_OWAR_EN             0x00000001
1553 #define PEX_OWAR_TYPE_CFG       0x00000000
1554 #define PEX_OWAR_TYPE_IO        0x00000002
1555 #define PEX_OWAR_TYPE_MEM       0x00000004
1556 #define PEX_OWAR_RLXO           0x00000008
1557 #define PEX_OWAR_NANP           0x00000010
1558 #define PEX_OWAR_SIZE           0xFFFFF000
1559
1560 #define PEX_IWAR_EN             0x00000001
1561 #define PEX_IWAR_TYPE_INT       0x00000000
1562 #define PEX_IWAR_TYPE_PF        0x00000004
1563 #define PEX_IWAR_TYPE_NO_PF     0x00000006
1564 #define PEX_IWAR_NSOV           0x00000008
1565 #define PEX_IWAR_NSNP           0x00000010
1566 #define PEX_IWAR_SIZE           0xFFFFF000
1567 #define PEX_IWAR_SIZE_1M        0x000FF000
1568 #define PEX_IWAR_SIZE_2M        0x001FF000
1569 #define PEX_IWAR_SIZE_4M        0x003FF000
1570 #define PEX_IWAR_SIZE_8M        0x007FF000
1571 #define PEX_IWAR_SIZE_16M       0x00FFF000
1572 #define PEX_IWAR_SIZE_32M       0x01FFF000
1573 #define PEX_IWAR_SIZE_64M       0x03FFF000
1574 #define PEX_IWAR_SIZE_128M      0x07FFF000
1575 #define PEX_IWAR_SIZE_256M      0x0FFFF000
1576
1577 #define PEX_GCLK_RATIO          0x440
1578
1579 #ifndef __ASSEMBLY__
1580 struct pci_region;
1581 void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
1582 void mpc83xx_pcislave_unlock(int bus);
1583 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
1584 #endif
1585
1586 #endif  /* __MPC83XX_H__ */