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1 /*
2  * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12
13 #ifndef __MPC83XX_H__
14 #define __MPC83XX_H__
15
16 #include <config.h>
17 #include <asm/fsl_lbc.h>
18 #if defined(CONFIG_E300)
19 #include <asm/e300.h>
20 #endif
21
22 /*
23  * MPC83xx cpu provide RCR register to do reset thing specially
24  */
25 #define MPC83xx_RESET
26
27 /*
28  * System reset offset (PowerPC standard)
29  */
30 #define EXC_OFF_SYS_RESET               0x0100
31 #define _START_OFFSET                   EXC_OFF_SYS_RESET
32
33 /*
34  * IMMRBAR - Internal Memory Register Base Address
35  */
36 #ifndef CONFIG_DEFAULT_IMMR
37 /* Default IMMR base address */
38 #define CONFIG_DEFAULT_IMMR             0xFF400000
39 #endif
40 /* Register offset to immr */
41 #define IMMRBAR                         0x0000
42 #define IMMRBAR_BASE_ADDR               0xFFF00000      /* Base addr. mask */
43 #define IMMRBAR_RES                     ~(IMMRBAR_BASE_ADDR)
44
45 /*
46  * LAWBAR - Local Access Window Base Address Register
47  */
48 /* Register offset to immr */
49 #define LBLAWBAR0                       0x0020
50 #define LBLAWAR0                        0x0024
51 #define LBLAWBAR1                       0x0028
52 #define LBLAWAR1                        0x002C
53 #define LBLAWBAR2                       0x0030
54 #define LBLAWAR2                        0x0034
55 #define LBLAWBAR3                       0x0038
56 #define LBLAWAR3                        0x003C
57 #define LAWBAR_BAR                      0xFFFFF000      /* Base addr. mask */
58
59 /*
60  * SPRIDR - System Part and Revision ID Register
61  */
62 #define SPRIDR_PARTID                   0xFFFF0000      /* Part Id */
63 #define SPRIDR_REVID                    0x0000FFFF      /* Revision Id */
64
65 #if defined(CONFIG_MPC834x)
66 #define REVID_MAJOR(spridr)             ((spridr & 0x0000FF00) >> 8)
67 #define REVID_MINOR(spridr)             (spridr & 0x000000FF)
68 #else
69 #define REVID_MAJOR(spridr)             ((spridr & 0x000000F0) >> 4)
70 #define REVID_MINOR(spridr)             (spridr & 0x0000000F)
71 #endif
72
73 #define PARTID_NO_E(spridr)             ((spridr & 0xFFFE0000) >> 16)
74 #define SPR_FAMILY(spridr)              ((spridr & 0xFFF00000) >> 20)
75
76 #define SPR_8308                        0x8100
77 #define SPR_831X_FAMILY                 0x80B
78 #define SPR_8311                        0x80B2
79 #define SPR_8313                        0x80B0
80 #define SPR_8314                        0x80B6
81 #define SPR_8315                        0x80B4
82 #define SPR_832X_FAMILY                 0x806
83 #define SPR_8321                        0x8066
84 #define SPR_8323                        0x8062
85 #define SPR_834X_FAMILY                 0x803
86 #define SPR_8343                        0x8036
87 #define SPR_8347_TBGA_                  0x8032
88 #define SPR_8347_PBGA_                  0x8034
89 #define SPR_8349                        0x8030
90 #define SPR_836X_FAMILY                 0x804
91 #define SPR_8358_TBGA_                  0x804A
92 #define SPR_8358_PBGA_                  0x804E
93 #define SPR_8360                        0x8048
94 #define SPR_837X_FAMILY                 0x80C
95 #define SPR_8377                        0x80C6
96 #define SPR_8378                        0x80C4
97 #define SPR_8379                        0x80C2
98
99 /*
100  * SPCR - System Priority Configuration Register
101  */
102 /* PCI Highest Priority Enable */
103 #define SPCR_PCIHPE                     0x10000000
104 #define SPCR_PCIHPE_SHIFT               (31-3)
105 /* PCI bridge system bus request priority */
106 #define SPCR_PCIPR                      0x03000000
107 #define SPCR_PCIPR_SHIFT                (31-7)
108 #define SPCR_OPT                        0x00800000      /* Optimize */
109 #define SPCR_OPT_SHIFT                  (31-8)
110 /* E300 PowerPC core time base unit enable */
111 #define SPCR_TBEN                       0x00400000
112 #define SPCR_TBEN_SHIFT                 (31-9)
113 /* E300 PowerPC Core system bus request priority */
114 #define SPCR_COREPR                     0x00300000
115 #define SPCR_COREPR_SHIFT               (31-11)
116
117 #if defined(CONFIG_MPC834x)
118 /* SPCR bits - MPC8349 specific */
119 /* TSEC1 data priority */
120 #define SPCR_TSEC1DP                    0x00003000
121 #define SPCR_TSEC1DP_SHIFT              (31-19)
122 /* TSEC1 buffer descriptor priority */
123 #define SPCR_TSEC1BDP                   0x00000C00
124 #define SPCR_TSEC1BDP_SHIFT             (31-21)
125 /* TSEC1 emergency priority */
126 #define SPCR_TSEC1EP                    0x00000300
127 #define SPCR_TSEC1EP_SHIFT              (31-23)
128 /* TSEC2 data priority */
129 #define SPCR_TSEC2DP                    0x00000030
130 #define SPCR_TSEC2DP_SHIFT              (31-27)
131 /* TSEC2 buffer descriptor priority */
132 #define SPCR_TSEC2BDP                   0x0000000C
133 #define SPCR_TSEC2BDP_SHIFT             (31-29)
134 /* TSEC2 emergency priority */
135 #define SPCR_TSEC2EP                    0x00000003
136 #define SPCR_TSEC2EP_SHIFT              (31-31)
137
138 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
139         defined(CONFIG_MPC837x)
140 /* SPCR bits - MPC8308, MPC831x and MPC837x specific */
141 /* TSEC data priority */
142 #define SPCR_TSECDP                     0x00003000
143 #define SPCR_TSECDP_SHIFT               (31-19)
144 /* TSEC buffer descriptor priority */
145 #define SPCR_TSECBDP                    0x00000C00
146 #define SPCR_TSECBDP_SHIFT              (31-21)
147 /* TSEC emergency priority */
148 #define SPCR_TSECEP                     0x00000300
149 #define SPCR_TSECEP_SHIFT               (31-23)
150 #endif
151
152 /* SICRL/H - System I/O Configuration Register Low/High
153  */
154 #if defined(CONFIG_MPC834x)
155 /* SICRL bits - MPC8349 specific */
156 #define SICRL_LDP_A                     0x80000000
157 #define SICRL_USB1                      0x40000000
158 #define SICRL_USB0                      0x20000000
159 #define SICRL_UART                      0x0C000000
160 #define SICRL_GPIO1_A                   0x02000000
161 #define SICRL_GPIO1_B                   0x01000000
162 #define SICRL_GPIO1_C                   0x00800000
163 #define SICRL_GPIO1_D                   0x00400000
164 #define SICRL_GPIO1_E                   0x00200000
165 #define SICRL_GPIO1_F                   0x00180000
166 #define SICRL_GPIO1_G                   0x00040000
167 #define SICRL_GPIO1_H                   0x00020000
168 #define SICRL_GPIO1_I                   0x00010000
169 #define SICRL_GPIO1_J                   0x00008000
170 #define SICRL_GPIO1_K                   0x00004000
171 #define SICRL_GPIO1_L                   0x00003000
172
173 /* SICRH bits - MPC8349 specific */
174 #define SICRH_DDR                       0x80000000
175 #define SICRH_TSEC1_A                   0x10000000
176 #define SICRH_TSEC1_B                   0x08000000
177 #define SICRH_TSEC1_C                   0x04000000
178 #define SICRH_TSEC1_D                   0x02000000
179 #define SICRH_TSEC1_E                   0x01000000
180 #define SICRH_TSEC1_F                   0x00800000
181 #define SICRH_TSEC2_A                   0x00400000
182 #define SICRH_TSEC2_B                   0x00200000
183 #define SICRH_TSEC2_C                   0x00100000
184 #define SICRH_TSEC2_D                   0x00080000
185 #define SICRH_TSEC2_E                   0x00040000
186 #define SICRH_TSEC2_F                   0x00020000
187 #define SICRH_TSEC2_G                   0x00010000
188 #define SICRH_TSEC2_H                   0x00008000
189 #define SICRH_GPIO2_A                   0x00004000
190 #define SICRH_GPIO2_B                   0x00002000
191 #define SICRH_GPIO2_C                   0x00001000
192 #define SICRH_GPIO2_D                   0x00000800
193 #define SICRH_GPIO2_E                   0x00000400
194 #define SICRH_GPIO2_F                   0x00000200
195 #define SICRH_GPIO2_G                   0x00000180
196 #define SICRH_GPIO2_H                   0x00000060
197 #define SICRH_TSOBI1                    0x00000002
198 #define SICRH_TSOBI2                    0x00000001
199
200 #elif defined(CONFIG_MPC8360)
201 /* SICRL bits - MPC8360 specific */
202 #define SICRL_LDP_A                     0xC0000000
203 #define SICRL_LCLK_1                    0x10000000
204 #define SICRL_LCLK_2                    0x08000000
205 #define SICRL_SRCID_A                   0x03000000
206 #define SICRL_IRQ_CKSTP_A               0x00C00000
207
208 /* SICRH bits - MPC8360 specific */
209 #define SICRH_DDR                       0x80000000
210 #define SICRH_SECONDARY_DDR             0x40000000
211 #define SICRH_SDDROE                    0x20000000
212 #define SICRH_IRQ3                      0x10000000
213 #define SICRH_UC1EOBI                   0x00000004
214 #define SICRH_UC2E1OBI                  0x00000002
215 #define SICRH_UC2E2OBI                  0x00000001
216
217 #elif defined(CONFIG_MPC832x)
218 /* SICRL bits - MPC832x specific */
219 #define SICRL_LDP_LCS_A                 0x80000000
220 #define SICRL_IRQ_CKS                   0x20000000
221 #define SICRL_PCI_MSRC                  0x10000000
222 #define SICRL_URT_CTPR                  0x06000000
223 #define SICRL_IRQ_CTPR                  0x00C00000
224
225 #elif defined(CONFIG_MPC8313)
226 /* SICRL bits - MPC8313 specific */
227 #define SICRL_LBC                       0x30000000
228 #define SICRL_UART                      0x0C000000
229 #define SICRL_SPI_A                     0x03000000
230 #define SICRL_SPI_B                     0x00C00000
231 #define SICRL_SPI_C                     0x00300000
232 #define SICRL_SPI_D                     0x000C0000
233 #define SICRL_USBDR_11                  0x00000C00
234 #define SICRL_USBDR_10                  0x00000800
235 #define SICRL_USBDR_01                  0x00000400
236 #define SICRL_USBDR_00                  0x00000000
237 #define SICRL_ETSEC1_A                  0x0000000C
238 #define SICRL_ETSEC2_A                  0x00000003
239
240 /* SICRH bits - MPC8313 specific */
241 #define SICRH_INTR_A                    0x02000000
242 #define SICRH_INTR_B                    0x00C00000
243 #define SICRH_IIC                       0x00300000
244 #define SICRH_ETSEC2_B                  0x000C0000
245 #define SICRH_ETSEC2_C                  0x00030000
246 #define SICRH_ETSEC2_D                  0x0000C000
247 #define SICRH_ETSEC2_E                  0x00003000
248 #define SICRH_ETSEC2_F                  0x00000C00
249 #define SICRH_ETSEC2_G                  0x00000300
250 #define SICRH_ETSEC1_B                  0x00000080
251 #define SICRH_ETSEC1_C                  0x00000060
252 #define SICRH_GTX1_DLY                  0x00000008
253 #define SICRH_GTX2_DLY                  0x00000004
254 #define SICRH_TSOBI1                    0x00000002
255 #define SICRH_TSOBI2                    0x00000001
256
257 #elif defined(CONFIG_MPC8315)
258 /* SICRL bits - MPC8315 specific */
259 #define SICRL_DMA_CH0                   0xc0000000
260 #define SICRL_DMA_SPI                   0x30000000
261 #define SICRL_UART                      0x0c000000
262 #define SICRL_IRQ4                      0x02000000
263 #define SICRL_IRQ5                      0x01800000
264 #define SICRL_IRQ6_7                    0x00400000
265 #define SICRL_IIC1                      0x00300000
266 #define SICRL_TDM                       0x000c0000
267 #define SICRL_TDM_SHARED                0x00030000
268 #define SICRL_PCI_A                     0x0000c000
269 #define SICRL_ELBC_A                    0x00003000
270 #define SICRL_ETSEC1_A                  0x000000c0
271 #define SICRL_ETSEC1_B                  0x00000030
272 #define SICRL_ETSEC1_C                  0x0000000c
273 #define SICRL_TSEXPOBI                  0x00000001
274
275 /* SICRH bits - MPC8315 specific */
276 #define SICRH_GPIO_0                    0xc0000000
277 #define SICRH_GPIO_1                    0x30000000
278 #define SICRH_GPIO_2                    0x0c000000
279 #define SICRH_GPIO_3                    0x03000000
280 #define SICRH_GPIO_4                    0x00c00000
281 #define SICRH_GPIO_5                    0x00300000
282 #define SICRH_GPIO_6                    0x000c0000
283 #define SICRH_GPIO_7                    0x00030000
284 #define SICRH_GPIO_8                    0x0000c000
285 #define SICRH_GPIO_9                    0x00003000
286 #define SICRH_GPIO_10                   0x00000c00
287 #define SICRH_GPIO_11                   0x00000300
288 #define SICRH_ETSEC2_A                  0x000000c0
289 #define SICRH_TSOBI1                    0x00000002
290 #define SICRH_TSOBI2                    0x00000001
291
292 #elif defined(CONFIG_MPC837x)
293 /* SICRL bits - MPC837x specific */
294 #define SICRL_USB_A                     0xC0000000
295 #define SICRL_USB_B                     0x30000000
296 #define SICRL_USB_B_SD                  0x20000000
297 #define SICRL_UART                      0x0C000000
298 #define SICRL_GPIO_A                    0x02000000
299 #define SICRL_GPIO_B                    0x01000000
300 #define SICRL_GPIO_C                    0x00800000
301 #define SICRL_GPIO_D                    0x00400000
302 #define SICRL_GPIO_E                    0x00200000
303 #define SICRL_GPIO_F                    0x00180000
304 #define SICRL_GPIO_G                    0x00040000
305 #define SICRL_GPIO_H                    0x00020000
306 #define SICRL_GPIO_I                    0x00010000
307 #define SICRL_GPIO_J                    0x00008000
308 #define SICRL_GPIO_K                    0x00004000
309 #define SICRL_GPIO_L                    0x00003000
310 #define SICRL_DMA_A                     0x00000800
311 #define SICRL_DMA_B                     0x00000400
312 #define SICRL_DMA_C                     0x00000200
313 #define SICRL_DMA_D                     0x00000100
314 #define SICRL_DMA_E                     0x00000080
315 #define SICRL_DMA_F                     0x00000040
316 #define SICRL_DMA_G                     0x00000020
317 #define SICRL_DMA_H                     0x00000010
318 #define SICRL_DMA_I                     0x00000008
319 #define SICRL_DMA_J                     0x00000004
320 #define SICRL_LDP_A                     0x00000002
321 #define SICRL_LDP_B                     0x00000001
322
323 /* SICRH bits - MPC837x specific */
324 #define SICRH_DDR                       0x80000000
325 #define SICRH_TSEC1_A                   0x10000000
326 #define SICRH_TSEC1_B                   0x08000000
327 #define SICRH_TSEC2_A                   0x00400000
328 #define SICRH_TSEC2_B                   0x00200000
329 #define SICRH_TSEC2_C                   0x00100000
330 #define SICRH_TSEC2_D                   0x00080000
331 #define SICRH_TSEC2_E                   0x00040000
332 #define SICRH_TMR                       0x00010000
333 #define SICRH_GPIO2_A                   0x00008000
334 #define SICRH_GPIO2_B                   0x00004000
335 #define SICRH_GPIO2_C                   0x00002000
336 #define SICRH_GPIO2_D                   0x00001000
337 #define SICRH_GPIO2_E                   0x00000C00
338 #define SICRH_GPIO2_E_SD                0x00000800
339 #define SICRH_GPIO2_F                   0x00000300
340 #define SICRH_GPIO2_G                   0x000000C0
341 #define SICRH_GPIO2_H                   0x00000030
342 #define SICRH_SPI                       0x00000003
343 #define SICRH_SPI_SD                    0x00000001
344
345 #elif defined(CONFIG_MPC8308)
346 /* SICRL bits - MPC8308 specific */
347 #define SICRL_SPI_PF0                   (0 << 28)
348 #define SICRL_SPI_PF1                   (1 << 28)
349 #define SICRL_SPI_PF3                   (3 << 28)
350 #define SICRL_UART_PF0                  (0 << 26)
351 #define SICRL_UART_PF1                  (1 << 26)
352 #define SICRL_UART_PF3                  (3 << 26)
353 #define SICRL_IRQ_PF0                   (0 << 24)
354 #define SICRL_IRQ_PF1                   (1 << 24)
355 #define SICRL_I2C2_PF0                  (0 << 20)
356 #define SICRL_I2C2_PF1                  (1 << 20)
357 #define SICRL_ETSEC1_TX_CLK             (0 << 6)
358 #define SICRL_ETSEC1_GTX_CLK125         (1 << 6)
359
360 /* SICRH bits - MPC8308 specific */
361 #define SICRH_ESDHC_A_SD                (0 << 30)
362 #define SICRH_ESDHC_A_GTM               (1 << 30)
363 #define SICRH_ESDHC_A_GPIO              (3 << 30)
364 #define SICRH_ESDHC_B_SD                (0 << 28)
365 #define SICRH_ESDHC_B_GTM               (1 << 28)
366 #define SICRH_ESDHC_B_GPIO              (3 << 28)
367 #define SICRH_ESDHC_C_SD                (0 << 26)
368 #define SICRH_ESDHC_C_GTM               (1 << 26)
369 #define SICRH_ESDHC_C_GPIO              (3 << 26)
370 #define SICRH_GPIO_A_GPIO               (0 << 24)
371 #define SICRH_GPIO_A_TSEC2              (1 << 24)
372 #define SICRH_GPIO_B_GPIO               (0 << 22)
373 #define SICRH_GPIO_B_TSEC2_TX_CLK       (1 << 22)
374 #define SICRH_GPIO_B_TSEC2_GTX_CLK125   (2 << 22)
375 #define SICRH_IEEE1588_A_TMR            (1 << 20)
376 #define SICRH_IEEE1588_A_GPIO           (3 << 20)
377 #define SICRH_USB                       (1 << 18)
378 #define SICRH_GTM_GTM                   (1 << 16)
379 #define SICRH_GTM_GPIO                  (3 << 16)
380 #define SICRH_IEEE1588_B_TMR            (1 << 14)
381 #define SICRH_IEEE1588_B_GPIO           (3 << 14)
382 #define SICRH_ETSEC2_CRS                (1 << 12)
383 #define SICRH_ETSEC2_GPIO               (3 << 12)
384 #define SICRH_GPIOSEL_0                 (0 << 8)
385 #define SICRH_GPIOSEL_1                 (1 << 8)
386 #define SICRH_TMROBI_V3P3               (0 << 4)
387 #define SICRH_TMROBI_V2P5               (1 << 4)
388 #define SICRH_TSOBI1_V3P3               (0 << 1)
389 #define SICRH_TSOBI1_V2P5               (1 << 1)
390 #define SICRH_TSOBI2_V3P3               (0 << 0)
391 #define SICRH_TSOBI2_V2P5               (1 << 0)
392 #endif
393
394 /*
395  * SWCRR - System Watchdog Control Register
396  */
397 /* Register offset to immr */
398 #define SWCRR                           0x0204
399 /* Software Watchdog Time Count */
400 #define SWCRR_SWTC                      0xFFFF0000
401 /* Watchdog Enable bit */
402 #define SWCRR_SWEN                      0x00000004
403 /* Software Watchdog Reset/Interrupt Select bit */
404 #define SWCRR_SWRI                      0x00000002
405 /* Software Watchdog Counter Prescale bit */
406 #define SWCRR_SWPR                      0x00000001
407 #define SWCRR_RES                       (~(SWCRR_SWTC | SWCRR_SWEN | \
408                                                 SWCRR_SWRI | SWCRR_SWPR))
409
410 /*
411  * SWCNR - System Watchdog Counter Register
412  */
413 /* Register offset to immr */
414 #define SWCNR                           0x0208
415 /* Software Watchdog Count mask */
416 #define SWCNR_SWCN                      0x0000FFFF
417 #define SWCNR_RES                       ~(SWCNR_SWCN)
418
419 /*
420  * SWSRR - System Watchdog Service Register
421  */
422 /* Register offset to immr */
423 #define SWSRR                           0x020E
424
425 /*
426  * ACR - Arbiter Configuration Register
427  */
428 #define ACR_COREDIS                     0x10000000      /* Core disable */
429 #define ACR_COREDIS_SHIFT               (31-7)
430 #define ACR_PIPE_DEP                    0x00070000      /* Pipeline depth */
431 #define ACR_PIPE_DEP_SHIFT              (31-15)
432 #define ACR_PCI_RPTCNT                  0x00007000      /* PCI repeat count */
433 #define ACR_PCI_RPTCNT_SHIFT            (31-19)
434 #define ACR_RPTCNT                      0x00000700      /* Repeat count */
435 #define ACR_RPTCNT_SHIFT                (31-23)
436 #define ACR_APARK                       0x00000030      /* Address parking */
437 #define ACR_APARK_SHIFT                 (31-27)
438 #define ACR_PARKM                       0x0000000F      /* Parking master */
439 #define ACR_PARKM_SHIFT                 (31-31)
440
441 /*
442  * ATR - Arbiter Timers Register
443  */
444 #define ATR_DTO                         0x00FF0000      /* Data time out */
445 #define ATR_DTO_SHIFT                   16
446 #define ATR_ATO                         0x000000FF      /* Address time out */
447 #define ATR_ATO_SHIFT                   0
448
449 /*
450  * AER - Arbiter Event Register
451  */
452 #define AER_ETEA                        0x00000020      /* Transfer error */
453 /* Reserved transfer type */
454 #define AER_RES                         0x00000010
455 /* External control word transfer type */
456 #define AER_ECW                         0x00000008
457 /* Address Only transfer type */
458 #define AER_AO                          0x00000004
459 #define AER_DTO                         0x00000002      /* Data time out */
460 #define AER_ATO                         0x00000001      /* Address time out */
461
462 /*
463  * AEATR - Arbiter Event Address Register
464  */
465 #define AEATR_EVENT                     0x07000000      /* Event type */
466 #define AEATR_EVENT_SHIFT               24
467 #define AEATR_MSTR_ID                   0x001F0000      /* Master Id */
468 #define AEATR_MSTR_ID_SHIFT             16
469 #define AEATR_TBST                      0x00000800      /* Transfer burst */
470 #define AEATR_TBST_SHIFT                11
471 #define AEATR_TSIZE                     0x00000700      /* Transfer Size */
472 #define AEATR_TSIZE_SHIFT               8
473 #define AEATR_TTYPE                     0x0000001F      /* Transfer Type */
474 #define AEATR_TTYPE_SHIFT               0
475
476 /*
477  * HRCWL - Hard Reset Configuration Word Low
478  */
479 #define HRCWL_LBIUCM                    0x80000000
480 #define HRCWL_LBIUCM_SHIFT              31
481 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1    0x00000000
482 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1    0x80000000
483
484 #define HRCWL_DDRCM                     0x40000000
485 #define HRCWL_DDRCM_SHIFT               30
486 #define HRCWL_DDR_TO_SCB_CLK_1X1        0x00000000
487 #define HRCWL_DDR_TO_SCB_CLK_2X1        0x40000000
488
489 #define HRCWL_SPMF                      0x0f000000
490 #define HRCWL_SPMF_SHIFT                24
491 #define HRCWL_CSB_TO_CLKIN_16X1         0x00000000
492 #define HRCWL_CSB_TO_CLKIN_1X1          0x01000000
493 #define HRCWL_CSB_TO_CLKIN_2X1          0x02000000
494 #define HRCWL_CSB_TO_CLKIN_3X1          0x03000000
495 #define HRCWL_CSB_TO_CLKIN_4X1          0x04000000
496 #define HRCWL_CSB_TO_CLKIN_5X1          0x05000000
497 #define HRCWL_CSB_TO_CLKIN_6X1          0x06000000
498 #define HRCWL_CSB_TO_CLKIN_7X1          0x07000000
499 #define HRCWL_CSB_TO_CLKIN_8X1          0x08000000
500 #define HRCWL_CSB_TO_CLKIN_9X1          0x09000000
501 #define HRCWL_CSB_TO_CLKIN_10X1         0x0A000000
502 #define HRCWL_CSB_TO_CLKIN_11X1         0x0B000000
503 #define HRCWL_CSB_TO_CLKIN_12X1         0x0C000000
504 #define HRCWL_CSB_TO_CLKIN_13X1         0x0D000000
505 #define HRCWL_CSB_TO_CLKIN_14X1         0x0E000000
506 #define HRCWL_CSB_TO_CLKIN_15X1         0x0F000000
507
508 #define HRCWL_VCO_BYPASS                0x00000000
509 #define HRCWL_VCO_1X2                   0x00000000
510 #define HRCWL_VCO_1X4                   0x00200000
511 #define HRCWL_VCO_1X8                   0x00400000
512
513 #define HRCWL_COREPLL                   0x007F0000
514 #define HRCWL_COREPLL_SHIFT             16
515 #define HRCWL_CORE_TO_CSB_BYPASS        0x00000000
516 #define HRCWL_CORE_TO_CSB_1X1           0x00020000
517 #define HRCWL_CORE_TO_CSB_1_5X1         0x00030000
518 #define HRCWL_CORE_TO_CSB_2X1           0x00040000
519 #define HRCWL_CORE_TO_CSB_2_5X1         0x00050000
520 #define HRCWL_CORE_TO_CSB_3X1           0x00060000
521
522 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
523 #define HRCWL_CEVCOD                    0x000000C0
524 #define HRCWL_CEVCOD_SHIFT              6
525 #define HRCWL_CE_PLL_VCO_DIV_4          0x00000000
526 #define HRCWL_CE_PLL_VCO_DIV_8          0x00000040
527 #define HRCWL_CE_PLL_VCO_DIV_2          0x00000080
528
529 #define HRCWL_CEPDF                     0x00000020
530 #define HRCWL_CEPDF_SHIFT               5
531 #define HRCWL_CE_PLL_DIV_1X1            0x00000000
532 #define HRCWL_CE_PLL_DIV_2X1            0x00000020
533
534 #define HRCWL_CEPMF                     0x0000001F
535 #define HRCWL_CEPMF_SHIFT               0
536 #define HRCWL_CE_TO_PLL_1X16_           0x00000000
537 #define HRCWL_CE_TO_PLL_1X2             0x00000002
538 #define HRCWL_CE_TO_PLL_1X3             0x00000003
539 #define HRCWL_CE_TO_PLL_1X4             0x00000004
540 #define HRCWL_CE_TO_PLL_1X5             0x00000005
541 #define HRCWL_CE_TO_PLL_1X6             0x00000006
542 #define HRCWL_CE_TO_PLL_1X7             0x00000007
543 #define HRCWL_CE_TO_PLL_1X8             0x00000008
544 #define HRCWL_CE_TO_PLL_1X9             0x00000009
545 #define HRCWL_CE_TO_PLL_1X10            0x0000000A
546 #define HRCWL_CE_TO_PLL_1X11            0x0000000B
547 #define HRCWL_CE_TO_PLL_1X12            0x0000000C
548 #define HRCWL_CE_TO_PLL_1X13            0x0000000D
549 #define HRCWL_CE_TO_PLL_1X14            0x0000000E
550 #define HRCWL_CE_TO_PLL_1X15            0x0000000F
551 #define HRCWL_CE_TO_PLL_1X16            0x00000010
552 #define HRCWL_CE_TO_PLL_1X17            0x00000011
553 #define HRCWL_CE_TO_PLL_1X18            0x00000012
554 #define HRCWL_CE_TO_PLL_1X19            0x00000013
555 #define HRCWL_CE_TO_PLL_1X20            0x00000014
556 #define HRCWL_CE_TO_PLL_1X21            0x00000015
557 #define HRCWL_CE_TO_PLL_1X22            0x00000016
558 #define HRCWL_CE_TO_PLL_1X23            0x00000017
559 #define HRCWL_CE_TO_PLL_1X24            0x00000018
560 #define HRCWL_CE_TO_PLL_1X25            0x00000019
561 #define HRCWL_CE_TO_PLL_1X26            0x0000001A
562 #define HRCWL_CE_TO_PLL_1X27            0x0000001B
563 #define HRCWL_CE_TO_PLL_1X28            0x0000001C
564 #define HRCWL_CE_TO_PLL_1X29            0x0000001D
565 #define HRCWL_CE_TO_PLL_1X30            0x0000001E
566 #define HRCWL_CE_TO_PLL_1X31            0x0000001F
567
568 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
569 #define HRCWL_SVCOD                     0x30000000
570 #define HRCWL_SVCOD_SHIFT               28
571 #define HRCWL_SVCOD_DIV_2               0x00000000
572 #define HRCWL_SVCOD_DIV_4               0x10000000
573 #define HRCWL_SVCOD_DIV_8               0x20000000
574 #define HRCWL_SVCOD_DIV_1               0x30000000
575
576 #elif defined(CONFIG_MPC837x)
577 #define HRCWL_SVCOD                     0x30000000
578 #define HRCWL_SVCOD_SHIFT               28
579 #define HRCWL_SVCOD_DIV_4               0x00000000
580 #define HRCWL_SVCOD_DIV_8               0x10000000
581 #define HRCWL_SVCOD_DIV_2               0x20000000
582 #define HRCWL_SVCOD_DIV_1               0x30000000
583 #endif
584
585 /*
586  * HRCWH - Hardware Reset Configuration Word High
587  */
588 #define HRCWH_PCI_HOST                  0x80000000
589 #define HRCWH_PCI_HOST_SHIFT            31
590 #define HRCWH_PCI_AGENT                 0x00000000
591
592 #if defined(CONFIG_MPC834x)
593 #define HRCWH_32_BIT_PCI                0x00000000
594 #define HRCWH_64_BIT_PCI                0x40000000
595 #endif
596
597 #define HRCWH_PCI1_ARBITER_DISABLE      0x00000000
598 #define HRCWH_PCI1_ARBITER_ENABLE       0x20000000
599
600 #define HRCWH_PCI_ARBITER_DISABLE       0x00000000
601 #define HRCWH_PCI_ARBITER_ENABLE        0x20000000
602
603 #if defined(CONFIG_MPC834x)
604 #define HRCWH_PCI2_ARBITER_DISABLE      0x00000000
605 #define HRCWH_PCI2_ARBITER_ENABLE       0x10000000
606
607 #elif defined(CONFIG_MPC8360)
608 #define HRCWH_PCICKDRV_DISABLE          0x00000000
609 #define HRCWH_PCICKDRV_ENABLE           0x10000000
610 #endif
611
612 #define HRCWH_CORE_DISABLE              0x08000000
613 #define HRCWH_CORE_ENABLE               0x00000000
614
615 #define HRCWH_FROM_0X00000100           0x00000000
616 #define HRCWH_FROM_0XFFF00100           0x04000000
617
618 #define HRCWH_BOOTSEQ_DISABLE           0x00000000
619 #define HRCWH_BOOTSEQ_NORMAL            0x01000000
620 #define HRCWH_BOOTSEQ_EXTENDED          0x02000000
621
622 #define HRCWH_SW_WATCHDOG_DISABLE       0x00000000
623 #define HRCWH_SW_WATCHDOG_ENABLE        0x00800000
624
625 #define HRCWH_ROM_LOC_DDR_SDRAM         0x00000000
626 #define HRCWH_ROM_LOC_PCI1              0x00100000
627 #if defined(CONFIG_MPC834x)
628 #define HRCWH_ROM_LOC_PCI2              0x00200000
629 #endif
630 #if defined(CONFIG_MPC837x)
631 #define HRCWH_ROM_LOC_ON_CHIP_ROM       0x00300000
632 #endif
633 #define HRCWH_ROM_LOC_LOCAL_8BIT        0x00500000
634 #define HRCWH_ROM_LOC_LOCAL_16BIT       0x00600000
635 #define HRCWH_ROM_LOC_LOCAL_32BIT       0x00700000
636
637 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
638         defined(CONFIG_MPC837x)
639 #define HRCWH_ROM_LOC_NAND_SP_8BIT      0x00100000
640 #define HRCWH_ROM_LOC_NAND_SP_16BIT     0x00200000
641 #define HRCWH_ROM_LOC_NAND_LP_8BIT      0x00500000
642 #define HRCWH_ROM_LOC_NAND_LP_16BIT     0x00600000
643
644 #define HRCWH_RL_EXT_LEGACY             0x00000000
645 #define HRCWH_RL_EXT_NAND               0x00040000
646
647 #define HRCWH_TSEC1M_MASK               0x0000E000
648 #define HRCWH_TSEC1M_IN_MII             0x00000000
649 #define HRCWH_TSEC1M_IN_RMII            0x00002000
650 #define HRCWH_TSEC1M_IN_RGMII           0x00006000
651 #define HRCWH_TSEC1M_IN_RTBI            0x0000A000
652 #define HRCWH_TSEC1M_IN_SGMII           0x0000C000
653
654 #define HRCWH_TSEC2M_MASK               0x00001C00
655 #define HRCWH_TSEC2M_IN_MII             0x00000000
656 #define HRCWH_TSEC2M_IN_RMII            0x00000400
657 #define HRCWH_TSEC2M_IN_RGMII           0x00000C00
658 #define HRCWH_TSEC2M_IN_RTBI            0x00001400
659 #define HRCWH_TSEC2M_IN_SGMII           0x00001800
660 #endif
661
662 #if defined(CONFIG_MPC834x)
663 #define HRCWH_TSEC1M_IN_RGMII           0x00000000
664 #define HRCWH_TSEC1M_IN_RTBI            0x00004000
665 #define HRCWH_TSEC1M_IN_GMII            0x00008000
666 #define HRCWH_TSEC1M_IN_TBI             0x0000C000
667 #define HRCWH_TSEC2M_IN_RGMII           0x00000000
668 #define HRCWH_TSEC2M_IN_RTBI            0x00001000
669 #define HRCWH_TSEC2M_IN_GMII            0x00002000
670 #define HRCWH_TSEC2M_IN_TBI             0x00003000
671 #endif
672
673 #if defined(CONFIG_MPC8360)
674 #define HRCWH_SECONDARY_DDR_DISABLE     0x00000000
675 #define HRCWH_SECONDARY_DDR_ENABLE      0x00000010
676 #endif
677
678 #define HRCWH_BIG_ENDIAN                0x00000000
679 #define HRCWH_LITTLE_ENDIAN             0x00000008
680
681 #define HRCWH_LALE_NORMAL               0x00000000
682 #define HRCWH_LALE_EARLY                0x00000004
683
684 #define HRCWH_LDP_SET                   0x00000000
685 #define HRCWH_LDP_CLEAR                 0x00000002
686
687 /*
688  * RSR - Reset Status Register
689  */
690 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
691         defined(CONFIG_MPC837x)
692 #define RSR_RSTSRC                      0xF0000000      /* Reset source */
693 #define RSR_RSTSRC_SHIFT                28
694 #else
695 #define RSR_RSTSRC                      0xE0000000      /* Reset source */
696 #define RSR_RSTSRC_SHIFT                29
697 #endif
698 #define RSR_BSF                         0x00010000      /* Boot seq. fail */
699 #define RSR_BSF_SHIFT                   16
700 /* software soft reset */
701 #define RSR_SWSR                        0x00002000
702 #define RSR_SWSR_SHIFT                  13
703 /* software hard reset */
704 #define RSR_SWHR                        0x00001000
705 #define RSR_SWHR_SHIFT                  12
706 #define RSR_JHRS                        0x00000200      /* jtag hreset */
707 #define RSR_JHRS_SHIFT                  9
708 /* jtag sreset status */
709 #define RSR_JSRS                        0x00000100
710 #define RSR_JSRS_SHIFT                  8
711 /* checkstop reset status */
712 #define RSR_CSHR                        0x00000010
713 #define RSR_CSHR_SHIFT                  4
714 /* software watchdog reset status */
715 #define RSR_SWRS                        0x00000008
716 #define RSR_SWRS_SHIFT                  3
717 /* bus monitop reset status */
718 #define RSR_BMRS                        0x00000004
719 #define RSR_BMRS_SHIFT                  2
720 #define RSR_SRS                         0x00000002      /* soft reset status */
721 #define RSR_SRS_SHIFT                   1
722 #define RSR_HRS                         0x00000001      /* hard reset status */
723 #define RSR_HRS_SHIFT                   0
724 #define RSR_RES                         (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
725                                                 RSR_SWHR | RSR_JHRS | \
726                                                 RSR_JSRS | RSR_CSHR | \
727                                                 RSR_SWRS | RSR_BMRS | \
728                                                 RSR_SRS | RSR_HRS))
729 /*
730  * RMR - Reset Mode Register
731  */
732 /* checkstop reset enable */
733 #define RMR_CSRE                        0x00000001
734 #define RMR_CSRE_SHIFT                  0
735 #define RMR_RES                         ~(RMR_CSRE)
736
737 /*
738  * RCR - Reset Control Register
739  */
740 /* software hard reset */
741 #define RCR_SWHR                        0x00000002
742 /* software soft reset */
743 #define RCR_SWSR                        0x00000001
744 #define RCR_RES                         ~(RCR_SWHR | RCR_SWSR)
745
746 /*
747  * RCER - Reset Control Enable Register
748  */
749 /* software hard reset */
750 #define RCER_CRE                        0x00000001
751 #define RCER_RES                        ~(RCER_CRE)
752
753 /*
754  * SPMR - System PLL Mode Register
755  */
756 #define SPMR_LBIUCM                     0x80000000
757 #define SPMR_LBIUCM_SHIFT               31
758 #define SPMR_DDRCM                      0x40000000
759 #define SPMR_DDRCM_SHIFT                30
760 #define SPMR_SPMF                       0x0F000000
761 #define SPMR_SPMF_SHIFT         24
762 #define SPMR_CKID                       0x00800000
763 #define SPMR_CKID_SHIFT                 23
764 #define SPMR_COREPLL                    0x007F0000
765 #define SPMR_COREPLL_SHIFT              16
766 #define SPMR_CEVCOD                     0x000000C0
767 #define SPMR_CEVCOD_SHIFT               6
768 #define SPMR_CEPDF                      0x00000020
769 #define SPMR_CEPDF_SHIFT                5
770 #define SPMR_CEPMF                      0x0000001F
771 #define SPMR_CEPMF_SHIFT                0
772
773 /*
774  * OCCR - Output Clock Control Register
775  */
776 #define OCCR_PCICOE0                    0x80000000
777 #define OCCR_PCICOE1                    0x40000000
778 #define OCCR_PCICOE2                    0x20000000
779 #define OCCR_PCICOE3                    0x10000000
780 #define OCCR_PCICOE4                    0x08000000
781 #define OCCR_PCICOE5                    0x04000000
782 #define OCCR_PCICOE6                    0x02000000
783 #define OCCR_PCICOE7                    0x01000000
784 #define OCCR_PCICD0                     0x00800000
785 #define OCCR_PCICD1                     0x00400000
786 #define OCCR_PCICD2                     0x00200000
787 #define OCCR_PCICD3                     0x00100000
788 #define OCCR_PCICD4                     0x00080000
789 #define OCCR_PCICD5                     0x00040000
790 #define OCCR_PCICD6                     0x00020000
791 #define OCCR_PCICD7                     0x00010000
792 #define OCCR_PCI1CR                     0x00000002
793 #define OCCR_PCI2CR                     0x00000001
794 #define OCCR_PCICR                      OCCR_PCI1CR
795
796 /*
797  * SCCR - System Clock Control Register
798  */
799 #define SCCR_ENCCM                      0x03000000
800 #define SCCR_ENCCM_SHIFT                24
801 #define SCCR_ENCCM_0                    0x00000000
802 #define SCCR_ENCCM_1                    0x01000000
803 #define SCCR_ENCCM_2                    0x02000000
804 #define SCCR_ENCCM_3                    0x03000000
805
806 #define SCCR_PCICM                      0x00010000
807 #define SCCR_PCICM_SHIFT                16
808
809 #if defined(CONFIG_MPC834x)
810 /* SCCR bits - MPC834x specific */
811 #define SCCR_TSEC1CM                    0xc0000000
812 #define SCCR_TSEC1CM_SHIFT              30
813 #define SCCR_TSEC1CM_0                  0x00000000
814 #define SCCR_TSEC1CM_1                  0x40000000
815 #define SCCR_TSEC1CM_2                  0x80000000
816 #define SCCR_TSEC1CM_3                  0xC0000000
817
818 #define SCCR_TSEC2CM                    0x30000000
819 #define SCCR_TSEC2CM_SHIFT              28
820 #define SCCR_TSEC2CM_0                  0x00000000
821 #define SCCR_TSEC2CM_1                  0x10000000
822 #define SCCR_TSEC2CM_2                  0x20000000
823 #define SCCR_TSEC2CM_3                  0x30000000
824
825 /* The MPH must have the same clock ratio as DR, unless its clock disabled */
826 #define SCCR_USBMPHCM                   0x00c00000
827 #define SCCR_USBMPHCM_SHIFT             22
828 #define SCCR_USBDRCM                    0x00300000
829 #define SCCR_USBDRCM_SHIFT              20
830 #define SCCR_USBCM                      0x00f00000
831 #define SCCR_USBCM_SHIFT                20
832 #define SCCR_USBCM_0                    0x00000000
833 #define SCCR_USBCM_1                    0x00500000
834 #define SCCR_USBCM_2                    0x00A00000
835 #define SCCR_USBCM_3                    0x00F00000
836
837 #elif defined(CONFIG_MPC8313)
838 /* TSEC1 bits are for TSEC2 as well */
839 #define SCCR_TSEC1CM                    0xc0000000
840 #define SCCR_TSEC1CM_SHIFT              30
841 #define SCCR_TSEC1CM_0                  0x00000000
842 #define SCCR_TSEC1CM_1                  0x40000000
843 #define SCCR_TSEC1CM_2                  0x80000000
844 #define SCCR_TSEC1CM_3                  0xC0000000
845
846 #define SCCR_TSEC1ON                    0x20000000
847 #define SCCR_TSEC1ON_SHIFT              29
848 #define SCCR_TSEC2ON                    0x10000000
849 #define SCCR_TSEC2ON_SHIFT              28
850
851 #define SCCR_USBDRCM                    0x00300000
852 #define SCCR_USBDRCM_SHIFT              20
853 #define SCCR_USBDRCM_0                  0x00000000
854 #define SCCR_USBDRCM_1                  0x00100000
855 #define SCCR_USBDRCM_2                  0x00200000
856 #define SCCR_USBDRCM_3                  0x00300000
857
858 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
859 /* SCCR bits - MPC8315/MPC8308 specific */
860 #define SCCR_TSEC1CM                    0xc0000000
861 #define SCCR_TSEC1CM_SHIFT              30
862 #define SCCR_TSEC1CM_0                  0x00000000
863 #define SCCR_TSEC1CM_1                  0x40000000
864 #define SCCR_TSEC1CM_2                  0x80000000
865 #define SCCR_TSEC1CM_3                  0xC0000000
866
867 #define SCCR_TSEC2CM                    0x30000000
868 #define SCCR_TSEC2CM_SHIFT              28
869 #define SCCR_TSEC2CM_0                  0x00000000
870 #define SCCR_TSEC2CM_1                  0x10000000
871 #define SCCR_TSEC2CM_2                  0x20000000
872 #define SCCR_TSEC2CM_3                  0x30000000
873
874 #define SCCR_SDHCCM                     0x0c000000
875 #define SCCR_SDHCCM_SHIFT               26
876 #define SCCR_SDHCCM_0                   0x00000000
877 #define SCCR_SDHCCM_1                   0x04000000
878 #define SCCR_SDHCCM_2                   0x08000000
879 #define SCCR_SDHCCM_3                   0x0c000000
880
881 #define SCCR_USBDRCM                    0x00c00000
882 #define SCCR_USBDRCM_SHIFT              22
883 #define SCCR_USBDRCM_0                  0x00000000
884 #define SCCR_USBDRCM_1                  0x00400000
885 #define SCCR_USBDRCM_2                  0x00800000
886 #define SCCR_USBDRCM_3                  0x00c00000
887
888 #define SCCR_SATA1CM                    0x00003000
889 #define SCCR_SATA1CM_SHIFT              12
890 #define SCCR_SATACM                     0x00003c00
891 #define SCCR_SATACM_SHIFT               10
892 #define SCCR_SATACM_0                   0x00000000
893 #define SCCR_SATACM_1                   0x00001400
894 #define SCCR_SATACM_2                   0x00002800
895 #define SCCR_SATACM_3                   0x00003c00
896
897 #define SCCR_TDMCM                      0x00000030
898 #define SCCR_TDMCM_SHIFT                4
899 #define SCCR_TDMCM_0                    0x00000000
900 #define SCCR_TDMCM_1                    0x00000010
901 #define SCCR_TDMCM_2                    0x00000020
902 #define SCCR_TDMCM_3                    0x00000030
903
904 #elif defined(CONFIG_MPC837x)
905 /* SCCR bits - MPC837x specific */
906 #define SCCR_TSEC1CM                    0xc0000000
907 #define SCCR_TSEC1CM_SHIFT              30
908 #define SCCR_TSEC1CM_0                  0x00000000
909 #define SCCR_TSEC1CM_1                  0x40000000
910 #define SCCR_TSEC1CM_2                  0x80000000
911 #define SCCR_TSEC1CM_3                  0xC0000000
912
913 #define SCCR_TSEC2CM                    0x30000000
914 #define SCCR_TSEC2CM_SHIFT              28
915 #define SCCR_TSEC2CM_0                  0x00000000
916 #define SCCR_TSEC2CM_1                  0x10000000
917 #define SCCR_TSEC2CM_2                  0x20000000
918 #define SCCR_TSEC2CM_3                  0x30000000
919
920 #define SCCR_SDHCCM                     0x0c000000
921 #define SCCR_SDHCCM_SHIFT               26
922 #define SCCR_SDHCCM_0                   0x00000000
923 #define SCCR_SDHCCM_1                   0x04000000
924 #define SCCR_SDHCCM_2                   0x08000000
925 #define SCCR_SDHCCM_3                   0x0c000000
926
927 #define SCCR_USBDRCM                    0x00c00000
928 #define SCCR_USBDRCM_SHIFT              22
929 #define SCCR_USBDRCM_0                  0x00000000
930 #define SCCR_USBDRCM_1                  0x00400000
931 #define SCCR_USBDRCM_2                  0x00800000
932 #define SCCR_USBDRCM_3                  0x00c00000
933
934 /* All of the four SATA controllers must have the same clock ratio */
935 #define SCCR_SATA1CM                    0x000000c0
936 #define SCCR_SATA1CM_SHIFT              6
937 #define SCCR_SATACM                     0x000000ff
938 #define SCCR_SATACM_SHIFT               0
939 #define SCCR_SATACM_0                   0x00000000
940 #define SCCR_SATACM_1                   0x00000055
941 #define SCCR_SATACM_2                   0x000000aa
942 #define SCCR_SATACM_3                   0x000000ff
943 #endif
944
945 #define SCCR_PCIEXP1CM                  0x00300000
946 #define SCCR_PCIEXP1CM_SHIFT            20
947 #define SCCR_PCIEXP1CM_0                0x00000000
948 #define SCCR_PCIEXP1CM_1                0x00100000
949 #define SCCR_PCIEXP1CM_2                0x00200000
950 #define SCCR_PCIEXP1CM_3                0x00300000
951
952 #define SCCR_PCIEXP2CM                  0x000c0000
953 #define SCCR_PCIEXP2CM_SHIFT            18
954 #define SCCR_PCIEXP2CM_0                0x00000000
955 #define SCCR_PCIEXP2CM_1                0x00040000
956 #define SCCR_PCIEXP2CM_2                0x00080000
957 #define SCCR_PCIEXP2CM_3                0x000c0000
958
959 /*
960  * CSn_BDNS - Chip Select memory Bounds Register
961  */
962 #define CSBNDS_SA                       0x00FF0000
963 #define CSBNDS_SA_SHIFT                 8
964 #define CSBNDS_EA                       0x000000FF
965 #define CSBNDS_EA_SHIFT                 24
966
967 /*
968  * CSn_CONFIG - Chip Select Configuration Register
969  */
970 #define CSCONFIG_EN                     0x80000000
971 #define CSCONFIG_AP                     0x00800000
972 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
973 #define CSCONFIG_ODT_RD_NEVER           0x00000000
974 #define CSCONFIG_ODT_RD_ONLY_CURRENT    0x00100000
975 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS   0x00200000
976 #define CSCONFIG_ODT_RD_ALL             0x00400000
977 #define CSCONFIG_ODT_WR_NEVER           0x00000000
978 #define CSCONFIG_ODT_WR_ONLY_CURRENT    0x00010000
979 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS   0x00020000
980 #define CSCONFIG_ODT_WR_ALL             0x00040000
981 #elif defined(CONFIG_MPC832x)
982 #define CSCONFIG_ODT_RD_CFG             0x00400000
983 #define CSCONFIG_ODT_WR_CFG             0x00040000
984 #elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
985 #define CSCONFIG_ODT_RD_NEVER           0x00000000
986 #define CSCONFIG_ODT_RD_ONLY_CURRENT    0x00100000
987 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS   0x00200000
988 #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
989 #define CSCONFIG_ODT_RD_ALL             0x00400000
990 #define CSCONFIG_ODT_WR_NEVER           0x00000000
991 #define CSCONFIG_ODT_WR_ONLY_CURRENT    0x00010000
992 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS   0x00020000
993 #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
994 #define CSCONFIG_ODT_WR_ALL             0x00040000
995 #endif
996 #define CSCONFIG_BANK_BIT_3             0x00004000
997 #define CSCONFIG_ROW_BIT                0x00000700
998 #define CSCONFIG_ROW_BIT_12             0x00000000
999 #define CSCONFIG_ROW_BIT_13             0x00000100
1000 #define CSCONFIG_ROW_BIT_14             0x00000200
1001 #define CSCONFIG_COL_BIT                0x00000007
1002 #define CSCONFIG_COL_BIT_8              0x00000000
1003 #define CSCONFIG_COL_BIT_9              0x00000001
1004 #define CSCONFIG_COL_BIT_10             0x00000002
1005 #define CSCONFIG_COL_BIT_11             0x00000003
1006
1007 /*
1008  * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
1009  */
1010 #define TIMING_CFG0_RWT                 0xC0000000
1011 #define TIMING_CFG0_RWT_SHIFT           30
1012 #define TIMING_CFG0_WRT                 0x30000000
1013 #define TIMING_CFG0_WRT_SHIFT           28
1014 #define TIMING_CFG0_RRT                 0x0C000000
1015 #define TIMING_CFG0_RRT_SHIFT           26
1016 #define TIMING_CFG0_WWT                 0x03000000
1017 #define TIMING_CFG0_WWT_SHIFT           24
1018 #define TIMING_CFG0_ACT_PD_EXIT         0x00700000
1019 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT   20
1020 #define TIMING_CFG0_PRE_PD_EXIT         0x00070000
1021 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT   16
1022 #define TIMING_CFG0_ODT_PD_EXIT         0x00000F00
1023 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT   8
1024 #define TIMING_CFG0_MRS_CYC             0x0000000F
1025 #define TIMING_CFG0_MRS_CYC_SHIFT       0
1026
1027 /*
1028  * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
1029  */
1030 #define TIMING_CFG1_PRETOACT            0x70000000
1031 #define TIMING_CFG1_PRETOACT_SHIFT      28
1032 #define TIMING_CFG1_ACTTOPRE            0x0F000000
1033 #define TIMING_CFG1_ACTTOPRE_SHIFT      24
1034 #define TIMING_CFG1_ACTTORW             0x00700000
1035 #define TIMING_CFG1_ACTTORW_SHIFT       20
1036 #define TIMING_CFG1_CASLAT              0x00070000
1037 #define TIMING_CFG1_CASLAT_SHIFT        16
1038 #define TIMING_CFG1_REFREC              0x0000F000
1039 #define TIMING_CFG1_REFREC_SHIFT        12
1040 #define TIMING_CFG1_WRREC               0x00000700
1041 #define TIMING_CFG1_WRREC_SHIFT         8
1042 #define TIMING_CFG1_ACTTOACT            0x00000070
1043 #define TIMING_CFG1_ACTTOACT_SHIFT      4
1044 #define TIMING_CFG1_WRTORD              0x00000007
1045 #define TIMING_CFG1_WRTORD_SHIFT        0
1046 #define TIMING_CFG1_CASLAT_20           0x00030000      /* CAS latency = 2.0 */
1047 #define TIMING_CFG1_CASLAT_25           0x00040000      /* CAS latency = 2.5 */
1048 #define TIMING_CFG1_CASLAT_30           0x00050000      /* CAS latency = 3.0 */
1049 #define TIMING_CFG1_CASLAT_35           0x00060000      /* CAS latency = 3.5 */
1050 #define TIMING_CFG1_CASLAT_40           0x00070000      /* CAS latency = 4.0 */
1051 #define TIMING_CFG1_CASLAT_45           0x00080000      /* CAS latency = 4.5 */
1052 #define TIMING_CFG1_CASLAT_50           0x00090000      /* CAS latency = 5.0 */
1053
1054 /*
1055  * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
1056  */
1057 #define TIMING_CFG2_CPO                 0x0F800000
1058 #define TIMING_CFG2_CPO_SHIFT           23
1059 #define TIMING_CFG2_ACSM                0x00080000
1060 #define TIMING_CFG2_WR_DATA_DELAY       0x00001C00
1061 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
1062 /* default (= CASLAT + 1) */
1063 #define TIMING_CFG2_CPO_DEF             0x00000000
1064
1065 #define TIMING_CFG2_ADD_LAT             0x70000000
1066 #define TIMING_CFG2_ADD_LAT_SHIFT       28
1067 #define TIMING_CFG2_WR_LAT_DELAY        0x00380000
1068 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT  19
1069 #define TIMING_CFG2_RD_TO_PRE           0x0000E000
1070 #define TIMING_CFG2_RD_TO_PRE_SHIFT     13
1071 #define TIMING_CFG2_CKE_PLS             0x000001C0
1072 #define TIMING_CFG2_CKE_PLS_SHIFT       6
1073 #define TIMING_CFG2_FOUR_ACT            0x0000003F
1074 #define TIMING_CFG2_FOUR_ACT_SHIFT      0
1075
1076 /*
1077  * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
1078  */
1079 #define TIMING_CFG3_EXT_REFREC          0x00070000
1080 #define TIMING_CFG3_EXT_REFREC_SHIFT    16
1081
1082 /*
1083  * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
1084  */
1085 #define SDRAM_CFG_MEM_EN                0x80000000
1086 #define SDRAM_CFG_SREN                  0x40000000
1087 #define SDRAM_CFG_ECC_EN                0x20000000
1088 #define SDRAM_CFG_RD_EN                 0x10000000
1089 #define SDRAM_CFG_SDRAM_TYPE_DDR1       0x02000000
1090 #define SDRAM_CFG_SDRAM_TYPE_DDR2       0x03000000
1091 #define SDRAM_CFG_SDRAM_TYPE_MASK       0x07000000
1092 #define SDRAM_CFG_SDRAM_TYPE_SHIFT      24
1093 #define SDRAM_CFG_DYN_PWR               0x00200000
1094 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
1095 #define SDRAM_CFG_DBW_MASK              0x00180000
1096 #define SDRAM_CFG_DBW_16                0x00100000
1097 #define SDRAM_CFG_DBW_32                0x00080000
1098 #else
1099 #define SDRAM_CFG_32_BE                 0x00080000
1100 #endif
1101 #if !defined(CONFIG_MPC8308)
1102 #define SDRAM_CFG_8_BE                  0x00040000
1103 #endif
1104 #define SDRAM_CFG_NCAP                  0x00020000
1105 #define SDRAM_CFG_2T_EN                 0x00008000
1106 #define SDRAM_CFG_HSE                   0x00000008
1107 #define SDRAM_CFG_BI                    0x00000001
1108
1109 /*
1110  * DDR_SDRAM_MODE - DDR SDRAM Mode Register
1111  */
1112 #define SDRAM_MODE_ESD                  0xFFFF0000
1113 #define SDRAM_MODE_ESD_SHIFT            16
1114 #define SDRAM_MODE_SD                   0x0000FFFF
1115 #define SDRAM_MODE_SD_SHIFT             0
1116 /* select extended mode reg */
1117 #define DDR_MODE_EXT_MODEREG            0x4000
1118 /* operating mode, mask */
1119 #define DDR_MODE_EXT_OPMODE             0x3FF8
1120 #define DDR_MODE_EXT_OP_NORMAL          0x0000          /* normal operation */
1121 /* QFC / compatibility, mask */
1122 #define DDR_MODE_QFC                    0x0004
1123 /* compatible to older SDRAMs */
1124 #define DDR_MODE_QFC_COMP               0x0000
1125 /* weak drivers */
1126 #define DDR_MODE_WEAK                   0x0002
1127 /* disable DLL */
1128 #define DDR_MODE_DLL_DIS                0x0001
1129 /* CAS latency, mask */
1130 #define DDR_MODE_CASLAT                 0x0070
1131 #define DDR_MODE_CASLAT_15              0x0010          /* CAS latency 1.5 */
1132 #define DDR_MODE_CASLAT_20              0x0020          /* CAS latency 2 */
1133 #define DDR_MODE_CASLAT_25              0x0060          /* CAS latency 2.5 */
1134 #define DDR_MODE_CASLAT_30              0x0030          /* CAS latency 3 */
1135 /* sequential burst */
1136 #define DDR_MODE_BTYPE_SEQ              0x0000
1137 /* interleaved burst */
1138 #define DDR_MODE_BTYPE_ILVD             0x0008
1139 #define DDR_MODE_BLEN_2                 0x0001          /* burst length 2 */
1140 #define DDR_MODE_BLEN_4                 0x0002          /* burst length 4 */
1141 /* exact value for 7.8125us */
1142 #define DDR_REFINT_166MHZ_7US           1302
1143 /* use 256 cycles as a starting point */
1144 #define DDR_BSTOPRE                     256
1145 /* select mode register */
1146 #define DDR_MODE_MODEREG                0x0000
1147
1148 /*
1149  * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
1150  */
1151 #define SDRAM_INTERVAL_REFINT           0x3FFF0000
1152 #define SDRAM_INTERVAL_REFINT_SHIFT     16
1153 #define SDRAM_INTERVAL_BSTOPRE          0x00003FFF
1154 #define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
1155
1156 /*
1157  * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
1158  */
1159 #define DDR_SDRAM_CLK_CNTL_SS_EN                0x80000000
1160 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025       0x01000000
1161 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05        0x02000000
1162 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075       0x03000000
1163 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1         0x04000000
1164
1165 /*
1166  * ECC_ERR_INJECT - Memory data path error injection mask ECC
1167  */
1168 /* ECC Mirror Byte */
1169 #define ECC_ERR_INJECT_EMB              (0x80000000 >> 22)
1170 /* Error Injection Enable */
1171 #define ECC_ERR_INJECT_EIEN             (0x80000000 >> 23)
1172 /* ECC Erroe Injection Enable */
1173 #define ECC_ERR_INJECT_EEIM             (0xff000000 >> 24)
1174 #define ECC_ERR_INJECT_EEIM_SHIFT       0
1175
1176 /*
1177  * CAPTURE_ECC - Memory data path read capture ECC
1178  */
1179 #define CAPTURE_ECC_ECE                 (0xff000000 >> 24)
1180 #define CAPTURE_ECC_ECE_SHIFT           0
1181
1182 /*
1183  * ERR_DETECT - Memory error detect
1184  */
1185 /* Multiple Memory Errors */
1186 #define ECC_ERROR_DETECT_MME            (0x80000000 >> 0)
1187 /* Multiple-Bit Error */
1188 #define ECC_ERROR_DETECT_MBE            (0x80000000 >> 28)
1189 /* Single-Bit ECC Error Pickup */
1190 #define ECC_ERROR_DETECT_SBE            (0x80000000 >> 29)
1191 /* Memory Select Error */
1192 #define ECC_ERROR_DETECT_MSE            (0x80000000 >> 31)
1193
1194 /*
1195  * ERR_DISABLE - Memory error disable
1196  */
1197 /* Multiple-Bit ECC Error Disable */
1198 #define ECC_ERROR_DISABLE_MBED          (0x80000000 >> 28)
1199 /* Sinle-Bit ECC Error disable */
1200 #define ECC_ERROR_DISABLE_SBED          (0x80000000 >> 29)
1201 /* Memory Select Error Disable */
1202 #define ECC_ERROR_DISABLE_MSED          (0x80000000 >> 31)
1203 #define ECC_ERROR_ENABLE                (~(ECC_ERROR_DISABLE_MSED | \
1204                                                 ECC_ERROR_DISABLE_SBED | \
1205                                                 ECC_ERROR_DISABLE_MBED))
1206
1207 /*
1208  * ERR_INT_EN - Memory error interrupt enable
1209  */
1210 /* Multiple-Bit ECC Error Interrupt Enable */
1211 #define ECC_ERR_INT_EN_MBEE             (0x80000000 >> 28)
1212 /* Single-Bit ECC Error Interrupt Enable */
1213 #define ECC_ERR_INT_EN_SBEE             (0x80000000 >> 29)
1214 /* Memory Select Error Interrupt Enable */
1215 #define ECC_ERR_INT_EN_MSEE             (0x80000000 >> 31)
1216 #define ECC_ERR_INT_DISABLE             (~(ECC_ERR_INT_EN_MBEE | \
1217                                                 ECC_ERR_INT_EN_SBEE | \
1218                                                 ECC_ERR_INT_EN_MSEE))
1219
1220 /*
1221  * CAPTURE_ATTRIBUTES - Memory error attributes capture
1222  */
1223 /* Data Beat Num */
1224 #define ECC_CAPT_ATTR_BNUM              (0xe0000000 >> 1)
1225 #define ECC_CAPT_ATTR_BNUM_SHIFT        28
1226 /* Transaction Size */
1227 #define ECC_CAPT_ATTR_TSIZ              (0xc0000000 >> 6)
1228 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW      0
1229 #define ECC_CAPT_ATTR_TSIZ_ONE_DW       1
1230 #define ECC_CAPT_ATTR_TSIZ_TWO_DW       2
1231 #define ECC_CAPT_ATTR_TSIZ_THREE_DW     3
1232 #define ECC_CAPT_ATTR_TSIZ_SHIFT        24
1233 /* Transaction Source */
1234 #define ECC_CAPT_ATTR_TSRC              (0xf8000000 >> 11)
1235 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
1236 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1237 #define ECC_CAPT_ATTR_TSRC_TSEC1        0x4
1238 #define ECC_CAPT_ATTR_TSRC_TSEC2        0x5
1239 #define ECC_CAPT_ATTR_TSRC_USB          (0x06|0x07)
1240 #define ECC_CAPT_ATTR_TSRC_ENCRYPT      0x8
1241 #define ECC_CAPT_ATTR_TSRC_I2C          0x9
1242 #define ECC_CAPT_ATTR_TSRC_JTAG         0xA
1243 #define ECC_CAPT_ATTR_TSRC_PCI1         0xD
1244 #define ECC_CAPT_ATTR_TSRC_PCI2         0xE
1245 #define ECC_CAPT_ATTR_TSRC_DMA          0xF
1246 #define ECC_CAPT_ATTR_TSRC_SHIFT        16
1247 /* Transaction Type */
1248 #define ECC_CAPT_ATTR_TTYP              (0xe0000000 >> 18)
1249 #define ECC_CAPT_ATTR_TTYP_WRITE        0x1
1250 #define ECC_CAPT_ATTR_TTYP_READ         0x2
1251 #define ECC_CAPT_ATTR_TTYP_R_M_W        0x3
1252 #define ECC_CAPT_ATTR_TTYP_SHIFT        12
1253 #define ECC_CAPT_ATTR_VLD               (0x80000000 >> 31)      /* Valid */
1254
1255 /*
1256  * ERR_SBE - Single bit ECC memory error management
1257  */
1258 /* Single-Bit Error Threshold 0..255 */
1259 #define ECC_ERROR_MAN_SBET              (0xff000000 >> 8)
1260 #define ECC_ERROR_MAN_SBET_SHIFT        16
1261 /* Single Bit Error Counter 0..255 */
1262 #define ECC_ERROR_MAN_SBEC              (0xff000000 >> 24)
1263 #define ECC_ERROR_MAN_SBEC_SHIFT        0
1264
1265 /*
1266  * CONFIG_ADDRESS - PCI Config Address Register
1267  */
1268 #define PCI_CONFIG_ADDRESS_EN           0x80000000
1269 #define PCI_CONFIG_ADDRESS_BN_SHIFT     16
1270 #define PCI_CONFIG_ADDRESS_BN_MASK      0x00ff0000
1271 #define PCI_CONFIG_ADDRESS_DN_SHIFT     11
1272 #define PCI_CONFIG_ADDRESS_DN_MASK      0x0000f800
1273 #define PCI_CONFIG_ADDRESS_FN_SHIFT     8
1274 #define PCI_CONFIG_ADDRESS_FN_MASK      0x00000700
1275 #define PCI_CONFIG_ADDRESS_RN_SHIFT     0
1276 #define PCI_CONFIG_ADDRESS_RN_MASK      0x000000fc
1277
1278 /*
1279  * POTAR - PCI Outbound Translation Address Register
1280  */
1281 #define POTAR_TA_MASK                   0x000fffff
1282
1283 /*
1284  * POBAR - PCI Outbound Base Address Register
1285  */
1286 #define POBAR_BA_MASK                   0x000fffff
1287
1288 /*
1289  * POCMR - PCI Outbound Comparision Mask Register
1290  */
1291 #define POCMR_EN                        0x80000000
1292 /* 0-memory space 1-I/O space */
1293 #define POCMR_IO                        0x40000000
1294 #define POCMR_SE                        0x20000000      /* streaming enable */
1295 #define POCMR_DST                       0x10000000      /* 0-PCI1 1-PCI2 */
1296 #define POCMR_CM_MASK                   0x000fffff
1297 #define POCMR_CM_4G                     0x00000000
1298 #define POCMR_CM_2G                     0x00080000
1299 #define POCMR_CM_1G                     0x000C0000
1300 #define POCMR_CM_512M                   0x000E0000
1301 #define POCMR_CM_256M                   0x000F0000
1302 #define POCMR_CM_128M                   0x000F8000
1303 #define POCMR_CM_64M                    0x000FC000
1304 #define POCMR_CM_32M                    0x000FE000
1305 #define POCMR_CM_16M                    0x000FF000
1306 #define POCMR_CM_8M                     0x000FF800
1307 #define POCMR_CM_4M                     0x000FFC00
1308 #define POCMR_CM_2M                     0x000FFE00
1309 #define POCMR_CM_1M                     0x000FFF00
1310 #define POCMR_CM_512K                   0x000FFF80
1311 #define POCMR_CM_256K                   0x000FFFC0
1312 #define POCMR_CM_128K                   0x000FFFE0
1313 #define POCMR_CM_64K                    0x000FFFF0
1314 #define POCMR_CM_32K                    0x000FFFF8
1315 #define POCMR_CM_16K                    0x000FFFFC
1316 #define POCMR_CM_8K                     0x000FFFFE
1317 #define POCMR_CM_4K                     0x000FFFFF
1318
1319 /*
1320  * PITAR - PCI Inbound Translation Address Register
1321  */
1322 #define PITAR_TA_MASK                   0x000fffff
1323
1324 /*
1325  * PIBAR - PCI Inbound Base/Extended Address Register
1326  */
1327 #define PIBAR_MASK                      0xffffffff
1328 #define PIEBAR_EBA_MASK                 0x000fffff
1329
1330 /*
1331  * PIWAR - PCI Inbound Windows Attributes Register
1332  */
1333 #define PIWAR_EN                        0x80000000
1334 #define PIWAR_PF                        0x20000000
1335 #define PIWAR_RTT_MASK                  0x000f0000
1336 #define PIWAR_RTT_NO_SNOOP              0x00040000
1337 #define PIWAR_RTT_SNOOP                 0x00050000
1338 #define PIWAR_WTT_MASK                  0x0000f000
1339 #define PIWAR_WTT_NO_SNOOP              0x00004000
1340 #define PIWAR_WTT_SNOOP                 0x00005000
1341 #define PIWAR_IWS_MASK                  0x0000003F
1342 #define PIWAR_IWS_4K                    0x0000000B
1343 #define PIWAR_IWS_8K                    0x0000000C
1344 #define PIWAR_IWS_16K                   0x0000000D
1345 #define PIWAR_IWS_32K                   0x0000000E
1346 #define PIWAR_IWS_64K                   0x0000000F
1347 #define PIWAR_IWS_128K                  0x00000010
1348 #define PIWAR_IWS_256K                  0x00000011
1349 #define PIWAR_IWS_512K                  0x00000012
1350 #define PIWAR_IWS_1M                    0x00000013
1351 #define PIWAR_IWS_2M                    0x00000014
1352 #define PIWAR_IWS_4M                    0x00000015
1353 #define PIWAR_IWS_8M                    0x00000016
1354 #define PIWAR_IWS_16M                   0x00000017
1355 #define PIWAR_IWS_32M                   0x00000018
1356 #define PIWAR_IWS_64M                   0x00000019
1357 #define PIWAR_IWS_128M                  0x0000001A
1358 #define PIWAR_IWS_256M                  0x0000001B
1359 #define PIWAR_IWS_512M                  0x0000001C
1360 #define PIWAR_IWS_1G                    0x0000001D
1361 #define PIWAR_IWS_2G                    0x0000001E
1362
1363 /*
1364  * PMCCR1 - PCI Configuration Register 1
1365  */
1366 #define PMCCR1_POWER_OFF                0x00000020
1367
1368 /*
1369  * DDRCDR - DDR Control Driver Register
1370  */
1371 #define DDRCDR_DHC_EN           0x80000000
1372 #define DDRCDR_EN               0x40000000
1373 #define DDRCDR_PZ               0x3C000000
1374 #define DDRCDR_PZ_MAXZ          0x00000000
1375 #define DDRCDR_PZ_HIZ           0x20000000
1376 #define DDRCDR_PZ_NOMZ          0x30000000
1377 #define DDRCDR_PZ_LOZ           0x38000000
1378 #define DDRCDR_PZ_MINZ          0x3C000000
1379 #define DDRCDR_NZ               0x3C000000
1380 #define DDRCDR_NZ_MAXZ          0x00000000
1381 #define DDRCDR_NZ_HIZ           0x02000000
1382 #define DDRCDR_NZ_NOMZ          0x03000000
1383 #define DDRCDR_NZ_LOZ           0x03800000
1384 #define DDRCDR_NZ_MINZ          0x03C00000
1385 #define DDRCDR_ODT              0x00080000
1386 #define DDRCDR_DDR_CFG          0x00040000
1387 #define DDRCDR_M_ODR            0x00000002
1388 #define DDRCDR_Q_DRN            0x00000001
1389
1390 /*
1391  * PCIE Bridge Register
1392  */
1393 #define PEX_CSB_CTRL_OBPIOE     0x00000001
1394 #define PEX_CSB_CTRL_IBPIOE     0x00000002
1395 #define PEX_CSB_CTRL_WDMAE      0x00000004
1396 #define PEX_CSB_CTRL_RDMAE      0x00000008
1397
1398 #define PEX_CSB_OBCTRL_PIOE     0x00000001
1399 #define PEX_CSB_OBCTRL_MEMWE    0x00000002
1400 #define PEX_CSB_OBCTRL_IOWE     0x00000004
1401 #define PEX_CSB_OBCTRL_CFGWE    0x00000008
1402
1403 #define PEX_CSB_IBCTRL_PIOE     0x00000001
1404
1405 #define PEX_OWAR_EN             0x00000001
1406 #define PEX_OWAR_TYPE_CFG       0x00000000
1407 #define PEX_OWAR_TYPE_IO        0x00000002
1408 #define PEX_OWAR_TYPE_MEM       0x00000004
1409 #define PEX_OWAR_RLXO           0x00000008
1410 #define PEX_OWAR_NANP           0x00000010
1411 #define PEX_OWAR_SIZE           0xFFFFF000
1412
1413 #define PEX_IWAR_EN             0x00000001
1414 #define PEX_IWAR_TYPE_INT       0x00000000
1415 #define PEX_IWAR_TYPE_PF        0x00000004
1416 #define PEX_IWAR_TYPE_NO_PF     0x00000006
1417 #define PEX_IWAR_NSOV           0x00000008
1418 #define PEX_IWAR_NSNP           0x00000010
1419 #define PEX_IWAR_SIZE           0xFFFFF000
1420 #define PEX_IWAR_SIZE_1M        0x000FF000
1421 #define PEX_IWAR_SIZE_2M        0x001FF000
1422 #define PEX_IWAR_SIZE_4M        0x003FF000
1423 #define PEX_IWAR_SIZE_8M        0x007FF000
1424 #define PEX_IWAR_SIZE_16M       0x00FFF000
1425 #define PEX_IWAR_SIZE_32M       0x01FFF000
1426 #define PEX_IWAR_SIZE_64M       0x03FFF000
1427 #define PEX_IWAR_SIZE_128M      0x07FFF000
1428 #define PEX_IWAR_SIZE_256M      0x0FFFF000
1429
1430 #define PEX_GCLK_RATIO          0x440
1431
1432 #ifndef __ASSEMBLY__
1433 struct pci_region;
1434 void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
1435 void mpc83xx_pcislave_unlock(int bus);
1436 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
1437 #endif
1438
1439 #endif  /* __MPC83XX_H__ */