git.sur5r.net Git - u-boot/blob - include/mtd/cfi_flash.h

   1 /*
   2  * (C) Copyright 2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #ifndef __CFI_FLASH_H__
  26 #define __CFI_FLASH_H__
  27
  28 #define FLASH_CMD_CFI                   0x98
  29 #define FLASH_CMD_READ_ID               0x90
  30 #define FLASH_CMD_RESET                 0xff
  31 #define FLASH_CMD_BLOCK_ERASE           0x20
  32 #define FLASH_CMD_ERASE_CONFIRM         0xD0
  33 #define FLASH_CMD_WRITE                 0x40
  34 #define FLASH_CMD_PROTECT               0x60
  35 #define FLASH_CMD_PROTECT_SET           0x01
  36 #define FLASH_CMD_PROTECT_CLEAR         0xD0
  37 #define FLASH_CMD_CLEAR_STATUS          0x50
  38 #define FLASH_CMD_READ_STATUS           0x70
  39 #define FLASH_CMD_WRITE_TO_BUFFER       0xE8
  40 #define FLASH_CMD_WRITE_BUFFER_PROG     0xE9
  41 #define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
  42
  43 #define FLASH_STATUS_DONE               0x80
  44 #define FLASH_STATUS_ESS                0x40
  45 #define FLASH_STATUS_ECLBS              0x20
  46 #define FLASH_STATUS_PSLBS              0x10
  47 #define FLASH_STATUS_VPENS              0x08
  48 #define FLASH_STATUS_PSS                0x04
  49 #define FLASH_STATUS_DPS                0x02
  50 #define FLASH_STATUS_R                  0x01
  51 #define FLASH_STATUS_PROTECT            0x01
  52
  53 #define AMD_CMD_RESET                   0xF0
  54 #define AMD_CMD_WRITE                   0xA0
  55 #define AMD_CMD_ERASE_START             0x80
  56 #define AMD_CMD_ERASE_SECTOR            0x30
  57 #define AMD_CMD_UNLOCK_START            0xAA
  58 #define AMD_CMD_UNLOCK_ACK              0x55
  59 #define AMD_CMD_WRITE_TO_BUFFER         0x25
  60 #define AMD_CMD_WRITE_BUFFER_CONFIRM    0x29
  61
  62 #define AMD_STATUS_TOGGLE               0x40
  63 #define AMD_STATUS_ERROR                0x20
  64
  65 #define ATM_CMD_UNLOCK_SECT             0x70
  66 #define ATM_CMD_SOFTLOCK_START          0x80
  67 #define ATM_CMD_LOCK_SECT               0x40
  68
  69 #define FLASH_CONTINUATION_CODE         0x7F
  70
  71 #define FLASH_OFFSET_MANUFACTURER_ID    0x00
  72 #define FLASH_OFFSET_DEVICE_ID          0x01
  73 #define FLASH_OFFSET_DEVICE_ID2         0x0E
  74 #define FLASH_OFFSET_DEVICE_ID3         0x0F
  75 #define FLASH_OFFSET_CFI                0x55
  76 #define FLASH_OFFSET_CFI_ALT            0x555
  77 #define FLASH_OFFSET_CFI_RESP           0x10
  78 #define FLASH_OFFSET_PRIMARY_VENDOR     0x13
  79 /* extended query table primary address */
  80 #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
  81 #define FLASH_OFFSET_WTOUT              0x1F
  82 #define FLASH_OFFSET_WBTOUT             0x20
  83 #define FLASH_OFFSET_ETOUT              0x21
  84 #define FLASH_OFFSET_CETOUT             0x22
  85 #define FLASH_OFFSET_WMAX_TOUT          0x23
  86 #define FLASH_OFFSET_WBMAX_TOUT         0x24
  87 #define FLASH_OFFSET_EMAX_TOUT          0x25
  88 #define FLASH_OFFSET_CEMAX_TOUT         0x26
  89 #define FLASH_OFFSET_SIZE               0x27
  90 #define FLASH_OFFSET_INTERFACE          0x28
  91 #define FLASH_OFFSET_BUFFER_SIZE        0x2A
  92 #define FLASH_OFFSET_NUM_ERASE_REGIONS  0x2C
  93 #define FLASH_OFFSET_ERASE_REGIONS      0x2D
  94 #define FLASH_OFFSET_PROTECT            0x02
  95 #define FLASH_OFFSET_USER_PROTECTION    0x85
  96 #define FLASH_OFFSET_INTEL_PROTECTION   0x81
  97
  98 #define CFI_CMDSET_NONE                 0
  99 #define CFI_CMDSET_INTEL_EXTENDED       1
 100 #define CFI_CMDSET_AMD_STANDARD         2
 101 #define CFI_CMDSET_INTEL_STANDARD       3
 102 #define CFI_CMDSET_AMD_EXTENDED         4
 103 #define CFI_CMDSET_MITSU_STANDARD       256
 104 #define CFI_CMDSET_MITSU_EXTENDED       257
 105 #define CFI_CMDSET_SST                  258
 106 #define CFI_CMDSET_INTEL_PROG_REGIONS   512
 107
 108 #ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
 109 # undef  FLASH_CMD_RESET
 110 # define FLASH_CMD_RESET        AMD_CMD_RESET /* use AMD-Reset instead */
 111 #endif
 112
 113 #define NUM_ERASE_REGIONS       4 /* max. number of erase regions */
 114
 115 typedef union {
 116         unsigned char c;
 117         unsigned short w;
 118         unsigned long l;
 119         unsigned long long ll;
 120 } cfiword_t;
 121
 122 /* CFI standard query structure */
 123 struct cfi_qry {
 124         u8      qry[3];
 125         u16     p_id;
 126         u16     p_adr;
 127         u16     a_id;
 128         u16     a_adr;
 129         u8      vcc_min;
 130         u8      vcc_max;
 131         u8      vpp_min;
 132         u8      vpp_max;
 133         u8      word_write_timeout_typ;
 134         u8      buf_write_timeout_typ;
 135         u8      block_erase_timeout_typ;
 136         u8      chip_erase_timeout_typ;
 137         u8      word_write_timeout_max;
 138         u8      buf_write_timeout_max;
 139         u8      block_erase_timeout_max;
 140         u8      chip_erase_timeout_max;
 141         u8      dev_size;
 142         u16     interface_desc;
 143         u16     max_buf_write_size;
 144         u8      num_erase_regions;
 145         u32     erase_region_info[NUM_ERASE_REGIONS];
 146 } __attribute__((packed));
 147
 148 struct cfi_pri_hdr {
 149         u8      pri[3];
 150         u8      major_version;
 151         u8      minor_version;
 152 } __attribute__((packed));
 153
 154 void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
 155                      uint offset, u32 cmd);
 156
 157 #endif /* __CFI_FLASH_H__ */