2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
13 * class_csr - block containing all the classifier control and status register.
14 * Mapped on CBUS and accessible from all PE's and ARM.
16 #define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
17 #define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
18 #define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
19 /* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
20 #define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
21 /* LMEM header size for the Classifier block.
22 * Data in the LMEM is written from this offset.
24 #define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f)
25 /* DDR header size for the Classifier block.
26 * Data in the DDR is written from this offset.
28 #define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16)
30 /* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
31 #define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
32 /* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
33 #define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024)
35 /* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
36 #define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060)
37 /* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
38 #define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064)
41 * @name Class PE memory access. Allows external PE's and HOST to
42 * read/write PMEM/DMEM memory ranges for each classifier PE.
44 #define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100)
45 /* Internal Memory Access Write Data [31:0] */
46 #define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104)
47 /* Internal Memory Access Read Data [31:0] */
48 #define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108)
49 #define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
50 #define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
52 #define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
53 #define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
54 #define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
55 #define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
56 #define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
57 #define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
58 #define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
59 #define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
60 #define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
61 #define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
63 #define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
64 /* bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR */
65 #define CLASS_BUS_ACCESS_ADDR_MASK (0x0001FFFF)
67 #define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
68 #define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
71 * (route_entry_size[9:0], route_hash_size[23:16]
72 * (this is actually ln2(size)))
74 #define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234)
75 #define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
76 #define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
78 #define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
79 #define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
80 #define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
81 #define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
82 #define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
83 #define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
84 #define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
85 #define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
87 #define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
88 /* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
89 #define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000)
91 #define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
93 #define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
94 #define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
95 #define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
96 #define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
97 #define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
98 #define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
99 #define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
100 #define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
101 #define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
102 #define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
103 #define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
104 #define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
106 #define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
107 #define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
109 #define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
110 #define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
112 #define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
114 #define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
115 #define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
116 #define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
117 #define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
118 #define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
119 #define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
121 #define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
122 #define CLASS_AXI_CTRL (CLASS_CSR_BASE_ADDR + 0x2d0)
125 #define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
126 #define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
128 #define CLASS_PBUF0_BASE_ADDR 0x000 /* Can be configured */
129 /* Can be configured */
130 #define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
131 /* Can be configured */
132 #define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
133 /* Can be configured */
134 #define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
136 #define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR +\
137 CLASS_PBUF_HEADER_OFFSET)
138 #define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR +\
139 CLASS_PBUF_HEADER_OFFSET)
140 #define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR +\
141 CLASS_PBUF_HEADER_OFFSET)
142 #define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR +\
143 CLASS_PBUF_HEADER_OFFSET)
145 #define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) |\
146 CLASS_PBUF0_BASE_ADDR)
147 #define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) |\
148 CLASS_PBUF2_BASE_ADDR)
150 #define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16)\
151 | CLASS_PBUF0_HEADER_BASE_ADDR)
152 #define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16)\
153 | CLASS_PBUF2_HEADER_BASE_ADDR)
155 #define CLASS_ROUTE_SIZE 128
156 #define CLASS_ROUTE_HASH_BITS 20
157 #define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1)
159 #define TWO_LEVEL_ROUTE BIT(0)
160 #define PHYNO_IN_HASH BIT(1)
161 #define HW_ROUTE_FETCH BIT(3)
162 #define HW_BRIDGE_FETCH BIT(5)
163 #define IP_ALIGNED BIT(6)
164 #define ARC_HIT_CHECK_EN BIT(7)
165 #define CLASS_TOE BIT(11)
166 #define HASH_CRC_PORT BIT(12)
167 #define HASH_CRC_IP BIT(13)
168 #define HASH_CRC_PORT_IP GENMASK(13, 12)
169 #define QB2BUS_LE BIT(15)
171 #define TCP_CHKSUM_DROP BIT(0)
172 #define UDP_CHKSUM_DROP BIT(1)
173 #define IPV4_CHKSUM_DROP BIT(9)
176 u32 route_table_baseaddr;
177 u32 route_table_hash_bits;
180 #endif /* _CLASS_CSR_H_ */