2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
13 * hif - PFE hif block control and status register.
14 * Mapped on CBUS and accessible from all PE's and ARM.
16 #define HIF_VERSION (HIF_BASE_ADDR + 0x00)
17 #define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
18 #define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
19 #define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
20 #define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
21 #define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
22 #define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
23 #define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
24 #define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
25 #define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
26 #define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
27 #define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
28 #define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
29 #define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
30 #define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
31 #define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
32 #define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
33 #define HIF_AXI_CTRL (HIF_BASE_ADDR + 0x54)
35 /* HIF_TX_CTRL bits */
36 #define HIF_CTRL_DMA_EN BIT(0)
37 #define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1)
38 #define HIF_CTRL_BDP_CH_START_WSTB BIT(2)
40 /* HIF_RX_STATUS bits */
41 #define BDP_CSR_RX_DMA_ACTV BIT(16)
43 /* HIF_INT_ENABLE bits */
44 #define HIF_INT_EN BIT(0)
45 #define HIF_RXBD_INT_EN BIT(1)
46 #define HIF_RXPKT_INT_EN BIT(2)
47 #define HIF_TXBD_INT_EN BIT(3)
48 #define HIF_TXPKT_INT_EN BIT(4)
50 /* HIF_POLL_CTRL bits*/
51 #define HIF_RX_POLL_CTRL_CYCLE 0x0400
52 #define HIF_TX_POLL_CTRL_CYCLE 0x0400
54 /* Buffer descriptor control bits */
55 #define BD_CTRL_BUFLEN_MASK (0xffff)
56 #define BD_BUF_LEN(x) (x & BD_CTRL_BUFLEN_MASK)
57 #define BD_CTRL_CBD_INT_EN BIT(16)
58 #define BD_CTRL_PKT_INT_EN BIT(17)
59 #define BD_CTRL_LIFM BIT(18)
60 #define BD_CTRL_LAST_BD BIT(19)
61 #define BD_CTRL_DIR BIT(20)
62 #define BD_CTRL_PKT_XFER BIT(24)
63 #define BD_CTRL_DESC_EN BIT(31)
64 #define BD_CTRL_PARSE_DISABLE BIT(25)
65 #define BD_CTRL_BRFETCH_DISABLE BIT(26)
66 #define BD_CTRL_RTFETCH_DISABLE BIT(27)