git.sur5r.net Git - u-boot/blob - include/power/mc34vr500_pmic.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  * Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __MC34VR500_H_
   9 #define __MC34VR500_H_
  10
  11 #include <power/pmic.h>
  12
  13 #define MC34VR500_I2C_ADDR      0x08
  14
  15 /* Drivers name */
  16 #define MC34VR500_REGULATOR_DRIVER      "mc34vr500_regulator"
  17
  18 /* Register map */
  19 enum {
  20         MC34VR500_DEVICEID              = 0x00,
  21
  22         MC34VR500_SILICONREVID          = 0x03,
  23         MC34VR500_FABID,
  24         MC34VR500_INTSTAT0,
  25         MC34VR500_INTMASK0,
  26         MC34VR500_INTSENSE0,
  27         MC34VR500_INTSTAT1,
  28         MC34VR500_INTMASK1,
  29         MC34VR500_INTSENSE1,
  30
  31         MC34VR500_INTSTAT4              = 0x11,
  32         MC34VR500_INTMASK4,
  33         MC34VR500_INTSENSE4,
  34
  35         MC34VR500_PWRCTL                = 0x1B,
  36
  37         MC34VR500_SW1VOLT               = 0x2E,
  38         MC34VR500_SW1STBY,
  39         MC34VR500_SW1OFF,
  40         MC34VR500_SW1MODE,
  41         MC34VR500_SW1CONF,
  42         MC34VR500_SW2VOLT,
  43         MC34VR500_SW2STBY,
  44         MC34VR500_SW2OFF,
  45         MC34VR500_SW2MODE,
  46         MC34VR500_SW2CONF,
  47
  48         MC34VR500_SW3VOLT               = 0x3C,
  49         MC34VR500_SW3STBY,
  50         MC34VR500_SW3OFF,
  51         MC34VR500_SW3MODE,
  52         MC34VR500_SW3CONF,
  53
  54         MC34VR500_SW4VOLT               = 0x4A,
  55         MC34VR500_SW4STBY,
  56         MC34VR500_SW4OFF,
  57         MC34VR500_SW4MODE,
  58         MC34VR500_SW4CONF,
  59
  60         MC34VR500_REFOUTCRTRL           = 0x6A,
  61
  62         MC34VR500_LDO1CTL               = 0x6D,
  63         MC34VR500_LDO2CTL,
  64         MC34VR500_LDO3CTL,
  65         MC34VR500_LDO4CTL,
  66         MC34VR500_LDO5CTL,
  67
  68         MC34VR500_PAGE_REGISTER         = 0x7F,
  69
  70         /* Internal RAM */
  71         MC34VR500_SW1_VOLT              = 0xA8,
  72         MC34VR500_SW1_SEQ,
  73         MC34VR500_SW1_CONFIG,
  74
  75         MC34VR500_SW2_VOLT              = 0xAC,
  76         MC34VR500_SW2_SEQ,
  77         MC34VR500_SW2_CONFIG,
  78
  79         MC34VR500_SW3_VOLT              = 0xB0,
  80         MC34VR500_SW3_SEQ,
  81         MC34VR500_SW3_CONFIG,
  82
  83         MC34VR500_SW4_VOLT              = 0xB8,
  84         MC34VR500_SW4_SEQ,
  85         MC34VR500_SW4_CONFIG,
  86
  87         MC34VR500_REFOUT_SEQ            = 0xC4,
  88
  89         MC34VR500_LDO1_VOLT             = 0xCC,
  90         MC34VR500_LDO1_SEQ,
  91
  92         MC34VR500_LDO2_VOLT             = 0xD0,
  93         MC34VR500_LDO2_SEQ,
  94
  95         MC34VR500_LDO3_VOLT             = 0xD4,
  96         MC34VR500_LDO3_SEQ,
  97
  98         MC34VR500_LDO4_VOLT             = 0xD8,
  99         MC34VR500_LDO4_SEQ,
 100
 101         MC34VR500_LDO5_VOLT             = 0xDC,
 102         MC34VR500_LDO5_SEQ,
 103
 104         MC34VR500_PU_CONFIG1            = 0xE0,
 105
 106         MC34VR500_TBB_POR               = 0xE4,
 107
 108         MC34VR500_PWRGD_EN              = 0xE8,
 109
 110         MC34VR500_NUM_OF_REGS,
 111 };
 112
 113 /* Registor offset based on SWxVOLT register */
 114 #define MC34VR500_VOLT_OFFSET   0
 115 #define MC34VR500_STBY_OFFSET   1
 116 #define MC34VR500_OFF_OFFSET    2
 117 #define MC34VR500_MODE_OFFSET   3
 118 #define MC34VR500_CONF_OFFSET   4
 119
 120 #define SW_MODE_MASK    0xf
 121 #define SW_MODE_SHIFT   0
 122
 123 #define LDO_VOL_MASK    0xf
 124 #define LDO_EN          (1 << 4)
 125 #define LDO_MODE_SHIFT  4
 126 #define LDO_MODE_MASK   (1 << 4)
 127 #define LDO_MODE_OFF    0
 128 #define LDO_MODE_ON     1
 129
 130 #define REFOUTEN        (1 << 4)
 131
 132 /*
 133  * Regulator Mode Control
 134  *
 135  * OFF: The regulator is switched off and the output voltage is discharged.
 136  * PFM: In this mode, the regulator is always in PFM mode, which is useful
 137  *      at light loads for optimized efficiency.
 138  * PWM: In this mode, the regulator is always in PWM mode operation
 139  *      regardless of load conditions.
 140  * APS: In this mode, the regulator moves automatically between pulse
 141  *      skipping mode and PWM mode depending on load conditions.
 142  *
 143  * SWxMODE[3:0]
 144  * Normal Mode  |  Standby Mode |      value
 145  *   OFF                OFF             0x0
 146  *   PWM                OFF             0x1
 147  *   PFM                OFF             0x3
 148  *   APS                OFF             0x4
 149  *   PWM                PWM             0x5
 150  *   PWM                APS             0x6
 151  *   APS                APS             0x8
 152  *   APS                PFM             0xc
 153  *   PWM                PFM             0xd
 154  */
 155 #define OFF_OFF         0x0
 156 #define PWM_OFF         0x1
 157 #define PFM_OFF         0x3
 158 #define APS_OFF         0x4
 159 #define PWM_PWM         0x5
 160 #define PWM_APS         0x6
 161 #define APS_APS         0x8
 162 #define APS_PFM         0xc
 163 #define PWM_PFM         0xd
 164
 165 enum swx {
 166         SW1 = 0,
 167         SW2,
 168         SW3,
 169         SW4,
 170 };
 171
 172 int mc34vr500_get_sw_volt(uint8_t sw);
 173 int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt);
 174 int power_mc34vr500_init(unsigned char bus);
 175 #endif /* __MC34VR500_PMIC_H_ */