1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 /* Define bits and masks for real-mode storage attribute control registers */
26 #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
27 #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
30 #define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
32 #define CFG_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
35 /*--------------------------------------------------------------------- */
36 /* Special Purpose Registers */
37 /*--------------------------------------------------------------------- */
38 #define srr2 0x3de /* save/restore register 2 */
39 #define srr3 0x3df /* save/restore register 3 */
42 * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
43 * exception for the exact same purposes - let's alias them and have a
44 * common handling in crit_return() and CRIT_EXCEPTION
49 #define dbsr 0x3f0 /* debug status register */
50 #define dbcr0 0x3f2 /* debug control register 0 */
51 #define dbcr1 0x3bd /* debug control register 1 */
52 #define iac1 0x3f4 /* instruction address comparator 1 */
53 #define iac2 0x3f5 /* instruction address comparator 2 */
54 #define iac3 0x3b4 /* instruction address comparator 3 */
55 #define iac4 0x3b5 /* instruction address comparator 4 */
56 #define dac1 0x3f6 /* data address comparator 1 */
57 #define dac2 0x3f7 /* data address comparator 2 */
58 #define dccr 0x3fa /* data cache control register */
59 #define iccr 0x3fb /* instruction cache control register */
60 #define esr 0x3d4 /* execption syndrome register */
61 #define dear 0x3d5 /* data exeption address register */
62 #define evpr 0x3d6 /* exeption vector prefix register */
63 #define tsr 0x3d8 /* timer status register */
64 #define tcr 0x3da /* timer control register */
65 #define pit 0x3db /* programmable interval timer */
66 #define sgr 0x3b9 /* storage guarded reg */
67 #define dcwr 0x3ba /* data cache write-thru reg*/
68 #define sler 0x3bb /* storage little-endian reg */
69 #define cdbcr 0x3d7 /* cache debug cntrl reg */
70 #define icdbdr 0x3d3 /* instr cache dbug data reg*/
71 #define ccr0 0x3b3 /* core configuration register */
72 #define dvc1 0x3b6 /* data value compare register 1 */
73 #define dvc2 0x3b7 /* data value compare register 2 */
74 #define pid 0x3b1 /* process ID */
75 #define su0r 0x3bc /* storage user-defined register 0 */
76 #define zpr 0x3b0 /* zone protection regsiter */
78 #define tbl 0x11c /* time base lower - privileged write */
79 #define tbu 0x11d /* time base upper - privileged write */
81 #define sprg4r 0x104 /* Special purpose general 4 - read only */
82 #define sprg5r 0x105 /* Special purpose general 5 - read only */
83 #define sprg6r 0x106 /* Special purpose general 6 - read only */
84 #define sprg7r 0x107 /* Special purpose general 7 - read only */
85 #define sprg4w 0x114 /* Special purpose general 4 - write only */
86 #define sprg5w 0x115 /* Special purpose general 5 - write only */
87 #define sprg6w 0x116 /* Special purpose general 6 - write only */
88 #define sprg7w 0x117 /* Special purpose general 7 - write only */
90 /******************************************************************************
91 * Special for PPC405GP
92 ******************************************************************************/
94 /******************************************************************************
96 ******************************************************************************/
97 #define DMA_DCR_BASE 0x100
98 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
99 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
100 #define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
101 #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
102 #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
103 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
104 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
105 #define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
106 #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
107 #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
108 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
109 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
110 #define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
111 #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
112 #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
113 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
114 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
115 #define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
116 #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
117 #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
118 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
119 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
120 #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
122 /******************************************************************************
123 * Universal interrupt controller
124 ******************************************************************************/
125 #define UIC_SR 0x0 /* UIC status */
126 #define UIC_ER 0x2 /* UIC enable */
127 #define UIC_CR 0x3 /* UIC critical */
128 #define UIC_PR 0x4 /* UIC polarity */
129 #define UIC_TR 0x5 /* UIC triggering */
130 #define UIC_MSR 0x6 /* UIC masked status */
131 #define UIC_VR 0x7 /* UIC vector */
132 #define UIC_VCR 0x8 /* UIC vector configuration */
134 #define UIC_DCR_BASE 0xc0
135 #define UIC0_DCR_BASE UIC_DCR_BASE
136 #define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
137 #define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
138 #define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
139 #define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
140 #define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
141 #define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
142 #define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
143 #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
144 #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
146 #if defined(CONFIG_405EX)
147 #define uic0sr uicsr /* UIC status */
148 #define uic0srs uicsrs /* UIC status set */
149 #define uic0er uicer /* UIC enable */
150 #define uic0cr uiccr /* UIC critical */
151 #define uic0pr uicpr /* UIC polarity */
152 #define uic0tr uictr /* UIC triggering */
153 #define uic0msr uicmsr /* UIC masked status */
154 #define uic0vr uicvr /* UIC vector */
155 #define uic0vcr uicvcr /* UIC vector configuration*/
157 #define UIC_DCR_BASE1 0xd0
158 #define UIC1_DCR_BASE 0xd0
159 #define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
160 #define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
161 #define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
162 #define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */
163 #define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */
164 #define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */
165 #define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */
166 #define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */
167 #define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
169 #define UIC_DCR_BASE2 0xe0
170 #define UIC2_DCR_BASE 0xe0
171 #define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
172 #define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
173 #define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
174 #define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */
175 #define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */
176 #define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */
177 #define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */
178 #define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */
179 #define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/
182 /*-----------------------------------------------------------------------------+
183 | Universal interrupt controller interrupts
184 +-----------------------------------------------------------------------------*/
185 #if defined(CONFIG_405EZ)
186 #define UIC_DMA0 0x80000000 /* DMA chan. 0 */
187 #define UIC_DMA1 0x40000000 /* DMA chan. 1 */
188 #define UIC_DMA2 0x20000000 /* DMA chan. 2 */
189 #define UIC_DMA3 0x10000000 /* DMA chan. 3 */
190 #define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
191 #define UIC_UART0 0x04000000 /* UART 0 */
192 #define UIC_UART1 0x02000000 /* UART 1 */
193 #define UIC_CAN0 0x01000000 /* CAN 0 */
194 #define UIC_CAN1 0x00800000 /* CAN 1 */
195 #define UIC_SPI 0x00400000 /* SPI */
196 #define UIC_IIC 0x00200000 /* IIC */
197 #define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
198 #define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
199 #define UIC_USBH1 0x00040000 /* USB Host 1 */
200 #define UIC_USBH2 0x00020000 /* USB Host 2 */
201 #define UIC_USBDEV 0x00010000 /* USB Device */
202 #define UIC_ENET 0x00008000 /* Ethernet interrupt status */
203 #define UIC_ENET1 0x00008000 /* dummy define */
204 #define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
206 #define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
207 #define UIC_MAL_SERR 0x00002000 /* MAL SERR */
208 #define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
209 #define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
211 #define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
212 #define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
213 #define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
214 #define UIC_NAND 0x00000200 /* NAND Flash controller */
215 #define UIC_ADC 0x00000100 /* ADC */
216 #define UIC_DAC 0x00000080 /* DAC */
217 #define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
218 #define UIC_RESERVED0 0x00000020 /* Reserved */
219 #define UIC_EXT0 0x00000010 /* External interrupt 0 */
220 #define UIC_EXT1 0x00000008 /* External interrupt 1 */
221 #define UIC_EXT2 0x00000004 /* External interrupt 2 */
222 #define UIC_EXT3 0x00000002 /* External interrupt 3 */
223 #define UIC_EXT4 0x00000001 /* External interrupt 4 */
225 #elif defined(CONFIG_405EX)
228 #define UIC_U0 0x80000000 /* */
229 #define UIC_U1 0x40000000 /* */
230 #define UIC_IIC0 0x20000000 /* */
231 #define UIC_PKA 0x10000000 /* */
232 #define UIC_TRNG 0x08000000 /* */
233 #define UIC_EBM 0x04000000 /* */
234 #define UIC_BGI 0x02000000 /* */
235 #define UIC_IIC1 0x01000000 /* */
236 #define UIC_SPI 0x00800000 /* */
237 #define UIC_EIRQ0 0x00400000 /**/
238 #define UIC_MTE 0x00200000 /*MAL Tx EOB */
239 #define UIC_MRE 0x00100000 /*MAL Rx EOB */
240 #define UIC_DMA0 0x00080000 /* */
241 #define UIC_DMA1 0x00040000 /* */
242 #define UIC_DMA2 0x00020000 /* */
243 #define UIC_DMA3 0x00010000 /* */
244 #define UIC_PCIE0AL 0x00008000 /* */
245 #define UIC_PCIE0VPD 0x00004000 /* */
246 #define UIC_RPCIE0HRST 0x00002000 /* */
247 #define UIC_FPCIE0HRST 0x00001000 /* */
248 #define UIC_PCIE0TCR 0x00000800 /* */
249 #define UIC_PCIEMSI0 0x00000400 /* */
250 #define UIC_PCIEMSI1 0x00000200 /* */
251 #define UIC_SECURITY 0x00000100 /* */
252 #define UIC_ENET 0x00000080 /* */
253 #define UIC_ENET1 0x00000040 /* */
254 #define UIC_PCIEMSI2 0x00000020 /* */
255 #define UIC_EIRQ4 0x00000010 /**/
256 #define UICB0_UIC2NCI 0x00000008 /* */
257 #define UICB0_UIC2CI 0x00000004 /* */
258 #define UICB0_UIC1NCI 0x00000002 /* */
259 #define UICB0_UIC1CI 0x00000001 /* */
261 #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
262 UICB0_UIC1CI | UICB0_UIC2NCI)
264 #define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
265 #define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
267 #define UIC_MS 0x80000000 /* MAL SERR */
268 #define UIC_MTDE 0x40000000 /* MAL TXDE */
269 #define UIC_MRDE 0x20000000 /* MAL RXDE */
270 #define UIC_PCIE0BMVC0 0x10000000 /* */
271 #define UIC_PCIE0DCRERR 0x08000000 /* */
272 #define UIC_EBC 0x04000000 /* */
273 #define UIC_NDFC 0x02000000 /* */
274 #define UIC_PCEI1DCRERR 0x01000000 /* */
275 #define UIC_GPTCMPT8 0x00800000 /* */
276 #define UIC_GPTCMPT9 0x00400000 /* */
277 #define UIC_PCIE1AL 0x00200000 /* */
278 #define UIC_PCIE1VPD 0x00100000 /* */
279 #define UIC_RPCE1HRST 0x00080000 /* */
280 #define UIC_FPCE1HRST 0x00040000 /* */
281 #define UIC_PCIE1TCR 0x00020000 /* */
282 #define UIC_PCIE1VC0 0x00010000 /* */
283 #define UIC_GPTCMPT3 0x00008000 /* */
284 #define UIC_GPTCMPT4 0x00004000 /* */
285 #define UIC_EIRQ7 0x00002000 /* */
286 #define UIC_EIRQ8 0x00001000 /* */
287 #define UIC_EIRQ9 0x00000800 /* */
288 #define UIC_GPTCMP5 0x00000400 /* */
289 #define UIC_GPTCMP6 0x00000200 /* */
290 #define UIC_GPTCMP7 0x00000100 /* */
291 #define UIC_SROM 0x00000080 /* SERIAL ROM*/
292 #define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/
293 #define UIC_EIRQ2 0x00000020 /* */
294 #define UIC_EIRQ5 0x00000010 /* */
295 #define UIC_EIRQ6 0x00000008 /* */
296 #define UIC_EMAC0WAKE 0x00000004 /* */
297 #define UIC_EIRQ1 0x00000002 /* */
298 #define UIC_EMAC1WAKE 0x00000001 /* */
299 #define UIC_MAL_SERR UIC_MS /* MAL SERR */
300 #define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */
301 #define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */
303 #define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/
304 #define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/
305 #define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/
306 #define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/
307 #define UIC_EIRQ3 0x08000000 /* External IRQ 3*/
308 #define UIC_DDRMCUE 0x04000000 /* */
309 #define UIC_DDRMCCE 0x02000000 /* */
310 #define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/
311 #define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/
312 #define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/
313 #define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/
314 #define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/
315 #define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/
316 #define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/
317 #define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/
318 #define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/
319 #define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/
320 #define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/
321 #define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/
322 #define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/
323 #define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/
324 #define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/
325 #define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/
326 #define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/
327 #define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/
328 #define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/
329 #define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/
330 #define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/
331 #define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/
332 #define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/
333 #define UIC_USBWAKE 0x00000002 /* USB wakup*/
334 #define UIC_USBOTG 0x00000001 /* USB OTG*/
335 #define UIC_ETH0 UIC_ENET
336 #define UIC_ETH1 UIC_ENET1
338 #else /* !defined(CONFIG_405EZ) */
340 #define UIC_UART0 0x80000000 /* UART 0 */
341 #define UIC_UART1 0x40000000 /* UART 1 */
342 #define UIC_IIC 0x20000000 /* IIC */
343 #define UIC_EXT_MAST 0x10000000 /* External Master */
344 #define UIC_PCI 0x08000000 /* PCI write to command reg */
345 #define UIC_DMA0 0x04000000 /* DMA chan. 0 */
346 #define UIC_DMA1 0x02000000 /* DMA chan. 1 */
347 #define UIC_DMA2 0x01000000 /* DMA chan. 2 */
348 #define UIC_DMA3 0x00800000 /* DMA chan. 3 */
349 #define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
350 #define UIC_MAL_SERR 0x00200000 /* MAL SERR */
351 #define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
352 #define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
353 #define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
354 #define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
355 #define UIC_ENET 0x00010000 /* Ethernet0 */
356 #define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */
357 #define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */
358 #define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
359 #define UIC_PCI_PM 0x00002000 /* PCI Power Management */
360 #define UIC_EXT0 0x00000040 /* External interrupt 0 */
361 #define UIC_EXT1 0x00000020 /* External interrupt 1 */
362 #define UIC_EXT2 0x00000010 /* External interrupt 2 */
363 #define UIC_EXT3 0x00000008 /* External interrupt 3 */
364 #define UIC_EXT4 0x00000004 /* External interrupt 4 */
365 #define UIC_EXT5 0x00000002 /* External interrupt 5 */
366 #define UIC_EXT6 0x00000001 /* External interrupt 6 */
367 #endif /* defined(CONFIG_405EZ) */
370 /******************************************************************************
371 * Decompression Controller
372 ******************************************************************************/
373 #define DECOMP_DCR_BASE 0x14
374 #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
375 #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
376 /* values for kiar register - indirect addressing of these regs */
377 #define kitor0 0x00 /* index table origin register 0 */
378 #define kitor1 0x01 /* index table origin register 1 */
379 #define kitor2 0x02 /* index table origin register 2 */
380 #define kitor3 0x03 /* index table origin register 3 */
381 #define kaddr0 0x04 /* address decode definition regsiter 0 */
382 #define kaddr1 0x05 /* address decode definition regsiter 1 */
383 #define kconf 0x40 /* decompression core config register */
384 #define kid 0x41 /* decompression core ID register */
385 #define kver 0x42 /* decompression core version # reg */
386 #define kpear 0x50 /* bus error addr reg (PLB addr) */
387 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
388 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
389 #define kesr0s 0x53 /* bus error status reg 0 (set) */
390 /* There are 0x400 of the following registers, from krom0 to krom3ff*/
391 /* Only the first one is given here. */
392 #define krom0 0x400 /* SRAM/ROM read/write */
395 /******************************************************************************
397 ******************************************************************************/
399 #define POWERMAN_DCR_BASE 0xb0
401 #define POWERMAN_DCR_BASE 0xb8
403 #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
404 #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
405 #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
407 /******************************************************************************
408 * Extrnal Bus Controller
409 ******************************************************************************/
410 /* values for ebccfga register - indirect addressing of these regs */
411 #define pb0cr 0x00 /* periph bank 0 config reg */
412 #define pb1cr 0x01 /* periph bank 1 config reg */
413 #define pb2cr 0x02 /* periph bank 2 config reg */
414 #define pb3cr 0x03 /* periph bank 3 config reg */
415 #define pb4cr 0x04 /* periph bank 4 config reg */
417 #define pb5cr 0x05 /* periph bank 5 config reg */
418 #define pb6cr 0x06 /* periph bank 6 config reg */
419 #define pb7cr 0x07 /* periph bank 7 config reg */
421 #define pb0ap 0x10 /* periph bank 0 access parameters */
422 #define pb1ap 0x11 /* periph bank 1 access parameters */
423 #define pb2ap 0x12 /* periph bank 2 access parameters */
424 #define pb3ap 0x13 /* periph bank 3 access parameters */
425 #define pb4ap 0x14 /* periph bank 4 access parameters */
427 #define pb5ap 0x15 /* periph bank 5 access parameters */
428 #define pb6ap 0x16 /* periph bank 6 access parameters */
429 #define pb7ap 0x17 /* periph bank 7 access parameters */
431 #define pbear 0x20 /* periph bus error addr reg */
432 #define pbesr0 0x21 /* periph bus error status reg 0 */
433 #define pbesr1 0x22 /* periph bus error status reg 1 */
434 #define epcr 0x23 /* external periph control reg */
435 #define EBC0_CFG 0x23 /* external bus configuration reg */
438 /******************************************************************************
440 ******************************************************************************/
441 #define CNTRL_DCR_BASE 0x0f0
442 #define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
443 #define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
444 #define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
445 #define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
446 #define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
447 #define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
449 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
450 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
451 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
452 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
453 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
454 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
455 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
456 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
457 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
458 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
460 /* Bit definitions */
461 #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
462 #define PLLMR0_CPU_DIV_BYPASS 0x00000000
463 #define PLLMR0_CPU_DIV_2 0x00100000
464 #define PLLMR0_CPU_DIV_3 0x00200000
465 #define PLLMR0_CPU_DIV_4 0x00300000
467 #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
468 #define PLLMR0_CPU_PLB_DIV_1 0x00000000
469 #define PLLMR0_CPU_PLB_DIV_2 0x00010000
470 #define PLLMR0_CPU_PLB_DIV_3 0x00020000
471 #define PLLMR0_CPU_PLB_DIV_4 0x00030000
473 #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
474 #define PLLMR0_OPB_PLB_DIV_1 0x00000000
475 #define PLLMR0_OPB_PLB_DIV_2 0x00001000
476 #define PLLMR0_OPB_PLB_DIV_3 0x00002000
477 #define PLLMR0_OPB_PLB_DIV_4 0x00003000
479 #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
480 #define PLLMR0_EXB_PLB_DIV_2 0x00000000
481 #define PLLMR0_EXB_PLB_DIV_3 0x00000100
482 #define PLLMR0_EXB_PLB_DIV_4 0x00000200
483 #define PLLMR0_EXB_PLB_DIV_5 0x00000300
485 #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
486 #define PLLMR0_MAL_PLB_DIV_1 0x00000000
487 #define PLLMR0_MAL_PLB_DIV_2 0x00000010
488 #define PLLMR0_MAL_PLB_DIV_3 0x00000020
489 #define PLLMR0_MAL_PLB_DIV_4 0x00000030
491 #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
492 #define PLLMR0_PCI_PLB_DIV_1 0x00000000
493 #define PLLMR0_PCI_PLB_DIV_2 0x00000001
494 #define PLLMR0_PCI_PLB_DIV_3 0x00000002
495 #define PLLMR0_PCI_PLB_DIV_4 0x00000003
497 #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
498 #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
499 #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
500 #define PLLMR1_FBMUL_DIV_16 0x00000000
501 #define PLLMR1_FBMUL_DIV_1 0x00100000
502 #define PLLMR1_FBMUL_DIV_2 0x00200000
503 #define PLLMR1_FBMUL_DIV_3 0x00300000
504 #define PLLMR1_FBMUL_DIV_4 0x00400000
505 #define PLLMR1_FBMUL_DIV_5 0x00500000
506 #define PLLMR1_FBMUL_DIV_6 0x00600000
507 #define PLLMR1_FBMUL_DIV_7 0x00700000
508 #define PLLMR1_FBMUL_DIV_8 0x00800000
509 #define PLLMR1_FBMUL_DIV_9 0x00900000
510 #define PLLMR1_FBMUL_DIV_10 0x00A00000
511 #define PLLMR1_FBMUL_DIV_11 0x00B00000
512 #define PLLMR1_FBMUL_DIV_12 0x00C00000
513 #define PLLMR1_FBMUL_DIV_13 0x00D00000
514 #define PLLMR1_FBMUL_DIV_14 0x00E00000
515 #define PLLMR1_FBMUL_DIV_15 0x00F00000
517 #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
518 #define PLLMR1_FWDVA_DIV_8 0x00000000
519 #define PLLMR1_FWDVA_DIV_7 0x00010000
520 #define PLLMR1_FWDVA_DIV_6 0x00020000
521 #define PLLMR1_FWDVA_DIV_5 0x00030000
522 #define PLLMR1_FWDVA_DIV_4 0x00040000
523 #define PLLMR1_FWDVA_DIV_3 0x00050000
524 #define PLLMR1_FWDVA_DIV_2 0x00060000
525 #define PLLMR1_FWDVA_DIV_1 0x00070000
526 #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
527 #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
529 /* Defines for CPC0_EPRCSR register */
530 #define CPC0_EPRCSR_E0NFE 0x80000000
531 #define CPC0_EPRCSR_E1NFE 0x40000000
532 #define CPC0_EPRCSR_E1RPP 0x00000080
533 #define CPC0_EPRCSR_E0RPP 0x00000040
534 #define CPC0_EPRCSR_E1ERP 0x00000020
535 #define CPC0_EPRCSR_E0ERP 0x00000010
536 #define CPC0_EPRCSR_E1PCI 0x00000002
537 #define CPC0_EPRCSR_E0PCI 0x00000001
539 /* Defines for CPC0_PCI Register */
540 #define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
541 #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
542 #define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
544 /* Defines for CPC0_BOOR Register */
545 #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
547 /* Defines for CPC0_PLLMR1 Register fields */
548 #define PLL_ACTIVE 0x80000000
549 #define CPC0_PLLMR1_SSCS 0x80000000
550 #define PLL_RESET 0x40000000
551 #define CPC0_PLLMR1_PLLR 0x40000000
552 /* Feedback multiplier */
553 #define PLL_FBKDIV 0x00F00000
554 #define CPC0_PLLMR1_FBDV 0x00F00000
555 #define PLL_FBKDIV_16 0x00000000
556 #define PLL_FBKDIV_1 0x00100000
557 #define PLL_FBKDIV_2 0x00200000
558 #define PLL_FBKDIV_3 0x00300000
559 #define PLL_FBKDIV_4 0x00400000
560 #define PLL_FBKDIV_5 0x00500000
561 #define PLL_FBKDIV_6 0x00600000
562 #define PLL_FBKDIV_7 0x00700000
563 #define PLL_FBKDIV_8 0x00800000
564 #define PLL_FBKDIV_9 0x00900000
565 #define PLL_FBKDIV_10 0x00A00000
566 #define PLL_FBKDIV_11 0x00B00000
567 #define PLL_FBKDIV_12 0x00C00000
568 #define PLL_FBKDIV_13 0x00D00000
569 #define PLL_FBKDIV_14 0x00E00000
570 #define PLL_FBKDIV_15 0x00F00000
571 /* Forward A divisor */
572 #define PLL_FWDDIVA 0x00070000
573 #define CPC0_PLLMR1_FWDVA 0x00070000
574 #define PLL_FWDDIVA_8 0x00000000
575 #define PLL_FWDDIVA_7 0x00010000
576 #define PLL_FWDDIVA_6 0x00020000
577 #define PLL_FWDDIVA_5 0x00030000
578 #define PLL_FWDDIVA_4 0x00040000
579 #define PLL_FWDDIVA_3 0x00050000
580 #define PLL_FWDDIVA_2 0x00060000
581 #define PLL_FWDDIVA_1 0x00070000
582 /* Forward B divisor */
583 #define PLL_FWDDIVB 0x00007000
584 #define CPC0_PLLMR1_FWDVB 0x00007000
585 #define PLL_FWDDIVB_8 0x00000000
586 #define PLL_FWDDIVB_7 0x00001000
587 #define PLL_FWDDIVB_6 0x00002000
588 #define PLL_FWDDIVB_5 0x00003000
589 #define PLL_FWDDIVB_4 0x00004000
590 #define PLL_FWDDIVB_3 0x00005000
591 #define PLL_FWDDIVB_2 0x00006000
592 #define PLL_FWDDIVB_1 0x00007000
594 #define PLL_TUNE_MASK 0x000003FF
595 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
596 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
597 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
598 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
599 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
600 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
601 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
603 /* Defines for CPC0_PLLMR0 Register fields */
605 #define PLL_CPUDIV 0x00300000
606 #define CPC0_PLLMR0_CCDV 0x00300000
607 #define PLL_CPUDIV_1 0x00000000
608 #define PLL_CPUDIV_2 0x00100000
609 #define PLL_CPUDIV_3 0x00200000
610 #define PLL_CPUDIV_4 0x00300000
612 #define PLL_PLBDIV 0x00030000
613 #define CPC0_PLLMR0_CBDV 0x00030000
614 #define PLL_PLBDIV_1 0x00000000
615 #define PLL_PLBDIV_2 0x00010000
616 #define PLL_PLBDIV_3 0x00020000
617 #define PLL_PLBDIV_4 0x00030000
619 #define PLL_OPBDIV 0x00003000
620 #define CPC0_PLLMR0_OPDV 0x00003000
621 #define PLL_OPBDIV_1 0x00000000
622 #define PLL_OPBDIV_2 0x00001000
623 #define PLL_OPBDIV_3 0x00002000
624 #define PLL_OPBDIV_4 0x00003000
626 #define PLL_EXTBUSDIV 0x00000300
627 #define CPC0_PLLMR0_EPDV 0x00000300
628 #define PLL_EXTBUSDIV_2 0x00000000
629 #define PLL_EXTBUSDIV_3 0x00000100
630 #define PLL_EXTBUSDIV_4 0x00000200
631 #define PLL_EXTBUSDIV_5 0x00000300
633 #define PLL_MALDIV 0x00000030
634 #define CPC0_PLLMR0_MPDV 0x00000030
635 #define PLL_MALDIV_1 0x00000000
636 #define PLL_MALDIV_2 0x00000010
637 #define PLL_MALDIV_3 0x00000020
638 #define PLL_MALDIV_4 0x00000030
640 #define PLL_PCIDIV 0x00000003
641 #define CPC0_PLLMR0_PPFD 0x00000003
642 #define PLL_PCIDIV_1 0x00000000
643 #define PLL_PCIDIV_2 0x00000001
644 #define PLL_PCIDIV_3 0x00000002
645 #define PLL_PCIDIV_4 0x00000003
648 *-------------------------------------------------------------------------------
649 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
650 * assuming a 33.3MHz input clock to the 405EP.
651 *-------------------------------------------------------------------------------
653 #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
654 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
655 PLL_MALDIV_1 | PLL_PCIDIV_4)
656 #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
657 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
658 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
660 #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
661 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
662 PLL_MALDIV_1 | PLL_PCIDIV_4)
663 #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
664 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
665 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
666 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
667 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
668 PLL_MALDIV_1 | PLL_PCIDIV_4)
669 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
670 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
671 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
672 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
673 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
674 PLL_MALDIV_1 | PLL_PCIDIV_4)
675 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
676 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
677 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
678 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
679 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
680 PLL_MALDIV_1 | PLL_PCIDIV_2)
681 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
682 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
683 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
684 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
685 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
686 PLL_MALDIV_1 | PLL_PCIDIV_3)
687 #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
688 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
689 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
690 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
691 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
692 PLL_MALDIV_1 | PLL_PCIDIV_1)
693 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
694 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
695 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
698 * PLL Voltage Controlled Oscillator (VCO) definitions
699 * Maximum and minimum values (in MHz) for correct PLL operation.
703 #elif defined(CONFIG_405EZ)
704 #define sdrnand0 0x4000
705 #define sdrultra0 0x4040
706 #define sdrultra1 0x4050
707 #define sdricintstat 0x4510
709 #define SDR_NAND0_NDEN 0x80000000
710 #define SDR_NAND0_NDBTEN 0x40000000
711 #define SDR_NAND0_NDBADR_MASK 0x30000000
712 #define SDR_NAND0_NDBPG_MASK 0x0f000000
713 #define SDR_NAND0_NDAREN 0x00800000
714 #define SDR_NAND0_NDRBEN 0x00400000
716 #define SDR_ULTRA0_NDGPIOBP 0x80000000
717 #define SDR_ULTRA0_CSN_MASK 0x78000000
718 #define SDR_ULTRA0_CSNSEL0 0x40000000
719 #define SDR_ULTRA0_CSNSEL1 0x20000000
720 #define SDR_ULTRA0_CSNSEL2 0x10000000
721 #define SDR_ULTRA0_CSNSEL3 0x08000000
722 #define SDR_ULTRA0_EBCRDYEN 0x04000000
723 #define SDR_ULTRA0_SPISSINEN 0x02000000
724 #define SDR_ULTRA0_NFSRSTEN 0x01000000
726 #define SDR_ULTRA1_LEDNENABLE 0x40000000
728 #define SDR_ICRX_STAT 0x80000000
729 #define SDR_ICTX0_STAT 0x40000000
730 #define SDR_ICTX1_STAT 0x20000000
732 #define SDR_PINSTP 0x40
734 /******************************************************************************
736 ******************************************************************************/
738 #define cprclkupd 0x020 /* CPR_CLKUPD */
739 #define cprpllc 0x040 /* CPR_PLLC */
740 #define cprplld 0x060 /* CPR_PLLD */
741 #define cprprimad 0x080 /* CPR_PRIMAD */
742 #define cprperd0 0x0e0 /* CPR_PERD0 */
743 #define cprperd1 0x0e1 /* CPR_PERD1 */
744 #define cprperc0 0x180 /* CPR_PERC0 */
745 #define cprmisc0 0x181 /* CPR_MISC0 */
746 #define cprmisc1 0x182 /* CPR_MISC1 */
748 #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
749 #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
750 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
752 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
754 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
755 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
756 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
758 #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
759 #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
760 #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
761 #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
763 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
764 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
765 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
766 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
768 #else /* #ifdef CONFIG_405EP */
769 /******************************************************************************
771 ******************************************************************************/
772 #define CNTRL_DCR_BASE 0x0b0
773 #define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
774 #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
775 #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
776 #define reset (CNTRL_DCR_BASE+0x3) /* reset register */
777 #define strap (CNTRL_DCR_BASE+0x4) /* strap register */
779 #define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
780 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
781 #define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
783 /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
784 #define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */
785 #define CPC0_ECR (0xaa) /* edge conditioner register */
787 #define ecr (0xaa) /* edge conditioner register (405gpr) */
789 /* Bit definitions */
790 #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
791 #define PLLMR_FWD_DIV_BYPASS 0xE0000000
792 #define PLLMR_FWD_DIV_3 0xA0000000
793 #define PLLMR_FWD_DIV_4 0x80000000
794 #define PLLMR_FWD_DIV_6 0x40000000
796 #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
797 #define PLLMR_FB_DIV_1 0x02000000
798 #define PLLMR_FB_DIV_2 0x04000000
799 #define PLLMR_FB_DIV_3 0x06000000
800 #define PLLMR_FB_DIV_4 0x08000000
802 #define PLLMR_TUNING_MASK 0x01F80000
804 #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
805 #define PLLMR_CPU_PLB_DIV_1 0x00000000
806 #define PLLMR_CPU_PLB_DIV_2 0x00020000
807 #define PLLMR_CPU_PLB_DIV_3 0x00040000
808 #define PLLMR_CPU_PLB_DIV_4 0x00060000
810 #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
811 #define PLLMR_OPB_PLB_DIV_1 0x00000000
812 #define PLLMR_OPB_PLB_DIV_2 0x00008000
813 #define PLLMR_OPB_PLB_DIV_3 0x00010000
814 #define PLLMR_OPB_PLB_DIV_4 0x00018000
816 #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
817 #define PLLMR_PCI_PLB_DIV_1 0x00000000
818 #define PLLMR_PCI_PLB_DIV_2 0x00002000
819 #define PLLMR_PCI_PLB_DIV_3 0x00004000
820 #define PLLMR_PCI_PLB_DIV_4 0x00006000
822 #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
823 #define PLLMR_EXB_PLB_DIV_2 0x00000000
824 #define PLLMR_EXB_PLB_DIV_3 0x00000800
825 #define PLLMR_EXB_PLB_DIV_4 0x00001000
826 #define PLLMR_EXB_PLB_DIV_5 0x00001800
828 /* definitions for PPC405GPr (new mode strapping) */
829 #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
831 #define PSR_PLL_FWD_MASK 0xC0000000
832 #define PSR_PLL_FDBACK_MASK 0x30000000
833 #define PSR_PLL_TUNING_MASK 0x0E000000
834 #define PSR_PLB_CPU_MASK 0x01800000
835 #define PSR_OPB_PLB_MASK 0x00600000
836 #define PSR_PCI_PLB_MASK 0x00180000
837 #define PSR_EB_PLB_MASK 0x00060000
838 #define PSR_ROM_WIDTH_MASK 0x00018000
839 #define PSR_ROM_LOC 0x00004000
840 #define PSR_PCI_ASYNC_EN 0x00001000
841 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
842 #define PSR_PCI_ARBIT_EN 0x00000400
843 #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
845 #ifndef CONFIG_IOP480
847 * PLL Voltage Controlled Oscillator (VCO) definitions
848 * Maximum and minimum values (in MHz) for correct PLL operation.
852 #endif /* #ifndef CONFIG_IOP480 */
853 #endif /* #ifdef CONFIG_405EP */
855 /******************************************************************************
856 * Memory Access Layer
857 ******************************************************************************/
858 #if defined(CONFIG_405EZ)
859 #define MAL_DCR_BASE 0x380
860 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
861 #define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
862 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
863 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
864 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
865 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
866 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
867 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
868 /* 0x08-0x0F Reserved */
869 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
870 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
871 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
872 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
873 /* 0x14-0x1F Reserved */
874 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
875 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
876 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
877 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
878 #define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
879 #define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
880 #define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
881 #define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
882 #define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
883 #define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
884 #define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
885 #define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
886 #define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
887 #define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
888 #define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
889 #define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
890 #define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
891 #define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
892 #define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
893 #define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
894 #define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
895 #define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
896 #define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
897 #define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
898 #define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
899 #define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
900 #define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
901 #define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
902 #define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
903 #define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
904 #define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
905 #define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
906 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
907 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
908 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
909 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
910 #define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
911 #define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
912 #define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
913 #define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
914 #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
915 #define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
916 #define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
917 #define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
918 #define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
919 #define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
920 #define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
921 #define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
922 #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
923 #define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
924 #define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
925 #define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
926 #define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
927 #define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
928 #define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
929 #define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
930 #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
931 #define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
932 #define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
933 #define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
934 #define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
935 #define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
936 #define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
937 #define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
938 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
939 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
940 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
941 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
942 #define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
943 #define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
944 #define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
945 #define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
946 #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
947 #define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
948 #define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
949 #define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
950 #define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
951 #define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
952 #define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
953 #define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
954 #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
955 #define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
956 #define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
957 #define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
958 #define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
959 #define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
960 #define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
961 #define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
962 #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
963 #define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
964 #define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
965 #define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
966 #define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
967 #define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
968 #define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
969 #define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
971 #else /* !defined(CONFIG_405EZ) */
973 #define MAL_DCR_BASE 0x180
974 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
975 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
976 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
977 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
978 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
979 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
980 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
981 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
982 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
983 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
984 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
985 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
986 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
987 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
988 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
989 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
990 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
991 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
992 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
993 #endif /* defined(CONFIG_405EZ) */
995 /*-----------------------------------------------------------------------------
996 | IIC Register Offsets
997 '----------------------------------------------------------------------------*/
998 #define IICMDBUF 0x00
999 #define IICSDBUF 0x02
1000 #define IICLMADR 0x04
1001 #define IICHMADR 0x05
1002 #define IICCNTL 0x06
1003 #define IICMDCNTL 0x07
1005 #define IICEXTSTS 0x09
1006 #define IICLSADR 0x0A
1007 #define IICHSADR 0x0B
1008 #define IICCLKDIV 0x0C
1009 #define IICINTRMSK 0x0D
1010 #define IICXFRCNT 0x0E
1011 #define IICXTCNTLSS 0x0F
1012 #define IICDIRECTCNTL 0x10
1014 /*-----------------------------------------------------------------------------
1015 | UART Register Offsets
1016 '----------------------------------------------------------------------------*/
1017 #define DATA_REG 0x00
1020 #define INT_ENABLE 0x01
1021 #define FIFO_CONTROL 0x02
1022 #define LINE_CONTROL 0x03
1023 #define MODEM_CONTROL 0x04
1024 #define LINE_STATUS 0x05
1025 #define MODEM_STATUS 0x06
1026 #define SCRATCH 0x07
1028 /******************************************************************************
1030 ******************************************************************************/
1031 #if defined(CONFIG_405EZ)
1032 #define OCM_DCR_BASE 0x020
1033 #define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
1034 #define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
1035 #define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
1036 #define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
1037 #define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
1038 #define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
1039 #define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
1040 #define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
1041 #define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
1042 #define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
1043 #define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
1044 #define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
1045 #define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
1046 #define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
1047 #define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
1049 #define OCM_DCR_BASE 0x018
1050 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
1051 #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
1052 #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
1053 #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
1054 #endif /* CONFIG_405EZ */
1056 /******************************************************************************
1057 * GPIO macro register defines
1058 ******************************************************************************/
1059 #if defined(CONFIG_405EZ)
1060 /* Only the 405EZ has 2 GPIOs */
1061 #define GPIO_BASE 0xEF600700
1062 #define GPIO0_OR (GPIO_BASE+0x0)
1063 #define GPIO0_TCR (GPIO_BASE+0x4)
1064 #define GPIO0_OSRL (GPIO_BASE+0x8)
1065 #define GPIO0_OSRH (GPIO_BASE+0xC)
1066 #define GPIO0_TSRL (GPIO_BASE+0x10)
1067 #define GPIO0_TSRH (GPIO_BASE+0x14)
1068 #define GPIO0_ODR (GPIO_BASE+0x18)
1069 #define GPIO0_IR (GPIO_BASE+0x1C)
1070 #define GPIO0_RR1 (GPIO_BASE+0x20)
1071 #define GPIO0_RR2 (GPIO_BASE+0x24)
1072 #define GPIO0_RR3 (GPIO_BASE+0x28)
1073 #define GPIO0_ISR1L (GPIO_BASE+0x30)
1074 #define GPIO0_ISR1H (GPIO_BASE+0x34)
1075 #define GPIO0_ISR2L (GPIO_BASE+0x38)
1076 #define GPIO0_ISR2H (GPIO_BASE+0x3C)
1077 #define GPIO0_ISR3L (GPIO_BASE+0x40)
1078 #define GPIO0_ISR3H (GPIO_BASE+0x44)
1080 #define GPIO1_BASE 0xEF600800
1081 #define GPIO1_OR (GPIO1_BASE+0x0)
1082 #define GPIO1_TCR (GPIO1_BASE+0x4)
1083 #define GPIO1_OSRL (GPIO1_BASE+0x8)
1084 #define GPIO1_OSRH (GPIO1_BASE+0xC)
1085 #define GPIO1_TSRL (GPIO1_BASE+0x10)
1086 #define GPIO1_TSRH (GPIO1_BASE+0x14)
1087 #define GPIO1_ODR (GPIO1_BASE+0x18)
1088 #define GPIO1_IR (GPIO1_BASE+0x1C)
1089 #define GPIO1_RR1 (GPIO1_BASE+0x20)
1090 #define GPIO1_RR2 (GPIO1_BASE+0x24)
1091 #define GPIO1_RR3 (GPIO1_BASE+0x28)
1092 #define GPIO1_ISR1L (GPIO1_BASE+0x30)
1093 #define GPIO1_ISR1H (GPIO1_BASE+0x34)
1094 #define GPIO1_ISR2L (GPIO1_BASE+0x38)
1095 #define GPIO1_ISR2H (GPIO1_BASE+0x3C)
1096 #define GPIO1_ISR3L (GPIO1_BASE+0x40)
1097 #define GPIO1_ISR3H (GPIO1_BASE+0x44)
1099 #elif defined(CONFIG_405EX)
1100 #define GPIO_BASE 0xEF600800
1101 #define GPIO0_OR (GPIO_BASE+0x0)
1102 #define GPIO0_TCR (GPIO_BASE+0x4)
1103 #define GPIO0_OSRL (GPIO_BASE+0x8)
1104 #define GPIO0_OSRH (GPIO_BASE+0xC)
1105 #define GPIO0_TSRL (GPIO_BASE+0x10)
1106 #define GPIO0_TSRH (GPIO_BASE+0x14)
1107 #define GPIO0_ODR (GPIO_BASE+0x18)
1108 #define GPIO0_IR (GPIO_BASE+0x1C)
1109 #define GPIO0_RR1 (GPIO_BASE+0x20)
1110 #define GPIO0_RR2 (GPIO_BASE+0x24)
1111 #define GPIO0_ISR1L (GPIO_BASE+0x30)
1112 #define GPIO0_ISR1H (GPIO_BASE+0x34)
1113 #define GPIO0_ISR2L (GPIO_BASE+0x38)
1114 #define GPIO0_ISR2H (GPIO_BASE+0x3C)
1115 #define GPIO0_ISR3L (GPIO_BASE+0x40)
1116 #define GPIO0_ISR3H (GPIO_BASE+0x44)
1120 #define GPIO_BASE 0xEF600700
1121 #define GPIO0_OR (GPIO_BASE+0x0)
1122 #define GPIO0_TCR (GPIO_BASE+0x4)
1123 #define GPIO0_OSRH (GPIO_BASE+0x8)
1124 #define GPIO0_OSRL (GPIO_BASE+0xC)
1125 #define GPIO0_TSRH (GPIO_BASE+0x10)
1126 #define GPIO0_TSRL (GPIO_BASE+0x14)
1127 #define GPIO0_ODR (GPIO_BASE+0x18)
1128 #define GPIO0_IR (GPIO_BASE+0x1C)
1129 #define GPIO0_RR1 (GPIO_BASE+0x20)
1130 #define GPIO0_RR2 (GPIO_BASE+0x24)
1131 #define GPIO0_ISR1H (GPIO_BASE+0x30)
1132 #define GPIO0_ISR1L (GPIO_BASE+0x34)
1133 #define GPIO0_ISR2H (GPIO_BASE+0x38)
1134 #define GPIO0_ISR2L (GPIO_BASE+0x3C)
1136 #endif /* CONFIG_405EZ */
1138 #define GPIO0_BASE GPIO_BASE
1140 #if defined(CONFIG_405EX)
1141 #define SDR0_SRST 0x0200
1144 * Software Reset Register
1146 #define SDR0_SRST_BGO PPC_REG_VAL(0, 1)
1147 #define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1)
1148 #define SDR0_SRST_EBC PPC_REG_VAL(2, 1)
1149 #define SDR0_SRST_OPB PPC_REG_VAL(3, 1)
1150 #define SDR0_SRST_UART0 PPC_REG_VAL(4, 1)
1151 #define SDR0_SRST_UART1 PPC_REG_VAL(5, 1)
1152 #define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1)
1153 #define SDR0_SRST_BGI PPC_REG_VAL(7, 1)
1154 #define SDR0_SRST_GPIO PPC_REG_VAL(8, 1)
1155 #define SDR0_SRST_GPT PPC_REG_VAL(9, 1)
1156 #define SDR0_SRST_DMC PPC_REG_VAL(10, 1)
1157 #define SDR0_SRST_RGMII PPC_REG_VAL(11, 1)
1158 #define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1)
1159 #define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1)
1160 #define SDR0_SRST_CPM PPC_REG_VAL(14, 1)
1161 #define SDR0_SRST_EPLL PPC_REG_VAL(15, 1)
1162 #define SDR0_SRST_UIC PPC_REG_VAL(16, 1)
1163 #define SDR0_SRST_UPRST PPC_REG_VAL(17, 1)
1164 #define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1)
1165 #define SDR0_SRST_SCP PPC_REG_VAL(19, 1)
1166 #define SDR0_SRST_UHRST PPC_REG_VAL(20, 1)
1167 #define SDR0_SRST_DMA PPC_REG_VAL(21, 1)
1168 #define SDR0_SRST_DMAC PPC_REG_VAL(22, 1)
1169 #define SDR0_SRST_MAL PPC_REG_VAL(23, 1)
1170 #define SDR0_SRST_EBM PPC_REG_VAL(24, 1)
1171 #define SDR0_SRST_GPTR PPC_REG_VAL(25, 1)
1172 #define SDR0_SRST_PE0 PPC_REG_VAL(26, 1)
1173 #define SDR0_SRST_PE1 PPC_REG_VAL(27, 1)
1174 #define SDR0_SRST_CRYP PPC_REG_VAL(28, 1)
1175 #define SDR0_SRST_PKP PPC_REG_VAL(29, 1)
1176 #define SDR0_SRST_AHB PPC_REG_VAL(30, 1)
1177 #define SDR0_SRST_NDFC PPC_REG_VAL(31, 1)
1179 #define sdr_uart0 0x0120 /* UART0 Config */
1180 #define sdr_uart1 0x0121 /* UART1 Config */
1181 #define sdr_mfr 0x4300 /* SDR0_MFR reg */
1183 /* Defines for CPC0_EPRCSR register */
1184 #define CPC0_EPRCSR_E0NFE 0x80000000
1185 #define CPC0_EPRCSR_E1NFE 0x40000000
1186 #define CPC0_EPRCSR_E1RPP 0x00000080
1187 #define CPC0_EPRCSR_E0RPP 0x00000040
1188 #define CPC0_EPRCSR_E1ERP 0x00000020
1189 #define CPC0_EPRCSR_E0ERP 0x00000010
1190 #define CPC0_EPRCSR_E1PCI 0x00000002
1191 #define CPC0_EPRCSR_E0PCI 0x00000001
1193 #define cpr0_clkupd 0x020
1194 #define cpr0_pllc 0x040
1195 #define cpr0_plld 0x060
1196 #define cpr0_cpud 0x080
1197 #define cpr0_plbd 0x0a0
1198 #define cpr0_opbd 0x0c0
1199 #define cpr0_perd 0x0e0
1200 #define cpr0_ahbd 0x100
1201 #define cpr0_icfg 0x140
1203 #define SDR_PINSTP 0x0040
1204 #define sdr_sdcs 0x0060
1206 #define SDR0_SDCS_SDD (0x80000000 >> 31)
1208 /* CUST0 Customer Configuration Register0 */
1209 #define SDR0_CUST0 0x4000
1210 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
1211 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
1212 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
1213 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
1215 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
1216 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
1217 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
1219 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
1220 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
1221 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
1223 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
1224 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
1225 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1227 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
1228 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
1229 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1231 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
1232 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
1233 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
1235 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
1236 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
1237 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
1239 #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
1240 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
1241 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
1243 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
1244 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
1245 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
1246 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
1247 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
1248 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
1249 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
1251 #define SDR0_PFC0 0x4100
1252 #define SDR0_PFC1 0x4101
1253 #define SDR0_PFC1_U1ME 0x02000000
1254 #define SDR0_PFC1_U0ME 0x00080000
1255 #define SDR0_PFC1_U0IM 0x00040000
1256 #define SDR0_PFC1_SIS 0x00020000
1257 #define SDR0_PFC1_DMAAEN 0x00010000
1258 #define SDR0_PFC1_DMADEN 0x00008000
1259 #define SDR0_PFC1_USBEN 0x00004000
1260 #define SDR0_PFC1_AHBSWAP 0x00000020
1261 #define SDR0_PFC1_USBBIGEN 0x00000010
1262 #define SDR0_PFC1_GPT_FREQ 0x0000000f
1265 /* General Purpose Timer (GPT) Register Offsets */
1266 #define GPT0_TBC 0x00000000
1267 #define GPT0_IM 0x00000018
1268 #define GPT0_ISS 0x0000001C
1269 #define GPT0_ISC 0x00000020
1270 #define GPT0_IE 0x00000024
1271 #define GPT0_COMP0 0x00000080
1272 #define GPT0_COMP1 0x00000084
1273 #define GPT0_COMP2 0x00000088
1274 #define GPT0_COMP3 0x0000008C
1275 #define GPT0_COMP4 0x00000090
1276 #define GPT0_COMP5 0x00000094
1277 #define GPT0_COMP6 0x00000098
1278 #define GPT0_MASK0 0x000000C0
1279 #define GPT0_MASK1 0x000000C4
1280 #define GPT0_MASK2 0x000000C8
1281 #define GPT0_MASK3 0x000000CC
1282 #define GPT0_MASK4 0x000000D0
1283 #define GPT0_MASK5 0x000000D4
1284 #define GPT0_MASK6 0x000000D8
1285 #define GPT0_DCT0 0x00000110
1286 #define GPT0_DCIS 0x0000011C
1288 #endif /* __PPC405_H__ */
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