1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 /*--------------------------------------------------------------------- */
26 /* Special Purpose Registers */
27 /*--------------------------------------------------------------------- */
28 #define dec 0x016 /* decrementer */
29 #define srr0 0x01a /* save/restore register 0 */
30 #define srr1 0x01b /* save/restore register 1 */
31 #define pid 0x030 /* process id */
32 #define decar 0x036 /* decrementer auto-reload */
33 #define csrr0 0x03a /* critical save/restore register 0 */
34 #define csrr1 0x03b /* critical save/restore register 1 */
35 #define dear 0x03d /* data exception address register */
36 #define esr 0x03e /* exception syndrome register */
37 #define ivpr 0x03f /* interrupt prefix register */
38 #define usprg0 0x100 /* user special purpose register general 0 */
39 #define usprg1 0x110 /* user special purpose register general 1 */
40 #define sprg1 0x111 /* special purpose register general 1 */
41 #define sprg2 0x112 /* special purpose register general 2 */
42 #define sprg3 0x113 /* special purpose register general 3 */
43 #define sprg4 0x114 /* special purpose register general 4 */
44 #define sprg5 0x115 /* special purpose register general 5 */
45 #define sprg6 0x116 /* special purpose register general 6 */
46 #define sprg7 0x117 /* special purpose register general 7 */
47 #define tbl 0x11c /* time base lower (supervisor)*/
48 #define tbu 0x11d /* time base upper (supervisor)*/
49 #define pir 0x11e /* processor id register */
50 /*#define pvr 0x11f processor version register */
51 #define dbsr 0x130 /* debug status register */
52 #define dbcr0 0x134 /* debug control register 0 */
53 #define dbcr1 0x135 /* debug control register 1 */
54 #define dbcr2 0x136 /* debug control register 2 */
55 #define iac1 0x138 /* instruction address compare 1 */
56 #define iac2 0x139 /* instruction address compare 2 */
57 #define iac3 0x13a /* instruction address compare 3 */
58 #define iac4 0x13b /* instruction address compare 4 */
59 #define dac1 0x13c /* data address compare 1 */
60 #define dac2 0x13d /* data address compare 2 */
61 #define dvc1 0x13e /* data value compare 1 */
62 #define dvc2 0x13f /* data value compare 2 */
63 #define tsr 0x150 /* timer status register */
64 #define tcr 0x154 /* timer control register */
65 #define ivor0 0x190 /* interrupt vector offset register 0 */
66 #define ivor1 0x191 /* interrupt vector offset register 1 */
67 #define ivor2 0x192 /* interrupt vector offset register 2 */
68 #define ivor3 0x193 /* interrupt vector offset register 3 */
69 #define ivor4 0x194 /* interrupt vector offset register 4 */
70 #define ivor5 0x195 /* interrupt vector offset register 5 */
71 #define ivor6 0x196 /* interrupt vector offset register 6 */
72 #define ivor7 0x197 /* interrupt vector offset register 7 */
73 #define ivor8 0x198 /* interrupt vector offset register 8 */
74 #define ivor9 0x199 /* interrupt vector offset register 9 */
75 #define ivor10 0x19a /* interrupt vector offset register 10 */
76 #define ivor11 0x19b /* interrupt vector offset register 11 */
77 #define ivor12 0x19c /* interrupt vector offset register 12 */
78 #define ivor13 0x19d /* interrupt vector offset register 13 */
79 #define ivor14 0x19e /* interrupt vector offset register 14 */
80 #define ivor15 0x19f /* interrupt vector offset register 15 */
81 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
82 #define mcsrr0 0x23a /* machine check save/restore register 0 */
83 #define mcsrr1 0x23b /* mahcine check save/restore register 1 */
84 #define mcsr 0x23c /* machine check status register */
86 #define inv0 0x370 /* instruction cache normal victim 0 */
87 #define inv1 0x371 /* instruction cache normal victim 1 */
88 #define inv2 0x372 /* instruction cache normal victim 2 */
89 #define inv3 0x373 /* instruction cache normal victim 3 */
90 #define itv0 0x374 /* instruction cache transient victim 0 */
91 #define itv1 0x375 /* instruction cache transient victim 1 */
92 #define itv2 0x376 /* instruction cache transient victim 2 */
93 #define itv3 0x377 /* instruction cache transient victim 3 */
94 #define dnv0 0x390 /* data cache normal victim 0 */
95 #define dnv1 0x391 /* data cache normal victim 1 */
96 #define dnv2 0x392 /* data cache normal victim 2 */
97 #define dnv3 0x393 /* data cache normal victim 3 */
98 #define dtv0 0x394 /* data cache transient victim 0 */
99 #define dtv1 0x395 /* data cache transient victim 1 */
100 #define dtv2 0x396 /* data cache transient victim 2 */
101 #define dtv3 0x397 /* data cache transient victim 3 */
102 #define dvlim 0x398 /* data cache victim limit */
103 #define ivlim 0x399 /* instruction cache victim limit */
104 #define rstcfg 0x39b /* reset configuration */
105 #define dcdbtrl 0x39c /* data cache debug tag register low */
106 #define dcdbtrh 0x39d /* data cache debug tag register high */
107 #define icdbtrl 0x39e /* instruction cache debug tag register low */
108 #define icdbtrh 0x39f /* instruction cache debug tag register high */
109 #define mmucr 0x3b2 /* mmu control register */
110 #define ccr0 0x3b3 /* core configuration register 0 */
111 #define ccr1 0x378 /* core configuration for 440x5 only */
112 #define icdbdr 0x3d3 /* instruction cache debug data register */
113 #define dbdr 0x3f3 /* debug data register */
115 /******************************************************************************
117 ******************************************************************************/
119 /*-----------------------------------------------------------------------------
120 | Clocking Controller
121 +----------------------------------------------------------------------------*/
122 #define CLOCKING_DCR_BASE 0x0c
123 #define clkcfga (CLOCKING_DCR_BASE+0x0)
124 #define clkcfgd (CLOCKING_DCR_BASE+0x1)
126 /* values for clkcfga register - indirect addressing of these regs */
127 #define clk_clkukpd 0x0020
128 #define clk_pllc 0x0040
129 #define clk_plld 0x0060
130 #define clk_primad 0x0080
131 #define clk_primbd 0x00a0
132 #define clk_opbd 0x00c0
133 #define clk_perd 0x00e0
134 #define clk_mald 0x0100
135 #define clk_spcid 0x0120
136 #define clk_icfg 0x0140
138 /* 440gx sdr register definations */
139 #define SDR_DCR_BASE 0x0e
140 #define sdrcfga (SDR_DCR_BASE+0x0)
141 #define sdrcfgd (SDR_DCR_BASE+0x1)
142 #define sdr_sdstp0 0x0020 /* */
143 #define sdr_sdstp1 0x0021 /* */
144 #define sdr_pinstp 0x0040
145 #define sdr_sdcs 0x0060
146 #define sdr_ecid0 0x0080
147 #define sdr_ecid1 0x0081
148 #define sdr_ecid2 0x0082
149 #define sdr_jtag 0x00c0
150 #define sdr_ddrdl 0x00e0
151 #define sdr_ebc 0x0100
152 #define sdr_uart0 0x0120 /* UART0 Config */
153 #define sdr_uart1 0x0121 /* UART1 Config */
154 #define sdr_uart2 0x0122 /* UART2 Config */
155 #define sdr_uart3 0x0123 /* UART3 Config */
156 #define sdr_cp440 0x0180
157 #define sdr_xcr 0x01c0
158 #define sdr_xpllc 0x01c1
159 #define sdr_xplld 0x01c2
160 #define sdr_srst 0x0200
161 #define sdr_slpipe 0x0220
162 #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
163 #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
164 #define sdr_mirq0 0x0260
165 #define sdr_mirq1 0x0261
166 #define sdr_maltbl 0x0280
167 #define sdr_malrbl 0x02a0
168 #define sdr_maltbs 0x02c0
169 #define sdr_malrbs 0x02e0
170 #define sdr_pci0 0x0300
171 #define sdr_usb0 0x0320
172 #define sdr_cust0 0x4000
173 #define sdr_sdstp2 0x4001
174 #define sdr_cust1 0x4002
175 #define sdr_sdstp3 0x4003
176 #define sdr_pfc0 0x4100 /* Pin Function 0 */
177 #define sdr_pfc1 0x4101 /* Pin Function 1 */
178 #define sdr_plbtr 0x4200
179 #define sdr_mfr 0x4300 /* SDR0_MFR reg */
181 /*-----------------------------------------------------------------------------
183 +----------------------------------------------------------------------------*/
184 #define SDRAM_DCR_BASE 0x10
185 #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
186 #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
188 /* values for memcfga register - indirect addressing of these regs */
189 #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
190 #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
191 #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
192 #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
193 #define mem_bear 0x0010 /* bus error address reg */
194 #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
195 #define mem_mirq_set 0x0012 /* bus master interrupt (set) */
196 #define mem_slio 0x0018 /* ddr sdram slave interface options */
197 #define mem_cfg0 0x0020 /* ddr sdram options 0 */
198 #define mem_cfg1 0x0021 /* ddr sdram options 1 */
199 #define mem_devopt 0x0022 /* ddr sdram device options */
200 #define mem_mcsts 0x0024 /* memory controller status */
201 #define mem_rtr 0x0030 /* refresh timer register */
202 #define mem_pmit 0x0034 /* power management idle timer */
203 #define mem_uabba 0x0038 /* plb UABus base address */
204 #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
205 #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
206 #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
207 #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
208 #define mem_tr0 0x0080 /* sdram timing register 0 */
209 #define mem_tr1 0x0081 /* sdram timing register 1 */
210 #define mem_clktr 0x0082 /* ddr clock timing register */
211 #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
212 #define mem_dlycal 0x0084 /* delay line calibration register */
213 #define mem_eccesr 0x0098 /* ECC error status */
215 /*-----------------------------------------------------------------------------
216 | External Bus Controller
217 +----------------------------------------------------------------------------*/
218 #define EBC_DCR_BASE 0x12
219 #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
220 #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
221 /* values for ebccfga register - indirect addressing of these regs */
222 #define pb0cr 0x00 /* periph bank 0 config reg */
223 #define pb1cr 0x01 /* periph bank 1 config reg */
224 #define pb2cr 0x02 /* periph bank 2 config reg */
225 #define pb3cr 0x03 /* periph bank 3 config reg */
226 #define pb4cr 0x04 /* periph bank 4 config reg */
227 #define pb5cr 0x05 /* periph bank 5 config reg */
228 #define pb6cr 0x06 /* periph bank 6 config reg */
229 #define pb7cr 0x07 /* periph bank 7 config reg */
230 #define pb0ap 0x10 /* periph bank 0 access parameters */
231 #define pb1ap 0x11 /* periph bank 1 access parameters */
232 #define pb2ap 0x12 /* periph bank 2 access parameters */
233 #define pb3ap 0x13 /* periph bank 3 access parameters */
234 #define pb4ap 0x14 /* periph bank 4 access parameters */
235 #define pb5ap 0x15 /* periph bank 5 access parameters */
236 #define pb6ap 0x16 /* periph bank 6 access parameters */
237 #define pb7ap 0x17 /* periph bank 7 access parameters */
238 #define pbear 0x20 /* periph bus error addr reg */
239 #define pbesr 0x21 /* periph bus error status reg */
240 #define xbcfg 0x23 /* external bus configuration reg */
241 #define xbcid 0x24 /* external bus core id reg */
243 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
245 /* PLB4 to PLB3 Bridge OUT */
246 #define P4P3_DCR_BASE 0x020
247 #define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
248 #define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
249 #define p4p3_eadr (P4P3_DCR_BASE+0x2)
250 #define p4p3_euadr (P4P3_DCR_BASE+0x3)
251 #define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
252 #define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
253 #define p4p3_confg (P4P3_DCR_BASE+0x6)
254 #define p4p3_pic (P4P3_DCR_BASE+0x7)
255 #define p4p3_peir (P4P3_DCR_BASE+0x8)
256 #define p4p3_rev (P4P3_DCR_BASE+0xA)
258 /* PLB3 to PLB4 Bridge IN */
259 #define P3P4_DCR_BASE 0x030
260 #define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
261 #define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
262 #define p3p4_eadr (P3P4_DCR_BASE+0x2)
263 #define p3p4_euadr (P3P4_DCR_BASE+0x3)
264 #define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
265 #define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
266 #define p3p4_confg (P3P4_DCR_BASE+0x6)
267 #define p3p4_pic (P3P4_DCR_BASE+0x7)
268 #define p3p4_peir (P3P4_DCR_BASE+0x8)
269 #define p3p4_rev (P3P4_DCR_BASE+0xA)
272 #define PLB3_DCR_BASE 0x070
273 #define plb3_revid (PLB3_DCR_BASE+0x2)
274 #define plb3_besr (PLB3_DCR_BASE+0x3)
275 #define plb3_bear (PLB3_DCR_BASE+0x6)
276 #define plb3_acr (PLB3_DCR_BASE+0x7)
278 /* PLB4 Arbiter - PowerPC440EP Pass1 */
279 #define PLB4_DCR_BASE 0x080
280 #define plb4_revid (PLB4_DCR_BASE+0x2)
281 #define plb4_acr (PLB4_DCR_BASE+0x3)
282 #define plb4_besr (PLB4_DCR_BASE+0x4)
283 #define plb4_bearl (PLB4_DCR_BASE+0x6)
284 #define plb4_bearh (PLB4_DCR_BASE+0x7)
286 /* Nebula PLB4 Arbiter - PowerPC440EP */
287 #define PLB_ARBITER_BASE 0x80
289 #define plb0_revid (PLB_ARBITER_BASE+ 0x00)
290 #define plb0_acr (PLB_ARBITER_BASE+ 0x01)
291 #define plb0_acr_ppm_mask 0xF0000000
292 #define plb0_acr_ppm_fixed 0x00000000
293 #define plb0_acr_ppm_fair 0xD0000000
294 #define plb0_acr_hbu_mask 0x08000000
295 #define plb0_acr_hbu_disabled 0x00000000
296 #define plb0_acr_hbu_enabled 0x08000000
297 #define plb0_acr_rdp_mask 0x06000000
298 #define plb0_acr_rdp_disabled 0x00000000
299 #define plb0_acr_rdp_2deep 0x02000000
300 #define plb0_acr_rdp_3deep 0x04000000
301 #define plb0_acr_rdp_4deep 0x06000000
302 #define plb0_acr_wrp_mask 0x01000000
303 #define plb0_acr_wrp_disabled 0x00000000
304 #define plb0_acr_wrp_2deep 0x01000000
306 #define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
307 #define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
308 #define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
309 #define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
310 #define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
312 #define plb1_acr (PLB_ARBITER_BASE+ 0x09)
313 #define plb1_acr_ppm_mask 0xF0000000
314 #define plb1_acr_ppm_fixed 0x00000000
315 #define plb1_acr_ppm_fair 0xD0000000
316 #define plb1_acr_hbu_mask 0x08000000
317 #define plb1_acr_hbu_disabled 0x00000000
318 #define plb1_acr_hbu_enabled 0x08000000
319 #define plb1_acr_rdp_mask 0x06000000
320 #define plb1_acr_rdp_disabled 0x00000000
321 #define plb1_acr_rdp_2deep 0x02000000
322 #define plb1_acr_rdp_3deep 0x04000000
323 #define plb1_acr_rdp_4deep 0x06000000
324 #define plb1_acr_wrp_mask 0x01000000
325 #define plb1_acr_wrp_disabled 0x00000000
326 #define plb1_acr_wrp_2deep 0x01000000
328 #define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
329 #define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
330 #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
331 #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
333 /* Pin Function Control Register 1 */
334 #define SDR0_PFC1 0x4101
335 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
336 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
337 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
338 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
339 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
340 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
341 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
342 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
343 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
344 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
345 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
346 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
347 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
348 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
349 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
350 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
351 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
352 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
353 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
354 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
355 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
356 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
357 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
358 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
360 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
361 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
362 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
363 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
365 /* USB Control Register */
366 #define SDR0_USB0 0x0320
367 #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
368 #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
369 #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
370 #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
371 #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
372 #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
374 /* CUST0 Customer Configuration Register0 */
375 #define SDR0_CUST0 0x4000
376 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
377 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
378 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
379 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
381 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
382 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
383 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
385 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
386 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
387 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
389 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
390 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
391 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
393 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
394 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
395 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
397 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
398 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
399 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
401 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
402 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
403 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
405 #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
406 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
407 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
409 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
410 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
411 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
412 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
413 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
414 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
415 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
417 /* CUST1 Customer Configuration Register1 */
418 #define SDR0_CUST1 0x4002
419 #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
420 #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
421 #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
423 /* Pin Function Control Register 0 */
424 #define SDR0_PFC0 0x4100
425 #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
426 #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
427 #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
428 #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
429 #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
431 /* Pin Function Control Register 1 */
432 #define SDR0_PFC1 0x4101
433 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
434 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
435 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
436 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
437 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
438 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
439 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
440 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
441 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
442 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
443 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
444 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
445 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
446 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
447 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
448 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
449 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
450 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
451 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
452 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
453 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
454 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
455 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
456 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
458 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
459 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
460 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
461 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
463 /* Miscealleneaous Function Reg. */
464 #define SDR0_MFR 0x4300
465 #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
466 #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
467 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
468 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
469 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
470 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
471 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
472 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
473 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
474 #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
475 #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
477 #define SDR0_MFR_ERRATA3_EN0 0x00800000
478 #define SDR0_MFR_ERRATA3_EN1 0x00400000
479 #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
480 #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
481 #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
482 #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
483 #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
487 /*-----------------------------------------------------------------------------
489 +----------------------------------------------------------------------------*/
490 #define ISRAM0_DCR_BASE 0x020
491 #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
492 #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
493 #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
494 #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
495 #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
496 #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
497 #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
498 #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
499 #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
500 #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
501 #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
503 /*-----------------------------------------------------------------------------
505 +----------------------------------------------------------------------------*/
506 #if defined (CONFIG_440GX) || defined(CONFIG_440SP)
507 #define L2_CACHE_BASE 0x030
508 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
509 #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
510 #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
511 #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
512 #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
513 #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
514 #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
515 #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
517 #endif /* CONFIG_440GX */
518 #endif /* !CONFIG_440EP !CONFIG_440GR*/
520 /*-----------------------------------------------------------------------------
522 +----------------------------------------------------------------------------*/
523 /* TODO: as needed */
525 /*-----------------------------------------------------------------------------
526 | Clocking, Power Management and Chip Control
527 +----------------------------------------------------------------------------*/
528 #define CNTRL_DCR_BASE 0x0b0
529 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
530 #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
531 #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
532 #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
534 #define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
535 #define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
536 #define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
539 #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
540 #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
541 #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
542 #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
544 #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
545 #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
546 #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
547 #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
549 #define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
551 #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
552 #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
554 /*-----------------------------------------------------------------------------
555 | Universal interrupt controller
556 +----------------------------------------------------------------------------*/
557 #define UIC0_DCR_BASE 0xc0
558 #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
559 #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
560 #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
561 #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
562 #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
563 #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
564 #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
565 #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
567 #define UIC1_DCR_BASE 0xd0
568 #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
569 #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
570 #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
571 #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
572 #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
573 #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
574 #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
575 #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
577 #if defined(CONFIG_440GX)
578 #define UIC2_DCR_BASE 0x210
579 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
580 #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
581 #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
582 #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
583 #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
584 #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
585 #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
586 #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
589 #define UIC_DCR_BASE 0x200
590 #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
591 #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
592 #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
593 #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
594 #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
595 #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
596 #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
597 #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
598 #endif /* CONFIG_440GX */
600 /* The following is for compatibility with 405 code */
606 #define uicmsr uic0msr
608 #define uicvcr uic0vcr
610 /*-----------------------------------------------------------------------------
612 +----------------------------------------------------------------------------*/
613 #define DMA_DCR_BASE 0x100
614 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
615 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
616 #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
617 #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
618 #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
619 #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
620 #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
621 #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
622 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
623 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
624 #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
625 #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
626 #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
627 #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
628 #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
629 #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
630 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
631 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
632 #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
633 #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
634 #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
635 #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
636 #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
637 #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
638 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
639 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
640 #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
641 #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
642 #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
643 #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
644 #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
645 #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
646 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
647 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
648 #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
649 #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
651 /*-----------------------------------------------------------------------------
652 | Memory Access Layer
653 +----------------------------------------------------------------------------*/
654 #define MAL_DCR_BASE 0x180
655 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
656 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
657 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
658 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
659 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
660 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
661 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
662 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
663 #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
664 #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
665 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
666 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
667 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
668 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
669 #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
670 #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
671 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
672 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
673 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
674 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
675 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
676 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
677 #if defined(CONFIG_440GX)
678 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
679 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
680 #endif /* CONFIG_440GX */
681 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
682 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
683 #if defined(CONFIG_440GX)
684 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
685 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
686 #endif /* CONFIG_440GX */
689 /*---------------------------------------------------------------------------+
690 | Universal interrupt controller 0 interrupts (UIC0)
691 +---------------------------------------------------------------------------*/
692 #if defined(CONFIG_440SP)
693 #define UIC_U0 0x80000000 /* UART 0 */
694 #define UIC_U1 0x40000000 /* UART 1 */
695 #define UIC_IIC0 0x20000000 /* IIC */
696 #define UIC_IIC1 0x10000000 /* IIC */
697 #define UIC_PIM 0x08000000 /* PCI0 inbound message */
698 #define UIC_PCRW 0x04000000 /* PCI0 command write register */
699 #define UIC_PPM 0x02000000 /* PCI0 power management */
700 #define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
701 #define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
702 #define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
703 #define UIC_P1CRW 0x00200000 /* PCI1 command write register */
704 #define UIC_P1PM 0x00100000 /* PCI1 power management */
705 #define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
706 #define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
707 #define UIC_P2IM 0x00020000 /* PCI2 inbound message */
708 #define UIC_P2CRW 0x00010000 /* PCI2 command register write */
709 #define UIC_P2PM 0x00008000 /* PCI2 power management */
710 #define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
711 #define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
712 #define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
713 #define UIC_D0CSF 0x00000800 /* DMA0 command status */
714 #define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
715 #define UIC_D1CSF 0x00000200 /* DMA1 command status */
716 #define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
717 #define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
718 #define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
719 #define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
720 #define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
721 #define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
722 #define UIC_GPTCT 0x00000004 /* GPT count timer */
723 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
724 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
725 #else /* CONFIG_440SP */
726 #define UIC_U0 0x80000000 /* UART 0 */
727 #define UIC_U1 0x40000000 /* UART 1 */
728 #define UIC_IIC0 0x20000000 /* IIC */
729 #define UIC_IIC1 0x10000000 /* IIC */
730 #define UIC_PIM 0x08000000 /* PCI inbound message */
731 #define UIC_PCRW 0x04000000 /* PCI command register write */
732 #define UIC_PPM 0x02000000 /* PCI power management */
733 #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
734 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
735 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
736 #define UIC_MTE 0x00200000 /* MAL TXEOB */
737 #define UIC_MRE 0x00100000 /* MAL RXEOB */
738 #define UIC_D0 0x00080000 /* DMA channel 0 */
739 #define UIC_D1 0x00040000 /* DMA channel 1 */
740 #define UIC_D2 0x00020000 /* DMA channel 2 */
741 #define UIC_D3 0x00010000 /* DMA channel 3 */
742 #define UIC_RSVD0 0x00008000 /* Reserved */
743 #define UIC_RSVD1 0x00004000 /* Reserved */
744 #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
745 #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
746 #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
747 #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
748 #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
749 #define UIC_EIR0 0x00000100 /* External interrupt 0 */
750 #define UIC_EIR1 0x00000080 /* External interrupt 1 */
751 #define UIC_EIR2 0x00000040 /* External interrupt 2 */
752 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
753 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
754 #define UIC_EIR5 0x00000008 /* External interrupt 5 */
755 #define UIC_EIR6 0x00000004 /* External interrupt 6 */
756 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
757 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
758 #endif /* CONFIG_440SP */
760 /* For compatibility with 405 code */
761 #define UIC_MAL_TXEOB UIC_MTE
762 #define UIC_MAL_RXEOB UIC_MRE
764 /*---------------------------------------------------------------------------+
765 | Universal interrupt controller 1 interrupts (UIC1)
766 +---------------------------------------------------------------------------*/
767 #if defined(CONFIG_440SP)
768 #define UIC_EIR0 0x80000000 /* External interrupt 0 */
769 #define UIC_MS 0x40000000 /* MAL SERR */
770 #define UIC_MTDE 0x20000000 /* MAL TXDE */
771 #define UIC_MRDE 0x10000000 /* MAL RXDE */
772 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
773 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
774 #define UIC_MTE 0x02000000 /* MAL TXEOB */
775 #define UIC_MRE 0x01000000 /* MAL RXEOB */
776 #define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
777 #define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
778 #define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
779 #define UIC_L2C 0x00100000 /* L2 cache */
780 #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
781 #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
782 #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
783 #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
784 #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
785 #define UIC_EIR1 0x00004000 /* External interrupt 1 */
786 #define UIC_EIR2 0x00002000 /* External interrupt 2 */
787 #define UIC_EIR3 0x00001000 /* External interrupt 3 */
788 #define UIC_EIR4 0x00000800 /* External interrupt 4 */
789 #define UIC_EIR5 0x00000400 /* External interrupt 5 */
790 #define UIC_DMAE 0x00000200 /* DMA error */
791 #define UIC_I2OE 0x00000100 /* I2O error */
792 #define UIC_SRE 0x00000080 /* Serial ROM error */
793 #define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
794 #define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
795 #define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
796 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
797 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
798 #define UIC_ETH1 0x00000002 /* Reserved */
799 #define UIC_XOR 0x00000001 /* XOR */
800 #else /* CONFIG_440SP */
801 #define UIC_MS 0x80000000 /* MAL SERR */
802 #define UIC_MTDE 0x40000000 /* MAL TXDE */
803 #define UIC_MRDE 0x20000000 /* MAL RXDE */
804 #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
805 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
806 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
807 #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
808 #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
809 #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
810 #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
811 #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
812 #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
813 #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
814 #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
815 #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
816 #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
817 #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
818 #define UIC_PPMI 0x00004000 /* PPM interrupt status */
819 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
820 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
821 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
822 #define UIC_EIR10 0x00000400 /* External interrupt 10 */
823 #define UIC_EIR11 0x00000200 /* External interrupt 11 */
824 #define UIC_EIR12 0x00000100 /* External interrupt 12 */
825 #define UIC_SRE 0x00000080 /* Serial ROM error */
826 #define UIC_RSVD2 0x00000040 /* Reserved */
827 #define UIC_RSVD3 0x00000020 /* Reserved */
828 #define UIC_PAE 0x00000010 /* PCI asynchronous error */
829 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
830 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
831 #define UIC_ETH1 0x00000002 /* Ethernet 1 */
832 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
833 #endif /* CONFIG_440SP */
835 /* For compatibility with 405 code */
836 #define UIC_MAL_SERR UIC_MS
837 #define UIC_MAL_TXDE UIC_MTDE
838 #define UIC_MAL_RXDE UIC_MRDE
839 #define UIC_ENET UIC_ETH0
841 /*---------------------------------------------------------------------------+
842 | Universal interrupt controller 2 interrupts (UIC2)
843 +---------------------------------------------------------------------------*/
844 #if defined(CONFIG_440GX)
845 #define UIC_ETH2 0x80000000 /* Ethernet 2 */
846 #define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
847 #define UIC_ETH3 0x20000000 /* Ethernet 3 */
848 #define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
849 #define UIC_TAH0 0x08000000 /* TAH 0 */
850 #define UIC_TAH1 0x04000000 /* TAH 1 */
851 #define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
852 #define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
853 #define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
854 #define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
855 #define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
856 #define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
857 #define UIC_IMUTO 0x00080000 /* IMU timeout */
858 #define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
859 #define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
860 #define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
861 #define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
862 #define UIC_EIR13 0x00004000 /* External interrupt 13 */
863 #define UIC_EIR14 0x00002000 /* External interrupt 14 */
864 #define UIC_EIR15 0x00001000 /* External interrupt 15 */
865 #define UIC_EIR16 0x00000800 /* External interrupt 16 */
866 #define UIC_EIR17 0x00000400 /* External interrupt 17 */
867 #define UIC_PCIVPD 0x00000200 /* PCI VPD */
868 #define UIC_L2C 0x00000100 /* L2 Cache */
869 #define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
870 #define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
871 #define UIC_RSVD26 0x00000020 /* Reserved */
872 #define UIC_RSVD27 0x00000010 /* Reserved */
873 #define UIC_RSVD28 0x00000008 /* Reserved */
874 #define UIC_RSVD29 0x00000004 /* Reserved */
875 #define UIC_RSVD30 0x00000002 /* Reserved */
876 #define UIC_RSVD31 0x00000001 /* Reserved */
877 #endif /* CONFIG_440GX */
879 /*---------------------------------------------------------------------------+
880 | Universal interrupt controller Base 0 interrupts (UICB0)
881 +---------------------------------------------------------------------------*/
882 #if defined(CONFIG_440GX)
883 #define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
884 #define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
885 #define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
886 #define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
887 #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
888 #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
890 #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
891 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
892 #endif /* CONFIG_440GX */
894 /*-----------------------------------------------------------------------------+
895 | External Bus Controller Bit Settings
896 +-----------------------------------------------------------------------------*/
897 #define EBC_CFGADDR_MASK 0x0000003F
899 #define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
900 #define EBC_BXCR_BS_MASK 0x000E0000
901 #define EBC_BXCR_BS_1MB 0x00000000
902 #define EBC_BXCR_BS_2MB 0x00020000
903 #define EBC_BXCR_BS_4MB 0x00040000
904 #define EBC_BXCR_BS_8MB 0x00060000
905 #define EBC_BXCR_BS_16MB 0x00080000
906 #define EBC_BXCR_BS_32MB 0x000A0000
907 #define EBC_BXCR_BS_64MB 0x000C0000
908 #define EBC_BXCR_BS_128MB 0x000E0000
909 #define EBC_BXCR_BU_MASK 0x00018000
910 #define EBC_BXCR_BU_R 0x00008000
911 #define EBC_BXCR_BU_W 0x00010000
912 #define EBC_BXCR_BU_RW 0x00018000
913 #define EBC_BXCR_BW_MASK 0x00006000
914 #define EBC_BXCR_BW_8BIT 0x00000000
915 #define EBC_BXCR_BW_16BIT 0x00002000
916 #define EBC_BXCR_BW_32BIT 0x00006000
917 #define EBC_BXAP_BME_ENABLED 0x80000000
918 #define EBC_BXAP_BME_DISABLED 0x00000000
919 #define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
920 #define EBC_BXAP_BCE_DISABLE 0x00000000
921 #define EBC_BXAP_BCE_ENABLE 0x00400000
922 #define EBC_BXAP_BCT_MASK 0x00300000
923 #define EBC_BXAP_BCT_2TRANS 0x00000000
924 #define EBC_BXAP_BCT_4TRANS 0x00100000
925 #define EBC_BXAP_BCT_8TRANS 0x00200000
926 #define EBC_BXAP_BCT_16TRANS 0x00300000
927 #define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
928 #define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
929 #define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
930 #define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12)
931 #define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9)
932 #define EBC_BXAP_RE_ENABLED 0x00000100
933 #define EBC_BXAP_RE_DISABLED 0x00000000
934 #define EBC_BXAP_SOR_DELAYED 0x00000000
935 #define EBC_BXAP_SOR_NONDELAYED 0x00000080
936 #define EBC_BXAP_BEM_WRITEONLY 0x00000000
937 #define EBC_BXAP_BEM_RW 0x00000040
938 #define EBC_BXAP_PEN_DISABLED 0x00000000
940 #define EBC_CFG_LE_MASK 0x80000000
941 #define EBC_CFG_LE_UNLOCK 0x00000000
942 #define EBC_CFG_LE_LOCK 0x80000000
943 #define EBC_CFG_PTD_MASK 0x40000000
944 #define EBC_CFG_PTD_ENABLE 0x00000000
945 #define EBC_CFG_PTD_DISABLE 0x40000000
946 #define EBC_CFG_RTC_MASK 0x38000000
947 #define EBC_CFG_RTC_16PERCLK 0x00000000
948 #define EBC_CFG_RTC_32PERCLK 0x08000000
949 #define EBC_CFG_RTC_64PERCLK 0x10000000
950 #define EBC_CFG_RTC_128PERCLK 0x18000000
951 #define EBC_CFG_RTC_256PERCLK 0x20000000
952 #define EBC_CFG_RTC_512PERCLK 0x28000000
953 #define EBC_CFG_RTC_1024PERCLK 0x30000000
954 #define EBC_CFG_RTC_2048PERCLK 0x38000000
955 #define EBC_CFG_ATC_MASK 0x04000000
956 #define EBC_CFG_ATC_HI 0x00000000
957 #define EBC_CFG_ATC_PREVIOUS 0x04000000
958 #define EBC_CFG_DTC_MASK 0x02000000
959 #define EBC_CFG_DTC_HI 0x00000000
960 #define EBC_CFG_DTC_PREVIOUS 0x02000000
961 #define EBC_CFG_CTC_MASK 0x01000000
962 #define EBC_CFG_CTC_HI 0x00000000
963 #define EBC_CFG_CTC_PREVIOUS 0x01000000
964 #define EBC_CFG_OEO_MASK 0x00800000
965 #define EBC_CFG_OEO_HI 0x00000000
966 #define EBC_CFG_OEO_PREVIOUS 0x00800000
967 #define EBC_CFG_EMC_MASK 0x00400000
968 #define EBC_CFG_EMC_NONDEFAULT 0x00000000
969 #define EBC_CFG_EMC_DEFAULT 0x00400000
970 #define EBC_CFG_PME_MASK 0x00200000
971 #define EBC_CFG_PME_DISABLE 0x00000000
972 #define EBC_CFG_PME_ENABLE 0x00200000
973 #define EBC_CFG_PMT_MASK 0x001F0000
974 #define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
975 #define EBC_CFG_PR_MASK 0x0000C000
976 #define EBC_CFG_PR_16 0x00000000
977 #define EBC_CFG_PR_32 0x00004000
978 #define EBC_CFG_PR_64 0x00008000
979 #define EBC_CFG_PR_128 0x0000C000
981 /*-----------------------------------------------------------------------------+
983 +-----------------------------------------------------------------------------*/
984 #define SDR0_SDCS_SDD (0x80000000 >> 31)
986 #if defined(CONFIG_440GP)
987 #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
988 #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
989 #endif /* defined(CONFIG_440GP) */
990 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
991 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
992 #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
993 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
994 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
995 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
996 #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
997 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
999 #define SDR0_UARTX_UXICS_MASK 0xF0000000
1000 #define SDR0_UARTX_UXICS_PLB 0x20000000
1001 #define SDR0_UARTX_UXEC_MASK 0x00800000
1002 #define SDR0_UARTX_UXEC_INT 0x00000000
1003 #define SDR0_UARTX_UXEC_EXT 0x00800000
1004 #define SDR0_UARTX_UXDTE_MASK 0x00400000
1005 #define SDR0_UARTX_UXDTE_DISABLE 0x00000000
1006 #define SDR0_UARTX_UXDTE_ENABLE 0x00400000
1007 #define SDR0_UARTX_UXDRE_MASK 0x00200000
1008 #define SDR0_UARTX_UXDRE_DISABLE 0x00000000
1009 #define SDR0_UARTX_UXDRE_ENABLE 0x00200000
1010 #define SDR0_UARTX_UXDC_MASK 0x00100000
1011 #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
1012 #define SDR0_UARTX_UXDC_CLEARED 0x00100000
1013 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
1014 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1015 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
1017 #define SDR0_CPU440_EARV_MASK 0x30000000
1018 #define SDR0_CPU440_EARV_EBC 0x10000000
1019 #define SDR0_CPU440_EARV_PCI 0x20000000
1020 #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1021 #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1022 #define SDR0_CPU440_NTO1_MASK 0x00000002
1023 #define SDR0_CPU440_NTO1_NTOP 0x00000000
1024 #define SDR0_CPU440_NTO1_NTO1 0x00000002
1025 #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1026 #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
1028 #define SDR0_XCR_PAE_MASK 0x80000000
1029 #define SDR0_XCR_PAE_DISABLE 0x00000000
1030 #define SDR0_XCR_PAE_ENABLE 0x80000000
1031 #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1032 #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1033 #define SDR0_XCR_PHCE_MASK 0x40000000
1034 #define SDR0_XCR_PHCE_DISABLE 0x00000000
1035 #define SDR0_XCR_PHCE_ENABLE 0x40000000
1036 #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1037 #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1038 #define SDR0_XCR_PISE_MASK 0x20000000
1039 #define SDR0_XCR_PISE_DISABLE 0x00000000
1040 #define SDR0_XCR_PISE_ENABLE 0x20000000
1041 #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1042 #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1043 #define SDR0_XCR_PCWE_MASK 0x10000000
1044 #define SDR0_XCR_PCWE_DISABLE 0x00000000
1045 #define SDR0_XCR_PCWE_ENABLE 0x10000000
1046 #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1047 #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1048 #define SDR0_XCR_PPIM_MASK 0x0F000000
1049 #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1050 #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1051 #define SDR0_XCR_PR64E_MASK 0x00800000
1052 #define SDR0_XCR_PR64E_DISABLE 0x00000000
1053 #define SDR0_XCR_PR64E_ENABLE 0x00800000
1054 #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1055 #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1056 #define SDR0_XCR_PXFS_MASK 0x00600000
1057 #define SDR0_XCR_PXFS_HIGH 0x00000000
1058 #define SDR0_XCR_PXFS_MED 0x00200000
1059 #define SDR0_XCR_PXFS_LOW 0x00400000
1060 #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1061 #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1062 #define SDR0_XCR_PDM_MASK 0x00000040
1063 #define SDR0_XCR_PDM_MULTIPOINT 0x00000000
1064 #define SDR0_XCR_PDM_P2P 0x00000040
1065 #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
1066 #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
1068 #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
1069 #define SDR0_PFC0_GEIE_MASK 0x00003E00
1070 #define SDR0_PFC0_GEIE_TRE 0x00003E00
1071 #define SDR0_PFC0_GEIE_NOTRE 0x00000000
1072 #define SDR0_PFC0_TRE_MASK 0x00000100
1073 #define SDR0_PFC0_TRE_DISABLE 0x00000000
1074 #define SDR0_PFC0_TRE_ENABLE 0x00000100
1075 #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1076 #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
1078 #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
1079 #define SDR0_PFC1_EPS_MASK 0x01C00000
1080 #define SDR0_PFC1_EPS_GROUP0 0x00000000
1081 #define SDR0_PFC1_EPS_GROUP1 0x00400000
1082 #define SDR0_PFC1_EPS_GROUP2 0x00800000
1083 #define SDR0_PFC1_EPS_GROUP3 0x00C00000
1084 #define SDR0_PFC1_EPS_GROUP4 0x01000000
1085 #define SDR0_PFC1_EPS_GROUP5 0x01400000
1086 #define SDR0_PFC1_EPS_GROUP6 0x01800000
1087 #define SDR0_PFC1_EPS_GROUP7 0x01C00000
1088 #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1089 #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1090 #define SDR0_PFC1_RMII_MASK 0x00200000
1091 #define SDR0_PFC1_RMII_100MBIT 0x00000000
1092 #define SDR0_PFC1_RMII_10MBIT 0x00200000
1093 #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
1094 #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1095 #define SDR0_PFC1_CTEMS_MASK 0x00100000
1096 #define SDR0_PFC1_CTEMS_EMS 0x00000000
1097 #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
1099 #define SDR0_MFR_TAH0_MASK 0x80000000
1100 #define SDR0_MFR_TAH0_ENABLE 0x00000000
1101 #define SDR0_MFR_TAH0_DISABLE 0x80000000
1102 #define SDR0_MFR_TAH1_MASK 0x40000000
1103 #define SDR0_MFR_TAH1_ENABLE 0x00000000
1104 #define SDR0_MFR_TAH1_DISABLE 0x40000000
1105 #define SDR0_MFR_PCM_MASK 0x20000000
1106 #define SDR0_MFR_PCM_PPC440GX 0x00000000
1107 #define SDR0_MFR_PCM_PPC440GP 0x20000000
1108 #define SDR0_MFR_ECS_MASK 0x10000000
1109 #define SDR0_MFR_ECS_INTERNAL 0x10000000
1111 #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
1112 #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
1113 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1114 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1115 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1116 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1117 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1118 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1119 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1120 #define SDR0_MFR_ERRATA3_EN0 0x00800000
1121 #define SDR0_MFR_ERRATA3_EN1 0x00400000
1122 #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
1123 #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1124 #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
1125 #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
1126 #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
1128 #define SDR0_SRST_BGO 0x80000000
1129 #define SDR0_SRST_PLB 0x40000000
1130 #define SDR0_SRST_EBC 0x20000000
1131 #define SDR0_SRST_OPB 0x10000000
1132 #define SDR0_SRST_UART0 0x08000000
1133 #define SDR0_SRST_UART1 0x04000000
1134 #define SDR0_SRST_IIC0 0x02000000
1135 #define SDR0_SRST_IIC1 0x01000000
1136 #define SDR0_SRST_GPIO 0x00800000
1137 #define SDR0_SRST_GPT 0x00400000
1138 #define SDR0_SRST_DMC 0x00200000
1139 #define SDR0_SRST_PCI 0x00100000
1140 #define SDR0_SRST_EMAC0 0x00080000
1141 #define SDR0_SRST_EMAC1 0x00040000
1142 #define SDR0_SRST_CPM 0x00020000
1143 #define SDR0_SRST_IMU 0x00010000
1144 #define SDR0_SRST_UIC01 0x00008000
1145 #define SDR0_SRST_UICB2 0x00004000
1146 #define SDR0_SRST_SRAM 0x00002000
1147 #define SDR0_SRST_EBM 0x00001000
1148 #define SDR0_SRST_BGI 0x00000800
1149 #define SDR0_SRST_DMA 0x00000400
1150 #define SDR0_SRST_DMAC 0x00000200
1151 #define SDR0_SRST_MAL 0x00000100
1152 #define SDR0_SRST_ZMII 0x00000080
1153 #define SDR0_SRST_GPTR 0x00000040
1154 #define SDR0_SRST_PPM 0x00000020
1155 #define SDR0_SRST_EMAC2 0x00000010
1156 #define SDR0_SRST_EMAC3 0x00000008
1157 #define SDR0_SRST_RGMII 0x00000001
1159 /*-----------------------------------------------------------------------------+
1161 +-----------------------------------------------------------------------------*/
1162 #if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
1163 #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
1164 #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
1165 #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
1166 #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
1167 #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
1168 #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
1169 #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
1170 #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
1171 #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
1172 #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
1173 #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
1174 #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
1176 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1177 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1178 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1179 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
1180 #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
1181 #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
1182 #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
1183 #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
1184 #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
1185 #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
1186 #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
1187 #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
1188 #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
1189 #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
1191 #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
1192 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
1193 #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
1194 #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
1195 #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
1196 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
1198 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
1199 #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
1200 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
1201 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
1202 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
1204 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1205 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1206 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1207 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
1209 /* Strap 1 Register */
1210 #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
1211 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1212 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
1213 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
1214 #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
1215 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
1216 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
1217 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
1218 #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
1219 #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
1220 #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
1221 #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
1222 #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
1223 #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
1224 #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
1225 #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
1226 #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
1227 #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
1228 #endif /* CONFIG_440GX */
1230 /*-----------------------------------------------------------------------------
1231 | IIC Register Offsets
1232 '----------------------------------------------------------------------------*/
1233 #define IICMDBUF 0x00
1234 #define IICSDBUF 0x02
1235 #define IICLMADR 0x04
1236 #define IICHMADR 0x05
1237 #define IICCNTL 0x06
1238 #define IICMDCNTL 0x07
1240 #define IICEXTSTS 0x09
1241 #define IICLSADR 0x0A
1242 #define IICHSADR 0x0B
1243 #define IICCLKDIV 0x0C
1244 #define IICINTRMSK 0x0D
1245 #define IICXFRCNT 0x0E
1246 #define IICXTCNTLSS 0x0F
1247 #define IICDIRECTCNTL 0x10
1249 /*-----------------------------------------------------------------------------
1250 | UART Register Offsets
1251 '----------------------------------------------------------------------------*/
1252 #define DATA_REG 0x00
1255 #define INT_ENABLE 0x01
1256 #define FIFO_CONTROL 0x02
1257 #define LINE_CONTROL 0x03
1258 #define MODEM_CONTROL 0x04
1259 #define LINE_STATUS 0x05
1260 #define MODEM_STATUS 0x06
1261 #define SCRATCH 0x07
1263 /*-----------------------------------------------------------------------------
1264 | PCI Internal Registers et. al. (accessed via plb)
1265 +----------------------------------------------------------------------------*/
1266 #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000)
1267 #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004)
1268 #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
1269 #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
1271 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
1273 /* PCI Local Configuration Registers
1274 --------------------------------- */
1275 #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
1277 /* PCI Master Local Configuration Registers */
1278 #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
1279 #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
1280 #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
1281 #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
1282 #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
1283 #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
1284 #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
1285 #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
1286 #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
1287 #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
1288 #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
1289 #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
1291 /* PCI Target Local Configuration Registers */
1292 #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
1293 #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
1294 #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
1295 #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
1299 #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
1300 #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
1301 #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
1302 #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
1303 #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
1304 #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
1305 #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
1306 #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
1307 #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
1308 #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
1309 #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
1310 #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
1311 #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
1312 #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
1313 #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
1314 #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
1315 #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
1316 #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
1317 #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
1318 #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
1319 #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
1320 #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
1321 #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
1322 #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
1323 #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
1324 #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
1325 #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
1326 #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
1328 #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
1329 #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
1331 #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
1332 #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
1333 #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
1334 #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
1335 #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
1336 #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
1337 #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
1338 #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
1339 #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
1340 #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
1341 #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
1343 #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
1344 #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
1345 #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
1346 #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
1347 #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
1348 #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
1349 #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
1350 #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
1351 #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
1353 #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
1355 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
1357 /******************************************************************************
1358 * GPIO macro register defines
1359 ******************************************************************************/
1360 #if defined(CONFIG_440GP)
1361 #define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700)
1363 #define GPIO0_OR (GPIO_BASE0+0x0)
1364 #define GPIO0_TCR (GPIO_BASE0+0x4)
1365 #define GPIO0_ODR (GPIO_BASE0+0x18)
1366 #define GPIO0_IR (GPIO_BASE0+0x1C)
1367 #endif /* CONFIG_440GP */
1369 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
1370 #define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
1371 #define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)
1373 #define GPIO0_OR (GPIO_BASE0+0x0)
1374 #define GPIO0_TCR (GPIO_BASE0+0x4)
1375 #define GPIO0_OSRL (GPIO_BASE0+0x8)
1376 #define GPIO0_OSRH (GPIO_BASE0+0xC)
1377 #define GPIO0_TSRL (GPIO_BASE0+0x10)
1378 #define GPIO0_TSRH (GPIO_BASE0+0x14)
1379 #define GPIO0_ODR (GPIO_BASE0+0x18)
1380 #define GPIO0_IR (GPIO_BASE0+0x1C)
1381 #define GPIO0_RR1 (GPIO_BASE0+0x20)
1382 #define GPIO0_RR2 (GPIO_BASE0+0x24)
1383 #define GPIO0_RR3 (GPIO_BASE0+0x28)
1384 #define GPIO0_ISR1L (GPIO_BASE0+0x30)
1385 #define GPIO0_ISR1H (GPIO_BASE0+0x34)
1386 #define GPIO0_ISR2L (GPIO_BASE0+0x38)
1387 #define GPIO0_ISR2H (GPIO_BASE0+0x3C)
1388 #define GPIO0_ISR3L (GPIO_BASE0+0x40)
1389 #define GPIO0_ISR3H (GPIO_BASE0+0x44)
1391 #define GPIO1_OR (GPIO_BASE1+0x0)
1392 #define GPIO1_TCR (GPIO_BASE1+0x4)
1393 #define GPIO1_OSRL (GPIO_BASE1+0x8)
1394 #define GPIO1_OSRH (GPIO_BASE1+0xC)
1395 #define GPIO1_TSRL (GPIO_BASE1+0x10)
1396 #define GPIO1_TSRH (GPIO_BASE1+0x14)
1397 #define GPIO1_ODR (GPIO_BASE1+0x18)
1398 #define GPIO1_IR (GPIO_BASE1+0x1C)
1399 #define GPIO1_RR1 (GPIO_BASE1+0x20)
1400 #define GPIO1_RR2 (GPIO_BASE1+0x24)
1401 #define GPIO1_RR3 (GPIO_BASE1+0x28)
1402 #define GPIO1_ISR1L (GPIO_BASE1+0x30)
1403 #define GPIO1_ISR1H (GPIO_BASE1+0x34)
1404 #define GPIO1_ISR2L (GPIO_BASE1+0x38)
1405 #define GPIO1_ISR2H (GPIO_BASE1+0x3C)
1406 #define GPIO1_ISR3L (GPIO_BASE1+0x40)
1407 #define GPIO1_ISR3H (GPIO_BASE1+0x44)
1411 * Macros for accessing the indirect EBC registers
1413 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
1414 #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
1417 * Macros for accessing the indirect SDRAM controller registers
1419 #define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
1420 #define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
1423 * Macros for accessing the indirect clocking controller registers
1425 #define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
1426 #define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
1429 * Macros for accessing the sdr controller registers
1431 #define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
1432 #define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
1435 #ifndef __ASSEMBLY__
1438 unsigned long pllFwdDivA;
1439 unsigned long pllFwdDivB;
1440 unsigned long pllFbkDiv;
1441 unsigned long pllOpbDiv;
1442 unsigned long pllPciDiv;
1443 unsigned long pllExtBusDiv;
1444 unsigned long freqVCOMhz; /* in MHz */
1445 unsigned long freqProcessor;
1446 unsigned long freqTmrClk;
1447 unsigned long freqPLB;
1448 unsigned long freqOPB;
1449 unsigned long freqEPB;
1450 unsigned long freqPCI;
1451 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
1452 unsigned long pciClkSync; /* PCI clock is synchronous */
1455 #endif /* _ASMLANGUAGE */
1457 #define RESET_VECTOR 0xfffffffc
1458 #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */
1459 /* cache line aligned data. */
1461 #endif /* __PPC440_H__ */
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