2 * Copyright (C) STMicroelectronics SA 2017
3 * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
15 #define AHB_PSC_16 0xB
16 #define AHB_PSC_64 0xC
17 #define AHB_PSC_128 0xD
18 #define AHB_PSC_256 0xE
19 #define AHB_PSC_512 0xF
25 #define APB_PSC_16 0x7
37 struct stm32_clk_info {
38 struct pll_psc sys_pll_psc;
48 struct stm32_rcc_clk {
53 struct stm32_rcc_regs {
54 u32 cr; /* RCC clock control */
55 u32 pllcfgr; /* RCC PLL configuration */
56 u32 cfgr; /* RCC clock configuration */
57 u32 cir; /* RCC clock interrupt */
58 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
59 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
60 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
62 u32 apb1rstr; /* RCC APB1 peripheral reset */
63 u32 apb2rstr; /* RCC APB2 peripheral reset */
65 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
66 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
67 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
69 u32 apb1enr; /* RCC APB1 peripheral clock enable */
70 u32 apb2enr; /* RCC APB2 peripheral clock enable */
72 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
73 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
74 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
76 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
77 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
79 u32 bdcr; /* RCC Backup domain control */
80 u32 csr; /* RCC clock control & status */
82 u32 sscgr; /* RCC spread spectrum clock generation */
83 u32 plli2scfgr; /* RCC PLLI2S configuration */
84 /* below registers are only available on STM32F46x and STM32F7 SoCs*/
85 u32 pllsaicfgr; /* PLLSAI configuration */
86 u32 dckcfgr; /* dedicated clocks configuration register */
87 /* Below registers are only available on STM32F7 SoCs */
88 u32 dckcfgr2; /* dedicated clocks configuration register */
91 #endif /* __STM32_RCC_H_ */