2 * (C) Copyright 2011 Andes Technology Corp
3 * Macpaul Lin <macpaul@andestech.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
23 #ifndef __DWCDDR21MCTL_H
24 #define __DWCDDR21MCTL_H
28 unsigned int ccr; /* Controller Configuration */
29 unsigned int dcr; /* DRAM Configuration */
30 unsigned int iocr; /* I/O Configuration */
31 unsigned int csr; /* Controller Status */
32 unsigned int drr; /* DRAM refresh */
33 unsigned int tpr0; /* SDRAM Timing Parameters 0 */
34 unsigned int tpr1; /* SDRAM Timing Parameters 1 */
35 unsigned int tpr2; /* SDRAM Timing Parameters 2 */
36 unsigned int gdllcr; /* Global DLL Control */
37 unsigned int dllcr[10]; /* DLL Control */
38 unsigned int rslr[4]; /* Rank System Lantency */
39 unsigned int rdgr[4]; /* Rank DQS Gating */
40 unsigned int dqtr[9]; /* DQ Timing */
41 unsigned int dqstr; /* DQS Timing */
42 unsigned int dqsbtr; /* DQS_b Timing */
43 unsigned int odtcr; /* ODT Configuration */
44 unsigned int dtr[2]; /* Data Training */
45 unsigned int dtar; /* Data Training Address */
46 unsigned int rsved[82]; /* Reserved */
47 unsigned int mr; /* Mode Register */
48 unsigned int emr; /* Extended Mode Register */
49 unsigned int emr2; /* Extended Mode Register 2 */
50 unsigned int emr3; /* Extended Mode Register 3 */
51 unsigned int hpcr[32]; /* Host Port Configurarion */
52 unsigned int pqcr[8]; /* Priority Queue Configuration */
53 unsigned int mmgcr; /* Memory Manager General Config */
55 #endif /* __ASSEMBLY__ */
58 * Control Configuration Register
60 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0)
61 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1)
62 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2)
63 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3)
64 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4)
65 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13)
66 #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14)
67 #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15)
68 #define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17)
69 #define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27)
70 #define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28)
71 #define DWCDDR21MCTL_CCR_IB(x) ((x) << 29)
72 #define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30)
73 #define DWCDDR21MCTL_CCR_IT(x) ((x) << 31)
76 * DRAM Configuration Register
78 #define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0)
79 #define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1)
80 #define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
81 #define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
82 #define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9)
83 #define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10)
84 #define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12)
85 #define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13)
86 #define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25)
87 #define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
88 #define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31)
91 * I/O Configuration Register
93 #define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
94 #define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
95 #define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8)
96 #define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
97 #define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29)
98 #define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30)
99 #define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31)
102 * Controller Status Register
104 #define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0)
105 #define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18)
106 #define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19)
107 #define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20)
108 #define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21)
109 #define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22)
112 * DRAM Refresh Register
114 #define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0)
115 #define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8)
116 #define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
117 #define DWCDDR21MCTL_DRR_RD(x) ((x) << 31)
120 * SDRAM Timing Parameters Register 0
122 #define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0)
123 #define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
124 #define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
125 #define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
126 #define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
127 #define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16)
128 #define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
129 #define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25)
130 #define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31)
133 * SDRAM Timing Parameters Register 1
135 #define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0)
136 #define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2)
137 #define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3)
138 #define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12)
139 #define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14)
140 #define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
141 #define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
142 #define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31)
145 * SDRAM Timing Parameters Register 2
147 #define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0)
148 #define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10)
149 #define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
152 * Global DLL Control Register
154 #define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0)
155 #define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
156 #define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5)
157 #define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
158 #define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9)
159 #define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11)
160 #define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12)
161 #define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20)
162 #define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29)
165 * DLL Control Register 0-9
167 #define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
168 #define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
169 #define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6)
170 #define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9)
171 #define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12)
172 #define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)
173 #define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18)
174 #define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19)
175 #define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31)
178 * Rank System Lantency Register
180 #define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0)
181 #define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3)
182 #define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6)
183 #define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9)
184 #define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12)
185 #define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15)
186 #define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18)
187 #define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21)
188 #define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24)
191 * Rank DQS Gating Register
193 #define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0)
194 #define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2)
195 #define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4)
196 #define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6)
197 #define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8)
198 #define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10)
199 #define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12)
200 #define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14)
201 #define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16)
206 #define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0)
207 #define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4)
208 #define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8)
209 #define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12)
210 #define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16)
211 #define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20)
212 #define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24)
213 #define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28)
216 * DQS Timing Register
218 #define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0)
219 #define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3)
220 #define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6)
221 #define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9)
222 #define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12)
223 #define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15)
224 #define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18)
225 #define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21)
226 #define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24)
229 * DQS_b (DQSBTR) Timing Register
231 #define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0)
232 #define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3)
233 #define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6)
234 #define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9)
235 #define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12)
236 #define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15)
237 #define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18)
238 #define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21)
239 #define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24)
242 * ODT Configuration Register
244 #define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0)
245 #define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4)
246 #define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8)
247 #define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12)
248 #define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16)
249 #define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20)
250 #define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24)
251 #define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28)
254 * Data Training Register
256 #define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */
257 #define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */
258 #define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */
259 #define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */
261 #define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */
262 #define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */
263 #define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */
264 #define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */
267 * Data Training Address Register
269 #define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0)
270 #define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12)
271 #define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28)
276 #define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0)
277 #define DWCDDR21MCTL_MR_BT(x) ((x) << 3)
278 #define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4)
279 #define DWCDDR21MCTL_MR_TM(x) ((x) << 7)
280 #define DWCDDR21MCTL_MR_DR(x) ((x) << 8)
281 #define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9)
282 #define DWCDDR21MCTL_MR_PD(x) ((x) << 12)
285 * Extended Mode register
287 #define DWCDDR21MCTL_EMR_DE(x) ((x) << 0)
288 #define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1)
289 #define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2)
290 #define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3)
291 #define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6)
292 #define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7)
293 #define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10)
294 #define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11)
295 #define DWCDDR21MCTL_EMR_OE(x) ((x) << 12)
297 #define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x)
298 #define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x)
300 #define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0))
301 #define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1))
302 #define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0))
303 #define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1))
306 * Extended Mode register 2
308 #define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0)
309 #define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3)
310 #define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7)
313 * Extended Mode register 3: [15:0] reserved for JEDEC.
317 * Host port Configuration register 0-31
319 #define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0)
322 * Priority Queue Configuration register 0-7
324 #define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0)
325 #define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8)
326 #define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10)
327 #define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12)
328 #define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20)
329 #define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25)
330 #define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28)
333 * Memory Manager General Configuration register
335 #define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0)
337 #endif /* __DWCDDR21MCTL_H */