1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*****************************************************************************
3 * (C) Copyright 2003; Tundra Semiconductor Corp.
4 * (C) Copyright 2006; Freescale Semiconductor Corp.
5 *****************************************************************************/
10 * Originator: Alex Bounine
13 * Common definitions for the Tundra Tsi108 bridge chip
20 #define TSI108_HLP_REG_OFFSET (0x0000)
21 #define TSI108_PCI_REG_OFFSET (0x1000)
22 #define TSI108_CLK_REG_OFFSET (0x2000)
23 #define TSI108_PB_REG_OFFSET (0x3000)
24 #define TSI108_SD_REG_OFFSET (0x4000)
25 #define TSI108_MPIC_REG_OFFSET (0x7400)
28 #define PB_RSR (0x004)
29 #define PB_BUS_MS_SELECT (0x008)
30 #define PB_ISR (0x00C)
31 #define PB_ARB_CTRL (0x018)
32 #define PB_PVT_CTRL2 (0x034)
33 #define PB_SCR (0x400)
34 #define PB_ERRCS (0x404)
35 #define PB_AERR (0x408)
36 #define PB_REG_BAR (0x410)
37 #define PB_OCN_BAR1 (0x414)
38 #define PB_OCN_BAR2 (0x418)
39 #define PB_SDRAM_BAR1 (0x41C)
40 #define PB_SDRAM_BAR2 (0x420)
41 #define PB_MCR (0xC00)
42 #define PB_MCMD (0xC04)
44 #define HLP_B0_ADDR (0x000)
45 #define HLP_B1_ADDR (0x010)
46 #define HLP_B2_ADDR (0x020)
47 #define HLP_B3_ADDR (0x030)
49 #define HLP_B0_MASK (0x004)
50 #define HLP_B1_MASK (0x014)
51 #define HLP_B2_MASK (0x024)
52 #define HLP_B3_MASK (0x034)
54 #define HLP_B0_CTRL0 (0x008)
55 #define HLP_B1_CTRL0 (0x018)
56 #define HLP_B2_CTRL0 (0x028)
57 #define HLP_B3_CTRL0 (0x038)
59 #define HLP_B0_CTRL1 (0x00C)
60 #define HLP_B1_CTRL1 (0x01C)
61 #define HLP_B2_CTRL1 (0x02C)
62 #define HLP_B3_CTRL1 (0x03C)
64 #define PCI_CSR (0x004)
65 #define PCI_P2O_BAR0 (0x010)
66 #define PCI_P2O_BAR0_UPPER (0x014)
67 #define PCI_P2O_BAR2 (0x018)
68 #define PCI_P2O_BAR2_UPPER (0x01C)
69 #define PCI_P2O_BAR3 (0x020)
70 #define PCI_P2O_BAR3_UPPER (0x024)
72 #define PCI_MISC_CSR (0x040)
73 #define PCI_P2O_PAGE_SIZES (0x04C)
75 #define PCI_PCIX_STAT (0x0F4)
77 #define PCI_IRP_STAT (0x184)
79 #define PCI_PFAB_BAR0 (0x204)
80 #define PCI_PFAB_BAR0_UPPER (0x208)
81 #define PCI_PFAB_IO (0x20C)
82 #define PCI_PFAB_IO_UPPER (0x210)
84 #define PCI_PFAB_MEM32 (0x214)
85 #define PCI_PFAB_MEM32_REMAP (0x218)
86 #define PCI_PFAB_MEM32_MASK (0x21C)
88 #define CG_PLL0_CTRL0 (0x210)
89 #define CG_PLL0_CTRL1 (0x214)
90 #define CG_PLL1_CTRL0 (0x220)
91 #define CG_PLL1_CTRL1 (0x224)
92 #define CG_PWRUP_STATUS (0x234)
94 #define MPIC_CSR(n) (0x30C + (n * 0x40))
96 #define SD_CTRL (0x000)
97 #define SD_STATUS (0x004)
98 #define SD_TIMING (0x008)
99 #define SD_REFRESH (0x00C)
100 #define SD_INT_STATUS (0x010)
101 #define SD_INT_ENABLE (0x014)
102 #define SD_INT_SET (0x018)
103 #define SD_D0_CTRL (0x020)
104 #define SD_D1_CTRL (0x024)
105 #define SD_D0_BAR (0x028)
106 #define SD_D1_BAR (0x02C)
107 #define SD_ECC_CTRL (0x040)
108 #define SD_DLL_STATUS (0x250)
110 #define TS_SD_CTRL_ENABLE (1 << 31)
112 #define PB_ERRCS_ES (1 << 1)
113 #define PB_ISR_PBS_RD_ERR (1 << 8)
114 #define PCI_IRP_STAT_P_CSR (1 << 23)
117 * I2C : Register address offset definitions
119 #define I2C_CNTRL1 (0x00000000)
120 #define I2C_CNTRL2 (0x00000004)
121 #define I2C_RD_DATA (0x00000008)
122 #define I2C_TX_DATA (0x0000000c)
125 * I2C : Register Bit Masks and Reset Values
126 * definitions for every register
129 /* I2C_CNTRL1 : Reset Value */
130 #define I2C_CNTRL1_RESET_VALUE (0x0000000a)
132 /* I2C_CNTRL1 : Register Bits Masks Definitions */
133 #define I2C_CNTRL1_DEVCODE (0x0000000f)
134 #define I2C_CNTRL1_PAGE (0x00000700)
135 #define I2C_CNTRL1_BYTADDR (0x00ff0000)
136 #define I2C_CNTRL1_I2CWRITE (0x01000000)
138 /* I2C_CNTRL1 : Read/Write Bit Mask Definition */
139 #define I2C_CNTRL1_RWMASK (0x01ff070f)
141 /* I2C_CNTRL1 : Unused/Reserved bits Definition */
142 #define I2C_CNTRL1_RESERVED (0xfe00f8f0)
144 /* I2C_CNTRL2 : Reset Value */
145 #define I2C_CNTRL2_RESET_VALUE (0x00000000)
147 /* I2C_CNTRL2 : Register Bits Masks Definitions */
148 #define I2C_CNTRL2_SIZE (0x00000003)
149 #define I2C_CNTRL2_LANE (0x0000000c)
150 #define I2C_CNTRL2_MULTIBYTE (0x00000010)
151 #define I2C_CNTRL2_START (0x00000100)
152 #define I2C_CNTRL2_WR_STATUS (0x00010000)
153 #define I2C_CNTRL2_RD_STATUS (0x00020000)
154 #define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
155 #define I2C_CNTRL2_I2C_CFGERR (0x08000000)
156 #define I2C_CNTRL2_I2C_CMPLT (0x10000000)
158 /* I2C_CNTRL2 : Read/Write Bit Mask Definition */
159 #define I2C_CNTRL2_RWMASK (0x0000011f)
161 /* I2C_CNTRL2 : Unused/Reserved bits Definition */
162 #define I2C_CNTRL2_RESERVED (0xe3fcfee0)
164 /* I2C_RD_DATA : Reset Value */
165 #define I2C_RD_DATA_RESET_VALUE (0x00000000)
167 /* I2C_RD_DATA : Register Bits Masks Definitions */
168 #define I2C_RD_DATA_RBYTE0 (0x000000ff)
169 #define I2C_RD_DATA_RBYTE1 (0x0000ff00)
170 #define I2C_RD_DATA_RBYTE2 (0x00ff0000)
171 #define I2C_RD_DATA_RBYTE3 (0xff000000)
173 /* I2C_RD_DATA : Read/Write Bit Mask Definition */
174 #define I2C_RD_DATA_RWMASK (0x00000000)
176 /* I2C_RD_DATA : Unused/Reserved bits Definition */
177 #define I2C_RD_DATA_RESERVED (0x00000000)
179 /* I2C_TX_DATA : Reset Value */
180 #define I2C_TX_DATA_RESET_VALUE (0x00000000)
182 /* I2C_TX_DATA : Register Bits Masks Definitions */
183 #define I2C_TX_DATA_TBYTE0 (0x000000ff)
184 #define I2C_TX_DATA_TBYTE1 (0x0000ff00)
185 #define I2C_TX_DATA_TBYTE2 (0x00ff0000)
186 #define I2C_TX_DATA_TBYTE3 (0xff000000)
188 /* I2C_TX_DATA : Read/Write Bit Mask Definition */
189 #define I2C_TX_DATA_RWMASK (0xffffffff)
191 /* I2C_TX_DATA : Unused/Reserved bits Definition */
192 #define I2C_TX_DATA_RESERVED (0x00000000)
194 #define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
195 #define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
197 #define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
199 /* I2C status codes */
201 #define TSI108_I2C_SUCCESS 0
202 #define TSI108_I2C_PARAM_ERR 1
203 #define TSI108_I2C_TIMEOUT_ERR 2
204 #define TSI108_I2C_IF_BUSY 3
205 #define TSI108_I2C_IF_ERROR 4
207 #endif /* _TSI108_H_ */