2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
13 * Supports: IT8603E Super I/O chip w/LPC interface
14 * IT8606E Super I/O chip w/LPC interface
15 * IT8607E Super I/O chip w/LPC interface
16 * IT8613E Super I/O chip w/LPC interface
17 * IT8620E Super I/O chip w/LPC interface
18 * IT8622E Super I/O chip w/LPC interface
19 * IT8623E Super I/O chip w/LPC interface
20 * IT8625E Super I/O chip w/LPC interface
21 * IT8628E Super I/O chip w/LPC interface
22 * IT8655E Super I/O chip w/LPC interface
23 * IT8665E Super I/O chip w/LPC interface
24 * IT8686E Super I/O chip w/LPC interface
25 * IT8705F Super I/O chip w/LPC interface
26 * IT8712F Super I/O chip w/LPC interface
27 * IT8716F Super I/O chip w/LPC interface
28 * IT8718F Super I/O chip w/LPC interface
29 * IT8720F Super I/O chip w/LPC interface
30 * IT8721F Super I/O chip w/LPC interface
31 * IT8726F Super I/O chip w/LPC interface
32 * IT8728F Super I/O chip w/LPC interface
33 * IT8732F Super I/O chip w/LPC interface
34 * IT8736F Super I/O chip w/LPC interface
35 * IT8738E Super I/O chip w/LPC interface
36 * IT8758E Super I/O chip w/LPC interface
37 * IT8771E Super I/O chip w/LPC interface
38 * IT8772E Super I/O chip w/LPC interface
39 * IT8781F Super I/O chip w/LPC interface
40 * IT8782F Super I/O chip w/LPC interface
41 * IT8783E/F Super I/O chip w/LPC interface
42 * IT8786E Super I/O chip w/LPC interface
43 * IT8790E Super I/O chip w/LPC interface
44 * IT8792E Super I/O chip w/LPC interface
45 * Sis950 A clone of the IT8705F
47 * Copyright (C) 2001 Chris Gauthron
48 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
50 * This program is free software; you can redistribute it and/or modify
51 * it under the terms of the GNU General Public License as published by
52 * the Free Software Foundation; either version 2 of the License, or
53 * (at your option) any later version.
55 * This program is distributed in the hope that it will be useful,
56 * but WITHOUT ANY WARRANTY; without even the implied warranty of
57 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
58 * GNU General Public License for more details.
61 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
63 #include <linux/bitops.h>
64 #include <linux/module.h>
65 #include <linux/init.h>
66 #include <linux/slab.h>
67 #include <linux/jiffies.h>
68 #include <linux/platform_device.h>
69 #include <linux/hwmon.h>
70 #include <linux/hwmon-sysfs.h>
71 #include <linux/hwmon-vid.h>
72 #include <linux/err.h>
73 #include <linux/mutex.h>
74 #include <linux/sysfs.h>
75 #include <linux/string.h>
76 #include <linux/dmi.h>
77 #include <linux/acpi.h>
81 #ifndef IT87_DRIVER_VERSION
82 #define IT87_DRIVER_VERSION "<not provided>"
85 #define DRVNAME "it87"
87 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
89 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
90 it8792, it8603, it8606, it8607, it8613, it8620, it8622, it8625,
91 it8628, it8655, it8665, it8686 };
93 static unsigned short force_id;
94 module_param(force_id, ushort, 0000);
95 MODULE_PARM_DESC(force_id, "Override the detected device ID");
97 static bool ignore_resource_conflict;
98 module_param(ignore_resource_conflict, bool, 0000);
99 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
102 module_param(mmio, bool, 0000);
103 MODULE_PARM_DESC(mmio, "Use MMIO if available");
105 static struct platform_device *it87_pdev[2];
107 #define REG_2E 0x2e /* The register to read/write */
108 #define REG_4E 0x4e /* Secondary register to read/write */
110 #define DEV 0x07 /* Register: Logical device select */
111 #define PME 0x04 /* The device with the fan registers in it */
113 /* The device with the IT8718F/IT8720F VID value in it */
116 #define DEVID 0x20 /* Register: Device ID */
117 #define DEVREV 0x22 /* Register: Device Revision */
119 static inline void __superio_enter(int ioreg)
124 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
127 static inline int superio_inb(int ioreg, int reg)
132 val = inb(ioreg + 1);
137 static inline void superio_outb(int ioreg, int reg, int val)
140 outb(val, ioreg + 1);
143 static int superio_inw(int ioreg, int reg)
145 return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
148 static inline void superio_select(int ioreg, int ldn)
151 outb(ldn, ioreg + 1);
154 static inline int superio_enter(int ioreg)
157 * Try to reserve ioreg and ioreg + 1 for exclusive access.
159 if (!request_muxed_region(ioreg, 2, DRVNAME))
162 __superio_enter(ioreg);
166 static inline void superio_exit(int ioreg, bool doexit)
170 outb(0x02, ioreg + 1);
172 release_region(ioreg, 2);
175 /* Logical device 4 registers */
176 #define IT8712F_DEVID 0x8712
177 #define IT8705F_DEVID 0x8705
178 #define IT8716F_DEVID 0x8716
179 #define IT8718F_DEVID 0x8718
180 #define IT8720F_DEVID 0x8720
181 #define IT8721F_DEVID 0x8721
182 #define IT8726F_DEVID 0x8726
183 #define IT8728F_DEVID 0x8728
184 #define IT8732F_DEVID 0x8732
185 #define IT8736F_DEVID 0x8736
186 #define IT8738E_DEVID 0x8738
187 #define IT8792E_DEVID 0x8733
188 #define IT8771E_DEVID 0x8771
189 #define IT8772E_DEVID 0x8772
190 #define IT8781F_DEVID 0x8781
191 #define IT8782F_DEVID 0x8782
192 #define IT8783E_DEVID 0x8783
193 #define IT8786E_DEVID 0x8786
194 #define IT8790E_DEVID 0x8790
195 #define IT8603E_DEVID 0x8603
196 #define IT8606E_DEVID 0x8606
197 #define IT8607E_DEVID 0x8607
198 #define IT8613E_DEVID 0x8613
199 #define IT8620E_DEVID 0x8620
200 #define IT8622E_DEVID 0x8622
201 #define IT8623E_DEVID 0x8623
202 #define IT8625E_DEVID 0x8625
203 #define IT8628E_DEVID 0x8628
204 #define IT8655E_DEVID 0x8655
205 #define IT8665E_DEVID 0x8665
206 #define IT8686E_DEVID 0x8686
208 /* Logical device 4 (Environmental Monitor) registers */
209 #define IT87_ACT_REG 0x30
210 #define IT87_BASE_REG 0x60
211 #define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */
213 /* Global configuration registers (IT8712F and later) */
214 #define IT87_EC_HWM_MIO_REG 0x24 /* MMIO configuration register */
215 #define IT87_SIO_GPIO1_REG 0x25
216 #define IT87_SIO_GPIO2_REG 0x26
217 #define IT87_SIO_GPIO3_REG 0x27
218 #define IT87_SIO_GPIO4_REG 0x28
219 #define IT87_SIO_GPIO5_REG 0x29
220 #define IT87_SIO_GPIO9_REG 0xd3
221 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
222 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
223 #define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
225 /* Logical device 7 (GPIO) registers (IT8712F and later) */
226 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
227 #define IT87_SIO_VID_REG 0xfc /* VID value */
228 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
230 /* Update battery voltage after every reading if true */
231 static bool update_vbat;
233 /* Not all BIOSes properly configure the PWM registers */
234 static bool fix_pwm_polarity;
236 /* Many IT87 constants specified below */
238 /* Length of ISA address segment */
239 #define IT87_EXTENT 8
241 /* Length of ISA address segment for Environmental Controller */
242 #define IT87_EC_EXTENT 2
244 /* Offset of EC registers from ISA base address */
245 #define IT87_EC_OFFSET 5
247 /* Where are the ISA address/data registers relative to the EC base address */
248 #define IT87_ADDR_REG_OFFSET 0
249 #define IT87_DATA_REG_OFFSET 1
251 /*----- The IT87 registers -----*/
253 #define IT87_REG_CONFIG 0x00
255 #define IT87_REG_ALARM1 0x01
256 #define IT87_REG_ALARM2 0x02
257 #define IT87_REG_ALARM3 0x03
259 #define IT87_REG_BANK 0x06
262 * The IT8718F and IT8720F have the VID value in a different register, in
263 * Super-I/O configuration space.
265 #define IT87_REG_VID 0x0a
267 /* Interface Selection register on other chips */
268 #define IT87_REG_IFSEL 0x0a
271 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
272 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
275 #define IT87_REG_FAN_DIV 0x0b
276 #define IT87_REG_FAN_16BIT 0x0c
280 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
281 * - up to 6 temp (1 to 6)
282 * - up to 6 fan (1 to 6)
285 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
286 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
287 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
288 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
290 static const u8 IT87_REG_FAN_8665[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
291 static const u8 IT87_REG_FAN_MIN_8665[] = {
292 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
293 static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
294 static const u8 IT87_REG_FANX_MIN_8665[] = {
295 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
297 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
299 static const u8 IT87_REG_TEMP_OFFSET_8686[] = {
300 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
302 #define IT87_REG_FAN_MAIN_CTRL 0x13
303 #define IT87_REG_FAN_CTL 0x14
305 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
306 static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
308 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
310 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
311 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
313 #define IT87_REG_TEMP(nr) (0x29 + (nr))
315 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
316 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
318 static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
319 static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
321 static const u8 IT87_REG_TEMP_HIGH_8686[] = {
322 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
323 static const u8 IT87_REG_TEMP_LOW_8686[] = {
324 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
326 #define IT87_REG_VIN_ENABLE 0x50
327 #define IT87_REG_TEMP_ENABLE 0x51
328 #define IT87_REG_TEMP_EXTRA 0x55
329 #define IT87_REG_BEEP_ENABLE 0x5c
331 #define IT87_REG_CHIPID 0x58
333 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
335 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
336 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
338 #define IT87_REG_TEMP456_ENABLE 0x77
340 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
341 #define IT87_REG_TEMP_SRC2 0x23d
343 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
344 #define NUM_VIN_LIMIT 8
346 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
347 #define NUM_FAN_DIV 3
348 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
349 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
351 struct it87_devices {
353 const char * const model;
357 u8 num_temp_map; /* Number of temperature sources for pwm */
360 u8 smbus_bitmap; /* SMBus enable bits in extra config register */
361 u8 ec_special_config;
364 #define FEAT_12MV_ADC BIT(0)
365 #define FEAT_NEWER_AUTOPWM BIT(1)
366 #define FEAT_OLD_AUTOPWM BIT(2)
367 #define FEAT_16BIT_FANS BIT(3)
368 #define FEAT_TEMP_PECI BIT(5)
369 #define FEAT_TEMP_OLD_PECI BIT(6)
370 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
371 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
372 #define FEAT_VID BIT(9) /* Set if chip supports VID */
373 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
374 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */
375 #define FEAT_10_9MV_ADC BIT(12)
376 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
377 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
378 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
379 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
380 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
381 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
382 #define FEAT_FOUR_FANS BIT(19) /* Supports four fans */
383 #define FEAT_FOUR_PWM BIT(20) /* Supports four fan controls */
384 #define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */
385 #define FEAT_SCALING BIT(22) /* Internal voltage scaling */
386 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
387 #define FEAT_11MV_ADC BIT(24)
388 #define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
389 #define FEAT_MMIO BIT(26) /* Chip supports MMIO */
390 #define FEAT_FOUR_TEMP BIT(27)
392 static const struct it87_devices it87_devices[] = {
396 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
397 /* may need to overwrite */
399 .num_temp_offset = 0,
405 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
406 /* may need to overwrite */
408 .num_temp_offset = 0,
414 .features = FEAT_16BIT_FANS | FEAT_VID
415 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
418 .num_temp_offset = 3,
424 .features = FEAT_16BIT_FANS | FEAT_VID
425 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
426 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
428 .num_temp_offset = 3,
430 .old_peci_mask = 0x4,
435 .features = FEAT_16BIT_FANS | FEAT_VID
436 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
437 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
439 .num_temp_offset = 3,
441 .old_peci_mask = 0x4,
446 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
447 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
448 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
449 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
451 .num_temp_offset = 3,
454 .old_peci_mask = 0x02, /* Actually reports PCH */
459 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
460 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
461 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
464 .num_temp_offset = 3,
471 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
472 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
473 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
474 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF | FEAT_SCALING,
476 .num_temp_offset = 3,
479 .old_peci_mask = 0x02, /* Actually reports PCH */
484 .features = FEAT_16BIT_FANS
485 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
486 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
487 | FEAT_FANCTL_ONOFF | FEAT_SCALING,
489 .num_temp_offset = 3,
492 .old_peci_mask = 0x02, /* Actually reports PCH */
497 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
498 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
499 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL
500 | FEAT_FANCTL_ONOFF | FEAT_SCALING
503 .num_temp_offset = 3,
506 .old_peci_mask = 0x02,
511 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
512 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
513 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
514 /* PECI: guesswork */
516 /* 16 bit fans (OHM) */
517 /* three fans, always 16 bit (guesswork) */
519 .num_temp_offset = 3,
526 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
527 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
528 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
529 /* PECI (coreboot) */
530 /* 12mV ADC (HWSensors4, OHM) */
531 /* 16 bit fans (HWSensors4, OHM) */
532 /* three fans, always 16 bit (datasheet) */
534 .num_temp_offset = 3,
541 .features = FEAT_16BIT_FANS
542 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
545 .num_temp_offset = 3,
547 .old_peci_mask = 0x4,
552 .features = FEAT_16BIT_FANS
553 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
556 .num_temp_offset = 3,
558 .old_peci_mask = 0x4,
562 .model = "IT8783E/F",
563 .features = FEAT_16BIT_FANS
564 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
567 .num_temp_offset = 3,
569 .old_peci_mask = 0x4,
574 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
575 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
576 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
578 .num_temp_offset = 3,
585 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
586 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
587 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
589 .num_temp_offset = 3,
595 .model = "IT8792E/IT8795E",
596 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
597 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
598 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
600 .num_temp_offset = 3,
607 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
608 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
609 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
611 .num_temp_offset = 3,
618 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
619 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
620 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
622 .num_temp_offset = 3,
629 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
630 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
631 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
634 .num_temp_offset = 3,
641 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
642 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
643 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
644 | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
646 .num_temp_offset = 6,
653 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
654 | FEAT_TEMP_PECI | FEAT_SIX_FANS
655 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
656 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
659 .num_temp_offset = 3,
666 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
667 | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
668 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
669 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
671 .num_temp_offset = 3,
674 .smbus_bitmap = BIT(1) | BIT(2),
679 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
680 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
681 | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
682 | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
684 .num_temp_offset = 6,
686 .smbus_bitmap = BIT(1) | BIT(2),
691 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
692 | FEAT_TEMP_PECI | FEAT_SIX_FANS
693 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
694 | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
697 .num_temp_offset = 3,
704 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
705 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
706 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
707 | FEAT_SIX_TEMP | FEAT_MMIO,
709 .num_temp_offset = 6,
711 .smbus_bitmap = BIT(2),
716 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
717 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
718 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
719 | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO | FEAT_SIX_TEMP,
721 .num_temp_offset = 6,
723 .smbus_bitmap = BIT(2),
728 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
729 | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
730 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
731 | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
733 .num_temp_offset = 6,
735 .smbus_bitmap = BIT(1) | BIT(2),
739 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
740 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
741 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
742 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
743 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
744 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
745 ((data)->peci_mask & BIT(nr)))
746 #define has_temp_old_peci(data, nr) \
747 (((data)->features & FEAT_TEMP_OLD_PECI) && \
748 ((data)->old_peci_mask & BIT(nr)))
749 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
750 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
752 #define has_vid(data) ((data)->features & FEAT_VID)
753 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
754 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
755 #define has_avcc3(data) ((data)->features & FEAT_AVCC3)
756 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
758 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
759 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
760 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
761 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
762 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
765 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
768 #define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL)
769 #define has_scaling(data) ((data)->features & FEAT_SCALING)
770 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
771 #define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
772 #define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
773 #define has_mmio(data) ((data)->features & FEAT_MMIO)
774 #define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP)
776 struct it87_sio_data {
780 /* Values read from Super-I/O config space */
784 u8 internal; /* Internal sensors can be labeled */
785 /* Features skipped based on config or DMI */
792 u8 ec_special_config;
796 * For each registered chip, we need to keep some data in memory.
797 * The structure is dynamically allocated.
800 const struct attribute_group *groups[7];
806 u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
807 u8 saved_bank; /* saved bank register value */
808 u8 ec_special_config; /* EC special config register restore value */
809 u8 sioaddr; /* SIO port address */
810 bool doexit; /* true if exit from sio config is ok */
812 void __iomem *mmio; /* Remapped MMIO address if available */
813 int (*read)(struct it87_data *, u16);
814 void (*write)(struct it87_data *, u16, u8);
818 const u8 *REG_FAN_MIN;
819 const u8 *REG_FANX_MIN;
823 const u8 *REG_TEMP_OFFSET;
824 const u8 *REG_TEMP_LOW;
825 const u8 *REG_TEMP_HIGH;
828 struct mutex update_lock;
829 char valid; /* !=0 if following fields are valid */
830 unsigned long last_updated; /* In jiffies */
832 u16 in_scaled; /* Internal voltage sensors are scaled */
833 u16 in_internal; /* Bitfield, internal sensors (for labels) */
834 u16 has_in; /* Bitfield, voltage sensors enabled */
835 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
836 u8 has_fan; /* Bitfield, fans enabled */
837 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
838 u8 has_temp; /* Bitfield, temp sensors enabled */
839 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
840 u8 num_temp_limit; /* Number of temperature limit registers */
841 u8 num_temp_offset; /* Number of temperature offset registers */
842 u8 temp_src[4]; /* Up to 4 temperature source registers */
843 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
844 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
845 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
846 bool has_vid; /* True if VID supported */
847 u8 vid; /* Register encoding, combined */
849 u32 alarms; /* Register encoding, combined */
850 bool has_beep; /* true if beep supported */
851 u8 beeps; /* Register encoding */
852 u8 fan_main_ctrl; /* Register value */
853 u8 fan_ctl; /* Register value */
856 * The following 3 arrays correspond to the same registers up to
857 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
858 * 7, and we want to preserve settings on mode changes, so we have
859 * to track all values separately.
860 * Starting with the IT8721F, the manual PWM duty cycles are stored
861 * in separate registers (8-bit values), so the separate tracking
862 * is no longer needed, but it is still done to keep the driver
865 u8 has_pwm; /* Bitfield, pwm control enabled */
866 u8 pwm_ctrl[NUM_PWM]; /* Register value */
867 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
868 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
869 u8 pwm_temp_map_mask; /* 0x03 for old, 0x07 for new temp map */
870 u8 pwm_temp_map_shift; /* 0 for old, 3 for new temp map */
871 u8 pwm_num_temp_map; /* from config data, 3..7 depending on chip */
873 /* Automatic fan speed control registers */
874 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
875 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
878 static int adc_lsb(const struct it87_data *data, int nr)
882 if (has_12mv_adc(data))
884 else if (has_10_9mv_adc(data))
886 else if (has_11mv_adc(data))
890 if (data->in_scaled & BIT(nr))
895 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
897 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
898 return clamp_val(val, 0, 255);
901 static int in_from_reg(const struct it87_data *data, int nr, int val)
903 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
906 static inline u8 FAN_TO_REG(long rpm, int div)
910 rpm = clamp_val(rpm, 1, 1000000);
911 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
914 static inline u16 FAN16_TO_REG(long rpm)
918 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
921 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
922 1350000 / ((val) * (div)))
923 /* The divider is fixed to 2 in 16-bit mode */
924 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
925 1350000 / ((val) * 2))
927 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
928 ((val) + 500) / 1000), -128, 127))
929 #define TEMP_FROM_REG(val) ((val) * 1000)
931 static u8 pwm_to_reg(const struct it87_data *data, long val)
933 if (has_newer_autopwm(data))
939 static int pwm_from_reg(const struct it87_data *data, u8 reg)
941 if (has_newer_autopwm(data))
944 return (reg & 0x7f) << 1;
947 static int DIV_TO_REG(int val)
951 while (answer < 7 && (val >>= 1))
956 #define DIV_FROM_REG(val) BIT(val)
958 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
962 map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
963 if (map >= data->pwm_num_temp_map) /* map is 0-based */
969 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
971 u8 ctrl = data->pwm_ctrl[nr];
973 return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
974 (map << data->pwm_temp_map_shift);
978 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
979 * depending on the chip type, to calculate the actual PWM frequency.
981 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
982 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
983 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
984 * sometimes just one. It is unknown if this is a datasheet error or real,
985 * so this is ignored for now.
987 static const unsigned int pwm_freq[8] = {
998 static int _it87_io_read(struct it87_data *data, u16 reg)
1000 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1001 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1004 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
1006 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1007 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1010 static int smbus_disable(struct it87_data *data)
1014 if (data->smbus_bitmap) {
1015 err = superio_enter(data->sioaddr);
1018 superio_select(data->sioaddr, PME);
1019 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
1020 data->ec_special_config & ~data->smbus_bitmap);
1021 superio_exit(data->sioaddr, data->doexit);
1022 if (has_bank_sel(data) && !data->mmio)
1023 data->saved_bank = _it87_io_read(data, IT87_REG_BANK);
1028 static int smbus_enable(struct it87_data *data)
1032 if (data->smbus_bitmap) {
1033 if (has_bank_sel(data) && !data->mmio)
1034 _it87_io_write(data, IT87_REG_BANK, data->saved_bank);
1035 err = superio_enter(data->sioaddr);
1039 superio_select(data->sioaddr, PME);
1040 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
1041 data->ec_special_config);
1042 superio_exit(data->sioaddr, data->doexit);
1047 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
1051 if (has_bank_sel(data)) {
1052 u8 breg = _it87_io_read(data, IT87_REG_BANK);
1055 if (bank != _bank) {
1057 breg |= (bank << 5);
1058 _it87_io_write(data, IT87_REG_BANK, breg);
1065 * Must be called with data->update_lock held, except during initialization.
1066 * Must be called with SMBus accesses disabled.
1067 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1068 * would slow down the IT87 access and should not be necessary.
1070 static int it87_io_read(struct it87_data *data, u16 reg)
1075 bank = it87_io_set_bank(data, reg >> 8);
1076 val = _it87_io_read(data, reg & 0xff);
1077 it87_io_set_bank(data, bank);
1083 * Must be called with data->update_lock held, except during initialization.
1084 * Must be called with SMBus accesses disabled
1085 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1086 * would slow down the IT87 access and should not be necessary.
1088 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1092 bank = it87_io_set_bank(data, reg >> 8);
1093 _it87_io_write(data, reg & 0xff, value);
1094 it87_io_set_bank(data, bank);
1097 static int it87_mmio_read(struct it87_data *data, u16 reg)
1099 return readb(data->mmio + reg);
1102 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1104 writeb(value, data->mmio + reg);
1107 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1111 ctrl = data->read(data, data->REG_PWM[nr]);
1112 data->pwm_ctrl[nr] = ctrl;
1113 if (has_newer_autopwm(data)) {
1114 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1115 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1117 if (ctrl & 0x80) /* Automatic mode */
1118 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1119 else /* Manual mode */
1120 data->pwm_duty[nr] = ctrl & 0x7f;
1123 if (has_old_autopwm(data)) {
1126 for (i = 0; i < 5 ; i++)
1127 data->auto_temp[nr][i] = data->read(data,
1128 IT87_REG_AUTO_TEMP(nr, i));
1129 for (i = 0; i < 3 ; i++)
1130 data->auto_pwm[nr][i] = data->read(data,
1131 IT87_REG_AUTO_PWM(nr, i));
1132 } else if (has_newer_autopwm(data)) {
1136 * 0: temperature hysteresis (base + 5)
1137 * 1: fan off temperature (base + 0)
1138 * 2: fan start temperature (base + 1)
1139 * 3: fan max temperature (base + 2)
1141 data->auto_temp[nr][0] =
1142 data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1144 for (i = 0; i < 3 ; i++)
1145 data->auto_temp[nr][i + 1] =
1146 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1148 * 0: start pwm value (base + 3)
1149 * 1: pwm slope (base + 4, 1/8th pwm)
1151 data->auto_pwm[nr][0] =
1152 data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1153 data->auto_pwm[nr][1] =
1154 data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1158 static int it87_lock(struct it87_data *data)
1162 mutex_lock(&data->update_lock);
1163 err = smbus_disable(data);
1165 mutex_unlock(&data->update_lock);
1169 static void it87_unlock(struct it87_data *data)
1172 mutex_unlock(&data->update_lock);
1175 static struct it87_data *it87_update_device(struct device *dev)
1177 struct it87_data *data = dev_get_drvdata(dev);
1178 struct it87_data *ret = data;
1182 mutex_lock(&data->update_lock);
1184 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1186 err = smbus_disable(data);
1193 * Cleared after each update, so reenable. Value
1194 * returned by this read will be previous value
1196 data->write(data, IT87_REG_CONFIG,
1197 data->read(data, IT87_REG_CONFIG) | 0x40);
1199 for (i = 0; i < NUM_VIN; i++) {
1200 if (!(data->has_in & BIT(i)))
1203 data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1205 /* VBAT and AVCC don't have limit registers */
1206 if (i >= NUM_VIN_LIMIT)
1209 data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1210 data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1213 for (i = 0; i < NUM_FAN; i++) {
1214 /* Skip disabled fans */
1215 if (!(data->has_fan & BIT(i)))
1218 data->fan[i][1] = data->read(data,
1219 data->REG_FAN_MIN[i]);
1220 data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1221 /* Add high byte if in 16-bit mode */
1222 if (has_16bit_fans(data)) {
1223 data->fan[i][0] |= data->read(data,
1224 data->REG_FANX[i]) << 8;
1225 data->fan[i][1] |= data->read(data,
1226 data->REG_FANX_MIN[i]) << 8;
1229 for (i = 0; i < NUM_TEMP; i++) {
1230 if (!(data->has_temp & BIT(i)))
1233 data->read(data, IT87_REG_TEMP(i));
1235 if (i >= data->num_temp_limit)
1238 if (i < data->num_temp_offset)
1240 data->read(data, data->REG_TEMP_OFFSET[i]);
1243 data->read(data, data->REG_TEMP_LOW[i]);
1245 data->read(data, data->REG_TEMP_HIGH[i]);
1248 /* Newer chips don't have clock dividers */
1249 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1250 i = data->read(data, IT87_REG_FAN_DIV);
1251 data->fan_div[0] = i & 0x07;
1252 data->fan_div[1] = (i >> 3) & 0x07;
1253 data->fan_div[2] = (i & 0x40) ? 3 : 1;
1257 data->read(data, IT87_REG_ALARM1) |
1258 (data->read(data, IT87_REG_ALARM2) << 8) |
1259 (data->read(data, IT87_REG_ALARM3) << 16);
1260 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1262 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1263 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1264 for (i = 0; i < NUM_PWM; i++) {
1265 if (!(data->has_pwm & BIT(i)))
1267 it87_update_pwm_ctrl(data, i);
1270 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1271 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1273 * The IT8705F does not have VID capability.
1274 * The IT8718F and later don't use IT87_REG_VID for the
1277 if (data->type == it8712 || data->type == it8716) {
1278 data->vid = data->read(data, IT87_REG_VID);
1280 * The older IT8712F revisions had only 5 VID pins,
1281 * but we assume it is always safe to read 6 bits.
1285 data->last_updated = jiffies;
1290 mutex_unlock(&data->update_lock);
1294 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1297 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1298 struct it87_data *data = it87_update_device(dev);
1299 int index = sattr->index;
1303 return PTR_ERR(data);
1305 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1308 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1309 const char *buf, size_t count)
1311 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1312 struct it87_data *data = dev_get_drvdata(dev);
1313 int index = sattr->index;
1318 if (kstrtoul(buf, 10, &val) < 0)
1321 err = it87_lock(data);
1325 data->in[nr][index] = in_to_reg(data, nr, val);
1326 data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1327 : IT87_REG_VIN_MAX(nr),
1328 data->in[nr][index]);
1333 static SENSOR_DEVICE_ATTR_2(in0_input, 0444, show_in, NULL, 0, 0);
1334 static SENSOR_DEVICE_ATTR_2(in0_min, 0644, show_in, set_in, 0, 1);
1335 static SENSOR_DEVICE_ATTR_2(in0_max, 0644, show_in, set_in, 0, 2);
1337 static SENSOR_DEVICE_ATTR_2(in1_input, 0444, show_in, NULL, 1, 0);
1338 static SENSOR_DEVICE_ATTR_2(in1_min, 0644, show_in, set_in, 1, 1);
1339 static SENSOR_DEVICE_ATTR_2(in1_max, 0644, show_in, set_in, 1, 2);
1341 static SENSOR_DEVICE_ATTR_2(in2_input, 0444, show_in, NULL, 2, 0);
1342 static SENSOR_DEVICE_ATTR_2(in2_min, 0644, show_in, set_in, 2, 1);
1343 static SENSOR_DEVICE_ATTR_2(in2_max, 0644, show_in, set_in, 2, 2);
1345 static SENSOR_DEVICE_ATTR_2(in3_input, 0444, show_in, NULL, 3, 0);
1346 static SENSOR_DEVICE_ATTR_2(in3_min, 0644, show_in, set_in, 3, 1);
1347 static SENSOR_DEVICE_ATTR_2(in3_max, 0644, show_in, set_in, 3, 2);
1349 static SENSOR_DEVICE_ATTR_2(in4_input, 0444, show_in, NULL, 4, 0);
1350 static SENSOR_DEVICE_ATTR_2(in4_min, 0644, show_in, set_in, 4, 1);
1351 static SENSOR_DEVICE_ATTR_2(in4_max, 0644, show_in, set_in, 4, 2);
1353 static SENSOR_DEVICE_ATTR_2(in5_input, 0444, show_in, NULL, 5, 0);
1354 static SENSOR_DEVICE_ATTR_2(in5_min, 0644, show_in, set_in, 5, 1);
1355 static SENSOR_DEVICE_ATTR_2(in5_max, 0644, show_in, set_in, 5, 2);
1357 static SENSOR_DEVICE_ATTR_2(in6_input, 0444, show_in, NULL, 6, 0);
1358 static SENSOR_DEVICE_ATTR_2(in6_min, 0644, show_in, set_in, 6, 1);
1359 static SENSOR_DEVICE_ATTR_2(in6_max, 0644, show_in, set_in, 6, 2);
1361 static SENSOR_DEVICE_ATTR_2(in7_input, 0444, show_in, NULL, 7, 0);
1362 static SENSOR_DEVICE_ATTR_2(in7_min, 0644, show_in, set_in, 7, 1);
1363 static SENSOR_DEVICE_ATTR_2(in7_max, 0644, show_in, set_in, 7, 2);
1365 static SENSOR_DEVICE_ATTR_2(in8_input, 0444, show_in, NULL, 8, 0);
1366 static SENSOR_DEVICE_ATTR_2(in9_input, 0444, show_in, NULL, 9, 0);
1367 static SENSOR_DEVICE_ATTR_2(in10_input, 0444, show_in, NULL, 10, 0);
1368 static SENSOR_DEVICE_ATTR_2(in11_input, 0444, show_in, NULL, 11, 0);
1369 static SENSOR_DEVICE_ATTR_2(in12_input, 0444, show_in, NULL, 12, 0);
1371 /* Up to 6 temperatures */
1372 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1375 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1377 int index = sattr->index;
1378 struct it87_data *data = it87_update_device(dev);
1381 return PTR_ERR(data);
1383 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1386 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1387 const char *buf, size_t count)
1389 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1391 int index = sattr->index;
1392 struct it87_data *data = dev_get_drvdata(dev);
1397 if (kstrtol(buf, 10, &val) < 0)
1400 err = it87_lock(data);
1407 reg = data->REG_TEMP_LOW[nr];
1410 reg = data->REG_TEMP_HIGH[nr];
1413 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1414 if (!(regval & 0x80)) {
1416 data->write(data, IT87_REG_BEEP_ENABLE, regval);
1419 reg = data->REG_TEMP_OFFSET[nr];
1423 data->temp[nr][index] = TEMP_TO_REG(val);
1424 data->write(data, reg, data->temp[nr][index]);
1429 static SENSOR_DEVICE_ATTR_2(temp1_input, 0444, show_temp, NULL, 0, 0);
1430 static SENSOR_DEVICE_ATTR_2(temp1_min, 0644, show_temp, set_temp, 0, 1);
1431 static SENSOR_DEVICE_ATTR_2(temp1_max, 0644, show_temp, set_temp, 0, 2);
1432 static SENSOR_DEVICE_ATTR_2(temp1_offset, 0644, show_temp, set_temp, 0, 3);
1433 static SENSOR_DEVICE_ATTR_2(temp2_input, 0444, show_temp, NULL, 1, 0);
1434 static SENSOR_DEVICE_ATTR_2(temp2_min, 0644, show_temp, set_temp, 1, 1);
1435 static SENSOR_DEVICE_ATTR_2(temp2_max, 0644, show_temp, set_temp, 1, 2);
1436 static SENSOR_DEVICE_ATTR_2(temp2_offset, 0644, show_temp, set_temp, 1, 3);
1437 static SENSOR_DEVICE_ATTR_2(temp3_input, 0444, show_temp, NULL, 2, 0);
1438 static SENSOR_DEVICE_ATTR_2(temp3_min, 0644, show_temp, set_temp, 2, 1);
1439 static SENSOR_DEVICE_ATTR_2(temp3_max, 0644, show_temp, set_temp, 2, 2);
1440 static SENSOR_DEVICE_ATTR_2(temp3_offset, 0644, show_temp, set_temp, 2, 3);
1441 static SENSOR_DEVICE_ATTR_2(temp4_input, 0444, show_temp, NULL, 3, 0);
1442 static SENSOR_DEVICE_ATTR_2(temp4_min, 0644, show_temp, set_temp, 3, 1);
1443 static SENSOR_DEVICE_ATTR_2(temp4_max, 0644, show_temp, set_temp, 3, 2);
1444 static SENSOR_DEVICE_ATTR_2(temp4_offset, 0644, show_temp, set_temp, 3, 3);
1445 static SENSOR_DEVICE_ATTR_2(temp5_input, 0444, show_temp, NULL, 4, 0);
1446 static SENSOR_DEVICE_ATTR_2(temp5_min, 0644, show_temp, set_temp, 4, 1);
1447 static SENSOR_DEVICE_ATTR_2(temp5_max, 0644, show_temp, set_temp, 4, 2);
1448 static SENSOR_DEVICE_ATTR_2(temp5_offset, 0644, show_temp, set_temp, 4, 3);
1449 static SENSOR_DEVICE_ATTR_2(temp6_input, 0444, show_temp, NULL, 5, 0);
1450 static SENSOR_DEVICE_ATTR_2(temp6_min, 0644, show_temp, set_temp, 5, 1);
1451 static SENSOR_DEVICE_ATTR_2(temp6_max, 0644, show_temp, set_temp, 5, 2);
1452 static SENSOR_DEVICE_ATTR_2(temp6_offset, 0644, show_temp, set_temp, 5, 3);
1454 static const u8 temp_types_8686[NUM_TEMP][9] = {
1455 { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1456 { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1457 { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1458 { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1459 { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1460 { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1463 static int get_temp_type(struct it87_data *data, int index)
1466 int ttype, type = 0;
1468 if (has_bank_sel(data)) {
1471 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1473 switch (data->type) {
1476 type = temp_types_8686[index][src1];
1487 src2 = data->temp_src[3];
1490 type = (src2 & BIT(index)) ? 6 : 5;
1493 type = (src2 & BIT(index)) ? 4 : 6;
1496 type = (src2 & BIT(index)) ? 5 : 0;
1509 /* Dectect PECI vs. AMDTSI */
1511 if ((has_temp_peci(data, index)) || data->type == it8721 ||
1512 data->type == it8720) {
1513 extra = data->read(data, IT87_REG_IFSEL);
1514 if ((extra & 0x70) == 0x40)
1518 reg = data->read(data, IT87_REG_TEMP_ENABLE);
1520 /* Per chip special detection */
1521 switch (data->type) {
1523 if (!(reg & 0xc0) && index == 3)
1530 if (type || index >= 3)
1533 extra = data->read(data, IT87_REG_TEMP_EXTRA);
1535 if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1536 (has_temp_old_peci(data, index) && (extra & 0x80)))
1537 type = ttype; /* Intel PECI or AMDTSI */
1538 else if (reg & BIT(index))
1539 type = 3; /* thermal diode */
1540 else if (reg & BIT(index + 3))
1541 type = 4; /* thermistor */
1546 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1549 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1550 struct it87_data *data = it87_update_device(dev);
1554 return PTR_ERR(data);
1556 type = get_temp_type(data, sensor_attr->index);
1557 return sprintf(buf, "%d\n", type);
1560 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1561 const char *buf, size_t count)
1563 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1564 int nr = sensor_attr->index;
1566 struct it87_data *data = dev_get_drvdata(dev);
1571 if (kstrtol(buf, 10, &val) < 0)
1574 err = it87_lock(data);
1578 reg = data->read(data, IT87_REG_TEMP_ENABLE);
1581 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1583 extra = data->read(data, IT87_REG_TEMP_EXTRA);
1584 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1586 if (val == 2) { /* backwards compatibility */
1588 "Sensor type 2 is deprecated, please use 4 instead\n");
1591 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1596 else if (has_temp_peci(data, nr) && val == 6)
1597 reg |= (nr + 1) << 6;
1598 else if (has_temp_old_peci(data, nr) && val == 6)
1600 else if (val != 0) {
1606 data->extra = extra;
1607 data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1608 if (has_temp_old_peci(data, nr))
1609 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1610 data->valid = 0; /* Force cache refresh */
1616 static SENSOR_DEVICE_ATTR(temp1_type, 0644, show_temp_type, set_temp_type, 0);
1617 static SENSOR_DEVICE_ATTR(temp2_type, 0644, show_temp_type, set_temp_type, 1);
1618 static SENSOR_DEVICE_ATTR(temp3_type, 0644, show_temp_type, set_temp_type, 2);
1619 static SENSOR_DEVICE_ATTR(temp4_type, 0644, show_temp_type, set_temp_type, 3);
1620 static SENSOR_DEVICE_ATTR(temp5_type, 0644, show_temp_type, set_temp_type, 4);
1621 static SENSOR_DEVICE_ATTR(temp6_type, 0644, show_temp_type, set_temp_type, 5);
1625 static int pwm_mode(const struct it87_data *data, int nr)
1627 if (has_fanctl_onoff(data) && nr < 3 &&
1628 !(data->fan_main_ctrl & BIT(nr)))
1629 return 0; /* Full speed */
1630 if (data->pwm_ctrl[nr] & 0x80)
1631 return 2; /* Automatic mode */
1632 if ((!has_fanctl_onoff(data) || nr >= 3) &&
1633 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1634 return 0; /* Full speed */
1636 return 1; /* Manual mode */
1639 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1642 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1644 int index = sattr->index;
1646 struct it87_data *data = it87_update_device(dev);
1649 return PTR_ERR(data);
1651 speed = has_16bit_fans(data) ?
1652 FAN16_FROM_REG(data->fan[nr][index]) :
1653 FAN_FROM_REG(data->fan[nr][index],
1654 DIV_FROM_REG(data->fan_div[nr]));
1655 return sprintf(buf, "%d\n", speed);
1658 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1661 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1662 struct it87_data *data = it87_update_device(dev);
1663 int nr = sensor_attr->index;
1666 return PTR_ERR(data);
1668 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1671 static ssize_t show_pwm_enable(struct device *dev,
1672 struct device_attribute *attr, char *buf)
1674 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1675 struct it87_data *data = it87_update_device(dev);
1676 int nr = sensor_attr->index;
1679 return PTR_ERR(data);
1681 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1684 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1687 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1688 struct it87_data *data = it87_update_device(dev);
1689 int nr = sensor_attr->index;
1692 return PTR_ERR(data);
1694 return sprintf(buf, "%d\n",
1695 pwm_from_reg(data, data->pwm_duty[nr]));
1698 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1701 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1702 struct it87_data *data = it87_update_device(dev);
1703 int nr = sensor_attr->index;
1708 return PTR_ERR(data);
1710 if (has_pwm_freq2(data) && nr == 1)
1711 index = (data->extra >> 4) & 0x07;
1713 index = (data->fan_ctl >> 4) & 0x07;
1715 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1717 return sprintf(buf, "%u\n", freq);
1720 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1721 const char *buf, size_t count)
1723 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1725 int index = sattr->index;
1727 struct it87_data *data = dev_get_drvdata(dev);
1732 if (kstrtol(buf, 10, &val) < 0)
1735 err = it87_lock(data);
1739 if (has_16bit_fans(data)) {
1740 data->fan[nr][index] = FAN16_TO_REG(val);
1741 data->write(data, data->REG_FAN_MIN[nr],
1742 data->fan[nr][index] & 0xff);
1743 data->write(data, data->REG_FANX_MIN[nr],
1744 data->fan[nr][index] >> 8);
1746 reg = data->read(data, IT87_REG_FAN_DIV);
1749 data->fan_div[nr] = reg & 0x07;
1752 data->fan_div[nr] = (reg >> 3) & 0x07;
1755 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1758 data->fan[nr][index] =
1759 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1760 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1766 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1767 const char *buf, size_t count)
1769 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1770 struct it87_data *data = dev_get_drvdata(dev);
1771 int nr = sensor_attr->index;
1776 if (kstrtoul(buf, 10, &val) < 0)
1779 err = it87_lock(data);
1783 old = data->read(data, IT87_REG_FAN_DIV);
1785 /* Save fan min limit */
1786 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1791 data->fan_div[nr] = DIV_TO_REG(val);
1795 data->fan_div[nr] = 1;
1797 data->fan_div[nr] = 3;
1800 val |= (data->fan_div[0] & 0x07);
1801 val |= (data->fan_div[1] & 0x07) << 3;
1802 if (data->fan_div[2] == 3)
1804 data->write(data, IT87_REG_FAN_DIV, val);
1806 /* Restore fan min limit */
1807 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1808 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1813 /* Returns 0 if OK, -EINVAL otherwise */
1814 static int check_trip_points(struct device *dev, int nr)
1816 const struct it87_data *data = dev_get_drvdata(dev);
1819 if (has_old_autopwm(data)) {
1820 for (i = 0; i < 3; i++) {
1821 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1824 for (i = 0; i < 2; i++) {
1825 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1828 } else if (has_newer_autopwm(data)) {
1829 for (i = 1; i < 3; i++) {
1830 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1837 "Inconsistent trip points, not switching to automatic mode\n");
1838 dev_err(dev, "Adjust the trip points and try again\n");
1843 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1844 const char *buf, size_t count)
1846 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1847 struct it87_data *data = dev_get_drvdata(dev);
1848 int nr = sensor_attr->index;
1852 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1855 /* Check trip points before switching to automatic mode */
1857 if (check_trip_points(dev, nr) < 0)
1861 err = it87_lock(data);
1865 it87_update_pwm_ctrl(data, nr);
1868 if (nr < 3 && has_fanctl_onoff(data)) {
1870 /* make sure the fan is on when in on/off mode */
1871 tmp = data->read(data, IT87_REG_FAN_CTL);
1872 data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1873 /* set on/off mode */
1874 data->fan_main_ctrl &= ~BIT(nr);
1875 data->write(data, IT87_REG_FAN_MAIN_CTRL,
1876 data->fan_main_ctrl);
1880 /* No on/off mode, set maximum pwm value */
1881 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1882 data->write(data, IT87_REG_PWM_DUTY[nr],
1883 data->pwm_duty[nr]);
1884 /* and set manual mode */
1885 if (has_newer_autopwm(data)) {
1886 ctrl = temp_map_to_reg(data, nr,
1887 data->pwm_temp_map[nr]);
1890 ctrl = data->pwm_duty[nr];
1892 data->pwm_ctrl[nr] = ctrl;
1893 data->write(data, data->REG_PWM[nr], ctrl);
1898 if (has_newer_autopwm(data)) {
1899 ctrl = temp_map_to_reg(data, nr,
1900 data->pwm_temp_map[nr]);
1906 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1908 data->pwm_ctrl[nr] = ctrl;
1909 data->write(data, data->REG_PWM[nr], ctrl);
1911 if (has_fanctl_onoff(data) && nr < 3) {
1912 /* set SmartGuardian mode */
1913 data->fan_main_ctrl |= BIT(nr);
1914 data->write(data, IT87_REG_FAN_MAIN_CTRL,
1915 data->fan_main_ctrl);
1922 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1923 const char *buf, size_t count)
1925 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1926 struct it87_data *data = dev_get_drvdata(dev);
1927 int nr = sensor_attr->index;
1931 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1934 err = it87_lock(data);
1938 it87_update_pwm_ctrl(data, nr);
1939 if (has_newer_autopwm(data)) {
1941 * If we are in automatic mode, the PWM duty cycle register
1942 * is read-only so we can't write the value.
1944 if (data->pwm_ctrl[nr] & 0x80) {
1948 data->pwm_duty[nr] = pwm_to_reg(data, val);
1949 data->write(data, IT87_REG_PWM_DUTY[nr],
1950 data->pwm_duty[nr]);
1952 data->pwm_duty[nr] = pwm_to_reg(data, val);
1954 * If we are in manual mode, write the duty cycle immediately;
1955 * otherwise, just store it for later use.
1957 if (!(data->pwm_ctrl[nr] & 0x80)) {
1958 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1959 data->write(data, data->REG_PWM[nr],
1960 data->pwm_ctrl[nr]);
1968 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1969 const char *buf, size_t count)
1971 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1972 struct it87_data *data = dev_get_drvdata(dev);
1973 int nr = sensor_attr->index;
1978 if (kstrtoul(buf, 10, &val) < 0)
1981 val = clamp_val(val, 0, 1000000);
1982 val *= has_newer_autopwm(data) ? 256 : 128;
1984 /* Search for the nearest available frequency */
1985 for (i = 0; i < ARRAY_SIZE(pwm_freq) - 1; i++) {
1986 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1990 err = it87_lock(data);
1995 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1996 data->fan_ctl |= i << 4;
1997 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1999 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
2000 data->extra |= i << 4;
2001 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
2007 static ssize_t show_pwm_temp_map(struct device *dev,
2008 struct device_attribute *attr, char *buf)
2010 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2011 struct it87_data *data = it87_update_device(dev);
2012 int nr = sensor_attr->index;
2015 return PTR_ERR(data);
2017 return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
2020 static ssize_t set_pwm_temp_map(struct device *dev,
2021 struct device_attribute *attr, const char *buf,
2024 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2025 struct it87_data *data = dev_get_drvdata(dev);
2026 int nr = sensor_attr->index;
2031 if (kstrtoul(buf, 10, &val) < 0)
2034 if (!val || val > data->pwm_num_temp_map)
2039 err = it87_lock(data);
2043 it87_update_pwm_ctrl(data, nr);
2044 data->pwm_temp_map[nr] = map;
2046 * If we are in automatic mode, write the temp mapping immediately;
2047 * otherwise, just store it for later use.
2049 if (data->pwm_ctrl[nr] & 0x80) {
2050 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2051 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2057 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2060 struct it87_data *data = it87_update_device(dev);
2061 struct sensor_device_attribute_2 *sensor_attr =
2062 to_sensor_dev_attr_2(attr);
2063 int nr = sensor_attr->nr;
2064 int point = sensor_attr->index;
2067 return PTR_ERR(data);
2069 return sprintf(buf, "%d\n",
2070 pwm_from_reg(data, data->auto_pwm[nr][point]));
2073 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2074 const char *buf, size_t count)
2076 struct it87_data *data = dev_get_drvdata(dev);
2077 struct sensor_device_attribute_2 *sensor_attr =
2078 to_sensor_dev_attr_2(attr);
2079 int nr = sensor_attr->nr;
2080 int point = sensor_attr->index;
2085 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2088 err = it87_lock(data);
2092 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2093 if (has_newer_autopwm(data))
2094 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2096 regaddr = IT87_REG_AUTO_PWM(nr, point);
2097 data->write(data, regaddr, data->auto_pwm[nr][point]);
2102 static ssize_t show_auto_pwm_slope(struct device *dev,
2103 struct device_attribute *attr, char *buf)
2105 struct it87_data *data = it87_update_device(dev);
2106 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2107 int nr = sensor_attr->index;
2110 return PTR_ERR(data);
2112 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2115 static ssize_t set_auto_pwm_slope(struct device *dev,
2116 struct device_attribute *attr,
2117 const char *buf, size_t count)
2119 struct it87_data *data = dev_get_drvdata(dev);
2120 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2121 int nr = sensor_attr->index;
2125 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2128 err = it87_lock(data);
2132 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2133 data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2138 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2141 struct it87_data *data = it87_update_device(dev);
2142 struct sensor_device_attribute_2 *sensor_attr =
2143 to_sensor_dev_attr_2(attr);
2144 int nr = sensor_attr->nr;
2145 int point = sensor_attr->index;
2149 return PTR_ERR(data);
2151 if (has_old_autopwm(data) || point)
2152 reg = data->auto_temp[nr][point];
2154 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2156 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2159 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2160 const char *buf, size_t count)
2162 struct it87_data *data = dev_get_drvdata(dev);
2163 struct sensor_device_attribute_2 *sensor_attr =
2164 to_sensor_dev_attr_2(attr);
2165 int nr = sensor_attr->nr;
2166 int point = sensor_attr->index;
2171 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2174 err = it87_lock(data);
2178 if (has_newer_autopwm(data) && !point) {
2179 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2180 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2181 data->auto_temp[nr][0] = reg;
2182 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2184 reg = TEMP_TO_REG(val);
2185 data->auto_temp[nr][point] = reg;
2186 if (has_newer_autopwm(data))
2188 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2194 static SENSOR_DEVICE_ATTR_2(fan1_input, 0444, show_fan, NULL, 0, 0);
2195 static SENSOR_DEVICE_ATTR_2(fan1_min, 0644, show_fan, set_fan, 0, 1);
2196 static SENSOR_DEVICE_ATTR(fan1_div, 0644, show_fan_div, set_fan_div, 0);
2198 static SENSOR_DEVICE_ATTR_2(fan2_input, 0444, show_fan, NULL, 1, 0);
2199 static SENSOR_DEVICE_ATTR_2(fan2_min, 0644, show_fan, set_fan, 1, 1);
2200 static SENSOR_DEVICE_ATTR(fan2_div, 0644, show_fan_div, set_fan_div, 1);
2202 static SENSOR_DEVICE_ATTR_2(fan3_input, 0444, show_fan, NULL, 2, 0);
2203 static SENSOR_DEVICE_ATTR_2(fan3_min, 0644, show_fan, set_fan, 2, 1);
2204 static SENSOR_DEVICE_ATTR(fan3_div, 0644, show_fan_div, set_fan_div, 2);
2206 static SENSOR_DEVICE_ATTR_2(fan4_input, 0444, show_fan, NULL, 3, 0);
2207 static SENSOR_DEVICE_ATTR_2(fan4_min, 0644, show_fan, set_fan, 3, 1);
2209 static SENSOR_DEVICE_ATTR_2(fan5_input, 0444, show_fan, NULL, 4, 0);
2210 static SENSOR_DEVICE_ATTR_2(fan5_min, 0644, show_fan, set_fan, 4, 1);
2212 static SENSOR_DEVICE_ATTR_2(fan6_input, 0444, show_fan, NULL, 5, 0);
2213 static SENSOR_DEVICE_ATTR_2(fan6_min, 0644, show_fan, set_fan, 5, 1);
2215 static SENSOR_DEVICE_ATTR(pwm1_enable, 0644,
2216 show_pwm_enable, set_pwm_enable, 0);
2217 static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);
2218 static SENSOR_DEVICE_ATTR(pwm1_freq, 0644, show_pwm_freq, set_pwm_freq, 0);
2219 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, 0444,
2220 show_pwm_temp_map, set_pwm_temp_map, 0);
2221 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, 0644,
2222 show_auto_pwm, set_auto_pwm, 0, 0);
2223 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, 0644,
2224 show_auto_pwm, set_auto_pwm, 0, 1);
2225 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, 0644,
2226 show_auto_pwm, set_auto_pwm, 0, 2);
2227 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, 0444,
2228 show_auto_pwm, NULL, 0, 3);
2229 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, 0644,
2230 show_auto_temp, set_auto_temp, 0, 1);
2231 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, 0644,
2232 show_auto_temp, set_auto_temp, 0, 0);
2233 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, 0644,
2234 show_auto_temp, set_auto_temp, 0, 2);
2235 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, 0644,
2236 show_auto_temp, set_auto_temp, 0, 3);
2237 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, 0644,
2238 show_auto_temp, set_auto_temp, 0, 4);
2239 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, 0644,
2240 show_auto_pwm, set_auto_pwm, 0, 0);
2241 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, 0644,
2242 show_auto_pwm_slope, set_auto_pwm_slope, 0);
2244 static SENSOR_DEVICE_ATTR(pwm2_enable, 0644,
2245 show_pwm_enable, set_pwm_enable, 1);
2246 static SENSOR_DEVICE_ATTR(pwm2, 0644, show_pwm, set_pwm, 1);
2247 static SENSOR_DEVICE_ATTR(pwm2_freq, 0444, show_pwm_freq, set_pwm_freq, 1);
2248 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, 0444,
2249 show_pwm_temp_map, set_pwm_temp_map, 1);
2250 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, 0644,
2251 show_auto_pwm, set_auto_pwm, 1, 0);
2252 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, 0644,
2253 show_auto_pwm, set_auto_pwm, 1, 1);
2254 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, 0644,
2255 show_auto_pwm, set_auto_pwm, 1, 2);
2256 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, 0444,
2257 show_auto_pwm, NULL, 1, 3);
2258 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, 0644,
2259 show_auto_temp, set_auto_temp, 1, 1);
2260 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, 0644,
2261 show_auto_temp, set_auto_temp, 1, 0);
2262 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, 0644,
2263 show_auto_temp, set_auto_temp, 1, 2);
2264 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, 0644,
2265 show_auto_temp, set_auto_temp, 1, 3);
2266 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, 0644,
2267 show_auto_temp, set_auto_temp, 1, 4);
2268 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, 0644,
2269 show_auto_pwm, set_auto_pwm, 1, 0);
2270 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, 0644,
2271 show_auto_pwm_slope, set_auto_pwm_slope, 1);
2273 static SENSOR_DEVICE_ATTR(pwm3_enable, 0644,
2274 show_pwm_enable, set_pwm_enable, 2);
2275 static SENSOR_DEVICE_ATTR(pwm3, 0644, show_pwm, set_pwm, 2);
2276 static SENSOR_DEVICE_ATTR(pwm3_freq, 0444, show_pwm_freq, NULL, 2);
2277 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, 0444,
2278 show_pwm_temp_map, set_pwm_temp_map, 2);
2279 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, 0644,
2280 show_auto_pwm, set_auto_pwm, 2, 0);
2281 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, 0644,
2282 show_auto_pwm, set_auto_pwm, 2, 1);
2283 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, 0644,
2284 show_auto_pwm, set_auto_pwm, 2, 2);
2285 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, 0444,
2286 show_auto_pwm, NULL, 2, 3);
2287 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, 0644,
2288 show_auto_temp, set_auto_temp, 2, 1);
2289 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, 0644,
2290 show_auto_temp, set_auto_temp, 2, 0);
2291 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, 0644,
2292 show_auto_temp, set_auto_temp, 2, 2);
2293 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, 0644,
2294 show_auto_temp, set_auto_temp, 2, 3);
2295 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, 0644,
2296 show_auto_temp, set_auto_temp, 2, 4);
2297 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, 0644,
2298 show_auto_pwm, set_auto_pwm, 2, 0);
2299 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, 0644,
2300 show_auto_pwm_slope, set_auto_pwm_slope, 2);
2302 static SENSOR_DEVICE_ATTR(pwm4_enable, 0644,
2303 show_pwm_enable, set_pwm_enable, 3);
2304 static SENSOR_DEVICE_ATTR(pwm4, 0644, show_pwm, set_pwm, 3);
2305 static SENSOR_DEVICE_ATTR(pwm4_freq, 0444, show_pwm_freq, NULL, 3);
2306 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, 0444,
2307 show_pwm_temp_map, set_pwm_temp_map, 3);
2308 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, 0644,
2309 show_auto_temp, set_auto_temp, 2, 1);
2310 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, 0644,
2311 show_auto_temp, set_auto_temp, 2, 0);
2312 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, 0644,
2313 show_auto_temp, set_auto_temp, 2, 2);
2314 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, 0644,
2315 show_auto_temp, set_auto_temp, 2, 3);
2316 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, 0644,
2317 show_auto_pwm, set_auto_pwm, 3, 0);
2318 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, 0644,
2319 show_auto_pwm_slope, set_auto_pwm_slope, 3);
2321 static SENSOR_DEVICE_ATTR(pwm5_enable, 0644,
2322 show_pwm_enable, set_pwm_enable, 4);
2323 static SENSOR_DEVICE_ATTR(pwm5, 0644, show_pwm, set_pwm, 4);
2324 static SENSOR_DEVICE_ATTR(pwm5_freq, 0444, show_pwm_freq, NULL, 4);
2325 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, 0444,
2326 show_pwm_temp_map, set_pwm_temp_map, 4);
2327 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, 0644,
2328 show_auto_temp, set_auto_temp, 2, 1);
2329 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, 0644,
2330 show_auto_temp, set_auto_temp, 2, 0);
2331 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, 0644,
2332 show_auto_temp, set_auto_temp, 2, 2);
2333 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, 0644,
2334 show_auto_temp, set_auto_temp, 2, 3);
2335 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, 0644,
2336 show_auto_pwm, set_auto_pwm, 4, 0);
2337 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, 0644,
2338 show_auto_pwm_slope, set_auto_pwm_slope, 4);
2340 static SENSOR_DEVICE_ATTR(pwm6_enable, 0644,
2341 show_pwm_enable, set_pwm_enable, 5);
2342 static SENSOR_DEVICE_ATTR(pwm6, 0644, show_pwm, set_pwm, 5);
2343 static SENSOR_DEVICE_ATTR(pwm6_freq, 0444, show_pwm_freq, NULL, 5);
2344 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, 0444,
2345 show_pwm_temp_map, set_pwm_temp_map, 5);
2346 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, 0644,
2347 show_auto_temp, set_auto_temp, 2, 1);
2348 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, 0644,
2349 show_auto_temp, set_auto_temp, 2, 0);
2350 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, 0644,
2351 show_auto_temp, set_auto_temp, 2, 2);
2352 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, 0644,
2353 show_auto_temp, set_auto_temp, 2, 3);
2354 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, 0644,
2355 show_auto_pwm, set_auto_pwm, 5, 0);
2356 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, 0644,
2357 show_auto_pwm_slope, set_auto_pwm_slope, 5);
2360 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2363 struct it87_data *data = it87_update_device(dev);
2366 return PTR_ERR(data);
2368 return sprintf(buf, "%u\n", data->alarms);
2370 static DEVICE_ATTR(alarms, 0444, show_alarms, NULL);
2372 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2375 struct it87_data *data = it87_update_device(dev);
2376 int bitnr = to_sensor_dev_attr(attr)->index;
2379 return PTR_ERR(data);
2381 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2384 static ssize_t clear_intrusion(struct device *dev,
2385 struct device_attribute *attr, const char *buf,
2388 struct it87_data *data = dev_get_drvdata(dev);
2392 if (kstrtol(buf, 10, &val) < 0 || val != 0)
2395 err = it87_lock(data);
2399 config = data->read(data, IT87_REG_CONFIG);
2401 data->write(data, IT87_REG_CONFIG, config);
2402 /* Invalidate cache to force re-read */
2408 static SENSOR_DEVICE_ATTR(in0_alarm, 0444, show_alarm, NULL, 8);
2409 static SENSOR_DEVICE_ATTR(in1_alarm, 0444, show_alarm, NULL, 9);
2410 static SENSOR_DEVICE_ATTR(in2_alarm, 0444, show_alarm, NULL, 10);
2411 static SENSOR_DEVICE_ATTR(in3_alarm, 0444, show_alarm, NULL, 11);
2412 static SENSOR_DEVICE_ATTR(in4_alarm, 0444, show_alarm, NULL, 12);
2413 static SENSOR_DEVICE_ATTR(in5_alarm, 0444, show_alarm, NULL, 13);
2414 static SENSOR_DEVICE_ATTR(in6_alarm, 0444, show_alarm, NULL, 14);
2415 static SENSOR_DEVICE_ATTR(in7_alarm, 0444, show_alarm, NULL, 15);
2416 static SENSOR_DEVICE_ATTR(fan1_alarm, 0444, show_alarm, NULL, 0);
2417 static SENSOR_DEVICE_ATTR(fan2_alarm, 0444, show_alarm, NULL, 1);
2418 static SENSOR_DEVICE_ATTR(fan3_alarm, 0444, show_alarm, NULL, 2);
2419 static SENSOR_DEVICE_ATTR(fan4_alarm, 0444, show_alarm, NULL, 3);
2420 static SENSOR_DEVICE_ATTR(fan5_alarm, 0444, show_alarm, NULL, 6);
2421 static SENSOR_DEVICE_ATTR(fan6_alarm, 0444, show_alarm, NULL, 7);
2422 static SENSOR_DEVICE_ATTR(temp1_alarm, 0444, show_alarm, NULL, 16);
2423 static SENSOR_DEVICE_ATTR(temp2_alarm, 0444, show_alarm, NULL, 17);
2424 static SENSOR_DEVICE_ATTR(temp3_alarm, 0444, show_alarm, NULL, 18);
2425 static SENSOR_DEVICE_ATTR(temp4_alarm, 0444, show_alarm, NULL, 19);
2426 static SENSOR_DEVICE_ATTR(temp5_alarm, 0444, show_alarm, NULL, 20);
2427 static SENSOR_DEVICE_ATTR(temp6_alarm, 0444, show_alarm, NULL, 21);
2428 static SENSOR_DEVICE_ATTR(intrusion0_alarm, 0644,
2429 show_alarm, clear_intrusion, 4);
2431 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2434 struct it87_data *data = it87_update_device(dev);
2435 int bitnr = to_sensor_dev_attr(attr)->index;
2438 return PTR_ERR(data);
2440 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2443 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2444 const char *buf, size_t count)
2446 int bitnr = to_sensor_dev_attr(attr)->index;
2447 struct it87_data *data = dev_get_drvdata(dev);
2451 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2454 err = it87_lock(data);
2458 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2460 data->beeps |= BIT(bitnr);
2462 data->beeps &= ~BIT(bitnr);
2463 data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2468 static SENSOR_DEVICE_ATTR(in0_beep, 0644,
2469 show_beep, set_beep, 1);
2470 static SENSOR_DEVICE_ATTR(in1_beep, 0444, show_beep, NULL, 1);
2471 static SENSOR_DEVICE_ATTR(in2_beep, 0444, show_beep, NULL, 1);
2472 static SENSOR_DEVICE_ATTR(in3_beep, 0444, show_beep, NULL, 1);
2473 static SENSOR_DEVICE_ATTR(in4_beep, 0444, show_beep, NULL, 1);
2474 static SENSOR_DEVICE_ATTR(in5_beep, 0444, show_beep, NULL, 1);
2475 static SENSOR_DEVICE_ATTR(in6_beep, 0444, show_beep, NULL, 1);
2476 static SENSOR_DEVICE_ATTR(in7_beep, 0444, show_beep, NULL, 1);
2477 /* fanX_beep writability is set later */
2478 static SENSOR_DEVICE_ATTR(fan1_beep, 0444, show_beep, set_beep, 0);
2479 static SENSOR_DEVICE_ATTR(fan2_beep, 0444, show_beep, set_beep, 0);
2480 static SENSOR_DEVICE_ATTR(fan3_beep, 0444, show_beep, set_beep, 0);
2481 static SENSOR_DEVICE_ATTR(fan4_beep, 0444, show_beep, set_beep, 0);
2482 static SENSOR_DEVICE_ATTR(fan5_beep, 0444, show_beep, set_beep, 0);
2483 static SENSOR_DEVICE_ATTR(fan6_beep, 0444, show_beep, set_beep, 0);
2484 static SENSOR_DEVICE_ATTR(temp1_beep, 0644,
2485 show_beep, set_beep, 2);
2486 static SENSOR_DEVICE_ATTR(temp2_beep, 0444, show_beep, NULL, 2);
2487 static SENSOR_DEVICE_ATTR(temp3_beep, 0444, show_beep, NULL, 2);
2488 static SENSOR_DEVICE_ATTR(temp4_beep, 0444, show_beep, NULL, 2);
2489 static SENSOR_DEVICE_ATTR(temp5_beep, 0444, show_beep, NULL, 2);
2490 static SENSOR_DEVICE_ATTR(temp6_beep, 0444, show_beep, NULL, 2);
2492 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2495 struct it87_data *data = dev_get_drvdata(dev);
2497 return sprintf(buf, "%u\n", data->vrm);
2500 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2501 const char *buf, size_t count)
2503 struct it87_data *data = dev_get_drvdata(dev);
2506 if (kstrtoul(buf, 10, &val) < 0)
2513 static DEVICE_ATTR(vrm, 0644, show_vrm_reg, store_vrm_reg);
2515 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2518 struct it87_data *data = it87_update_device(dev);
2521 return PTR_ERR(data);
2523 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2525 static DEVICE_ATTR(cpu0_vid, 0444, show_vid_reg, NULL);
2527 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2530 static const char * const labels[] = {
2536 static const char * const labels_it8721[] = {
2542 struct it87_data *data = dev_get_drvdata(dev);
2543 int nr = to_sensor_dev_attr(attr)->index;
2546 if (has_vin3_5v(data) && nr == 0)
2548 else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2550 label = labels_it8721[nr];
2554 return sprintf(buf, "%s\n", label);
2556 static SENSOR_DEVICE_ATTR(in3_label, 0444, show_label, NULL, 0);
2557 static SENSOR_DEVICE_ATTR(in7_label, 0444, show_label, NULL, 1);
2558 static SENSOR_DEVICE_ATTR(in8_label, 0444, show_label, NULL, 2);
2560 static SENSOR_DEVICE_ATTR(in9_label, 0444, show_label, NULL, 3);
2562 static umode_t it87_in_is_visible(struct kobject *kobj,
2563 struct attribute *attr, int index)
2565 struct device *dev = container_of(kobj, struct device, kobj);
2566 struct it87_data *data = dev_get_drvdata(dev);
2567 int i = index / 5; /* voltage index */
2568 int a = index % 5; /* attribute index */
2570 if (index >= 40) { /* in8 and higher only have input attributes */
2575 if (!(data->has_in & BIT(i)))
2578 if (a == 4 && !data->has_beep)
2584 static struct attribute *it87_attributes_in[] = {
2585 &sensor_dev_attr_in0_input.dev_attr.attr,
2586 &sensor_dev_attr_in0_min.dev_attr.attr,
2587 &sensor_dev_attr_in0_max.dev_attr.attr,
2588 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2589 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2591 &sensor_dev_attr_in1_input.dev_attr.attr,
2592 &sensor_dev_attr_in1_min.dev_attr.attr,
2593 &sensor_dev_attr_in1_max.dev_attr.attr,
2594 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2595 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2597 &sensor_dev_attr_in2_input.dev_attr.attr,
2598 &sensor_dev_attr_in2_min.dev_attr.attr,
2599 &sensor_dev_attr_in2_max.dev_attr.attr,
2600 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2601 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2603 &sensor_dev_attr_in3_input.dev_attr.attr,
2604 &sensor_dev_attr_in3_min.dev_attr.attr,
2605 &sensor_dev_attr_in3_max.dev_attr.attr,
2606 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2607 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2609 &sensor_dev_attr_in4_input.dev_attr.attr,
2610 &sensor_dev_attr_in4_min.dev_attr.attr,
2611 &sensor_dev_attr_in4_max.dev_attr.attr,
2612 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2613 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2615 &sensor_dev_attr_in5_input.dev_attr.attr,
2616 &sensor_dev_attr_in5_min.dev_attr.attr,
2617 &sensor_dev_attr_in5_max.dev_attr.attr,
2618 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2619 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2621 &sensor_dev_attr_in6_input.dev_attr.attr,
2622 &sensor_dev_attr_in6_min.dev_attr.attr,
2623 &sensor_dev_attr_in6_max.dev_attr.attr,
2624 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2625 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2627 &sensor_dev_attr_in7_input.dev_attr.attr,
2628 &sensor_dev_attr_in7_min.dev_attr.attr,
2629 &sensor_dev_attr_in7_max.dev_attr.attr,
2630 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2631 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2633 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2634 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
2635 &sensor_dev_attr_in10_input.dev_attr.attr, /* 42 */
2636 &sensor_dev_attr_in11_input.dev_attr.attr, /* 43 */
2637 &sensor_dev_attr_in12_input.dev_attr.attr, /* 44 */
2641 static const struct attribute_group it87_group_in = {
2642 .attrs = it87_attributes_in,
2643 .is_visible = it87_in_is_visible,
2646 static umode_t it87_temp_is_visible(struct kobject *kobj,
2647 struct attribute *attr, int index)
2649 struct device *dev = container_of(kobj, struct device, kobj);
2650 struct it87_data *data = dev_get_drvdata(dev);
2651 int i = index / 7; /* temperature index */
2652 int a = index % 7; /* attribute index */
2654 if (!(data->has_temp & BIT(i)))
2657 if (a && i >= data->num_temp_limit)
2661 int type = get_temp_type(data, i);
2665 if (has_bank_sel(data))
2670 if (a == 5 && i >= data->num_temp_offset)
2673 if (a == 6 && !data->has_beep)
2679 static struct attribute *it87_attributes_temp[] = {
2680 &sensor_dev_attr_temp1_input.dev_attr.attr,
2681 &sensor_dev_attr_temp1_max.dev_attr.attr,
2682 &sensor_dev_attr_temp1_min.dev_attr.attr,
2683 &sensor_dev_attr_temp1_type.dev_attr.attr, /* 3 */
2684 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2685 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2686 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2688 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2689 &sensor_dev_attr_temp2_max.dev_attr.attr,
2690 &sensor_dev_attr_temp2_min.dev_attr.attr,
2691 &sensor_dev_attr_temp2_type.dev_attr.attr,
2692 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2693 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2694 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2696 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2697 &sensor_dev_attr_temp3_max.dev_attr.attr,
2698 &sensor_dev_attr_temp3_min.dev_attr.attr,
2699 &sensor_dev_attr_temp3_type.dev_attr.attr,
2700 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2701 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2702 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2704 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2705 &sensor_dev_attr_temp4_max.dev_attr.attr,
2706 &sensor_dev_attr_temp4_min.dev_attr.attr,
2707 &sensor_dev_attr_temp4_type.dev_attr.attr,
2708 &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2709 &sensor_dev_attr_temp4_offset.dev_attr.attr,
2710 &sensor_dev_attr_temp4_beep.dev_attr.attr,
2712 &sensor_dev_attr_temp5_input.dev_attr.attr,
2713 &sensor_dev_attr_temp5_max.dev_attr.attr,
2714 &sensor_dev_attr_temp5_min.dev_attr.attr,
2715 &sensor_dev_attr_temp5_type.dev_attr.attr,
2716 &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2717 &sensor_dev_attr_temp5_offset.dev_attr.attr,
2718 &sensor_dev_attr_temp5_beep.dev_attr.attr,
2720 &sensor_dev_attr_temp6_input.dev_attr.attr,
2721 &sensor_dev_attr_temp6_max.dev_attr.attr,
2722 &sensor_dev_attr_temp6_min.dev_attr.attr,
2723 &sensor_dev_attr_temp6_type.dev_attr.attr,
2724 &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2725 &sensor_dev_attr_temp6_offset.dev_attr.attr,
2726 &sensor_dev_attr_temp6_beep.dev_attr.attr,
2730 static const struct attribute_group it87_group_temp = {
2731 .attrs = it87_attributes_temp,
2732 .is_visible = it87_temp_is_visible,
2735 static umode_t it87_is_visible(struct kobject *kobj,
2736 struct attribute *attr, int index)
2738 struct device *dev = container_of(kobj, struct device, kobj);
2739 struct it87_data *data = dev_get_drvdata(dev);
2741 if ((index == 2 || index == 3) && !data->has_vid)
2744 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2750 static struct attribute *it87_attributes[] = {
2751 &dev_attr_alarms.attr,
2752 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2753 &dev_attr_vrm.attr, /* 2 */
2754 &dev_attr_cpu0_vid.attr, /* 3 */
2755 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2756 &sensor_dev_attr_in7_label.dev_attr.attr,
2757 &sensor_dev_attr_in8_label.dev_attr.attr,
2758 &sensor_dev_attr_in9_label.dev_attr.attr,
2762 static const struct attribute_group it87_group = {
2763 .attrs = it87_attributes,
2764 .is_visible = it87_is_visible,
2767 static umode_t it87_fan_is_visible(struct kobject *kobj,
2768 struct attribute *attr, int index)
2770 struct device *dev = container_of(kobj, struct device, kobj);
2771 struct it87_data *data = dev_get_drvdata(dev);
2772 int i = index / 5; /* fan index */
2773 int a = index % 5; /* attribute index */
2775 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2776 i = (index - 15) / 4 + 3;
2777 a = (index - 15) % 4;
2780 if (!(data->has_fan & BIT(i)))
2783 if (a == 3) { /* beep */
2784 if (!data->has_beep)
2786 /* first fan beep attribute is writable */
2787 if (i == __ffs(data->has_fan))
2788 return attr->mode | 0200;
2791 if (a == 4 && has_16bit_fans(data)) /* divisor */
2797 static struct attribute *it87_attributes_fan[] = {
2798 &sensor_dev_attr_fan1_input.dev_attr.attr,
2799 &sensor_dev_attr_fan1_min.dev_attr.attr,
2800 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2801 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2802 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2804 &sensor_dev_attr_fan2_input.dev_attr.attr,
2805 &sensor_dev_attr_fan2_min.dev_attr.attr,
2806 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2807 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2808 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2810 &sensor_dev_attr_fan3_input.dev_attr.attr,
2811 &sensor_dev_attr_fan3_min.dev_attr.attr,
2812 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2813 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2814 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2816 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2817 &sensor_dev_attr_fan4_min.dev_attr.attr,
2818 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2819 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2821 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2822 &sensor_dev_attr_fan5_min.dev_attr.attr,
2823 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2824 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2826 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2827 &sensor_dev_attr_fan6_min.dev_attr.attr,
2828 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2829 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2833 static const struct attribute_group it87_group_fan = {
2834 .attrs = it87_attributes_fan,
2835 .is_visible = it87_fan_is_visible,
2838 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2839 struct attribute *attr, int index)
2841 struct device *dev = container_of(kobj, struct device, kobj);
2842 struct it87_data *data = dev_get_drvdata(dev);
2843 int i = index / 4; /* pwm index */
2844 int a = index % 4; /* attribute index */
2846 if (!(data->has_pwm & BIT(i)))
2849 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2850 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2851 return attr->mode | 0200;
2853 /* pwm2_freq is writable if there are two pwm frequency selects */
2854 if (has_pwm_freq2(data) && i == 1 && a == 2)
2855 return attr->mode | 0200;
2860 static struct attribute *it87_attributes_pwm[] = {
2861 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2862 &sensor_dev_attr_pwm1.dev_attr.attr,
2863 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2864 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2866 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2867 &sensor_dev_attr_pwm2.dev_attr.attr,
2868 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2869 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2871 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2872 &sensor_dev_attr_pwm3.dev_attr.attr,
2873 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2874 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2876 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2877 &sensor_dev_attr_pwm4.dev_attr.attr,
2878 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2879 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2881 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2882 &sensor_dev_attr_pwm5.dev_attr.attr,
2883 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2884 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2886 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2887 &sensor_dev_attr_pwm6.dev_attr.attr,
2888 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2889 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2894 static const struct attribute_group it87_group_pwm = {
2895 .attrs = it87_attributes_pwm,
2896 .is_visible = it87_pwm_is_visible,
2899 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2900 struct attribute *attr, int index)
2902 struct device *dev = container_of(kobj, struct device, kobj);
2903 struct it87_data *data = dev_get_drvdata(dev);
2904 int i = index / 11; /* pwm index */
2905 int a = index % 11; /* attribute index */
2907 if (index >= 33) { /* pwm 4..6 */
2908 i = (index - 33) / 6 + 3;
2909 a = (index - 33) % 6 + 4;
2912 if (!(data->has_pwm & BIT(i)))
2915 if (has_newer_autopwm(data)) {
2916 if (a < 4) /* no auto point pwm */
2918 if (a == 8) /* no auto_point4 */
2921 if (has_old_autopwm(data)) {
2922 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2929 static struct attribute *it87_attributes_auto_pwm[] = {
2930 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2931 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2932 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2933 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2934 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2935 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2936 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2937 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2938 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2939 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2940 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2942 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2943 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2944 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2945 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2946 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2947 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2948 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2949 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2950 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2951 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2952 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2954 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2955 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2956 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2957 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2958 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2959 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2960 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2961 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2962 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2963 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2964 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2966 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2967 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2968 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2969 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2970 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2971 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2973 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2974 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2975 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2976 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2977 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2978 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2980 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2981 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2982 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2983 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2984 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2985 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2990 static const struct attribute_group it87_group_auto_pwm = {
2991 .attrs = it87_attributes_auto_pwm,
2992 .is_visible = it87_auto_pwm_is_visible,
2995 /* SuperIO detection - will change isa_address if a chip is found */
2996 static int __init it87_find(int sioaddr, unsigned short *address,
2997 phys_addr_t *mmio_address,
2998 struct it87_sio_data *sio_data)
3000 const struct it87_devices *config;
3001 phys_addr_t base = 0;
3007 err = superio_enter(sioaddr);
3011 sio_data->sioaddr = sioaddr;
3014 chip_type = superio_inw(sioaddr, DEVID);
3015 if (chip_type == 0xffff)
3019 chip_type = force_id;
3021 switch (chip_type) {
3023 sio_data->type = it87;
3026 sio_data->type = it8712;
3030 sio_data->type = it8716;
3033 sio_data->type = it8718;
3036 sio_data->type = it8720;
3039 sio_data->type = it8721;
3042 sio_data->type = it8728;
3045 sio_data->type = it8732;
3048 sio_data->type = it8736;
3051 sio_data->type = it8738;
3054 sio_data->type = it8792;
3056 * Disabling configuration mode on IT8792E can result in system
3057 * hang-ups and access failures to the Super-IO chip at the
3058 * second SIO address. Never exit configuration mode on this
3059 * chip to avoid the problem.
3064 sio_data->type = it8771;
3067 sio_data->type = it8772;
3070 sio_data->type = it8781;
3073 sio_data->type = it8782;
3076 sio_data->type = it8783;
3079 sio_data->type = it8786;
3082 sio_data->type = it8790;
3083 doexit = false; /* See IT8792E comment above */
3087 sio_data->type = it8603;
3090 sio_data->type = it8606;
3093 sio_data->type = it8607;
3096 sio_data->type = it8613;
3099 sio_data->type = it8620;
3102 sio_data->type = it8622;
3105 sio_data->type = it8625;
3108 sio_data->type = it8628;
3111 sio_data->type = it8655;
3114 sio_data->type = it8665;
3117 sio_data->type = it8686;
3119 case 0xffff: /* No device at all */
3122 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3126 superio_select(sioaddr, PME);
3127 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3128 pr_info("Device not activated, skipping\n");
3132 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3133 if (*address == 0) {
3134 pr_info("Base address not set, skipping\n");
3138 sio_data->doexit = doexit;
3141 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3143 config = &it87_devices[sio_data->type];
3145 if (has_mmio(config) && mmio) {
3148 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3150 base = 0xf0000000 + ((reg & 0x0f) << 24);
3151 base += (reg & 0xc0) << 14;
3154 *mmio_address = base;
3158 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3160 pr_info("Found %s chip at 0x%x%s, revision %d\n",
3161 it87_devices[sio_data->type].model,
3162 *address, mmio_str, sio_data->revision);
3164 /* in7 (VSB or VCCH5V) is always internal on some chips */
3165 if (has_in7_internal(config))
3166 sio_data->internal |= BIT(1);
3168 /* in8 (Vbat) is always internal */
3169 sio_data->internal |= BIT(2);
3171 /* in9 (AVCC3), always internal if supported */
3172 if (has_avcc3(config))
3173 sio_data->internal |= BIT(3); /* in9 is AVCC */
3175 sio_data->skip_in |= BIT(9);
3177 if (!has_four_pwm(config))
3178 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3179 else if (!has_five_pwm(config))
3180 sio_data->skip_pwm |= BIT(4) | BIT(5);
3181 else if (!has_six_pwm(config))
3182 sio_data->skip_pwm |= BIT(5);
3184 if (!has_vid(config))
3185 sio_data->skip_vid = 1;
3187 /* Read GPIO config and VID value from LDN 7 (GPIO) */
3188 if (sio_data->type == it87) {
3189 /* The IT8705F has a different LD number for GPIO */
3190 superio_select(sioaddr, 5);
3191 sio_data->beep_pin = superio_inb(sioaddr,
3192 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3193 } else if (sio_data->type == it8783) {
3194 int reg25, reg27, reg2a, reg2c, regef;
3196 superio_select(sioaddr, GPIO);
3198 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3199 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3200 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3201 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3202 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3204 /* Check if fan3 is there or not */
3205 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3206 sio_data->skip_fan |= BIT(2);
3207 if ((reg25 & BIT(4)) ||
3208 (!(reg2a & BIT(1)) && (regef & BIT(0))))
3209 sio_data->skip_pwm |= BIT(2);
3211 /* Check if fan2 is there or not */
3213 sio_data->skip_fan |= BIT(1);
3215 sio_data->skip_pwm |= BIT(1);
3218 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3219 sio_data->skip_in |= BIT(5); /* No VIN5 */
3223 sio_data->skip_in |= BIT(6); /* No VIN6 */
3227 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3229 if (reg27 & BIT(2)) {
3231 * The data sheet is a bit unclear regarding the
3232 * internal voltage divider for VCCH5V. It says
3233 * "This bit enables and switches VIN7 (pin 91) to the
3234 * internal voltage divider for VCCH5V".
3235 * This is different to other chips, where the internal
3236 * voltage divider would connect VIN7 to an internal
3237 * voltage source. Maybe that is the case here as well.
3239 * Since we don't know for sure, re-route it if that is
3240 * not the case, and ask the user to report if the
3241 * resulting voltage is sane.
3243 if (!(reg2c & BIT(1))) {
3245 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3247 pr_notice("Routing internal VCCH5V to in7.\n");
3249 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3250 pr_notice("Please report if it displays a reasonable voltage.\n");
3254 sio_data->internal |= BIT(0);
3256 sio_data->internal |= BIT(1);
3258 sio_data->beep_pin = superio_inb(sioaddr,
3259 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3260 } else if (sio_data->type == it8603 || sio_data->type == it8606 ||
3261 sio_data->type == it8607) {
3264 superio_select(sioaddr, GPIO);
3266 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3268 /* Check if fan3 is there or not */
3270 sio_data->skip_pwm |= BIT(2);
3272 sio_data->skip_fan |= BIT(2);
3274 /* Check if fan2 is there or not */
3275 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3277 sio_data->skip_pwm |= BIT(1);
3279 sio_data->skip_fan |= BIT(1);
3281 switch (sio_data->type) {
3283 sio_data->skip_in |= BIT(5); /* No VIN5 */
3284 sio_data->skip_in |= BIT(6); /* No VIN6 */
3287 sio_data->skip_pwm |= BIT(0);/* No fan1 */
3288 sio_data->skip_fan |= BIT(0);
3293 sio_data->beep_pin = superio_inb(sioaddr,
3294 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3295 } else if (sio_data->type == it8613) {
3296 int reg27, reg29, reg2a;
3298 superio_select(sioaddr, GPIO);
3300 /* Check for pwm3, fan3, pwm5, fan5 */
3301 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3303 sio_data->skip_fan |= BIT(4);
3305 sio_data->skip_pwm |= BIT(4);
3307 sio_data->skip_pwm |= BIT(2);
3309 sio_data->skip_fan |= BIT(2);
3311 /* Check for pwm2, fan2 */
3312 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3314 sio_data->skip_pwm |= BIT(1);
3316 sio_data->skip_fan |= BIT(1);
3318 /* Check for pwm4, fan4 */
3319 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3320 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3321 sio_data->skip_fan |= BIT(3);
3322 sio_data->skip_pwm |= BIT(3);
3325 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3326 sio_data->skip_fan |= BIT(0); /* No fan1 */
3327 sio_data->skip_in |= BIT(3); /* No VIN3 */
3328 sio_data->skip_in |= BIT(6); /* No VIN6 */
3330 sio_data->beep_pin = superio_inb(sioaddr,
3331 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3332 } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3333 sio_data->type == it8686) {
3336 superio_select(sioaddr, GPIO);
3338 /* Check for pwm5 */
3339 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3341 sio_data->skip_pwm |= BIT(4);
3343 /* Check for fan4, fan5 */
3344 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3345 if (!(reg & BIT(5)))
3346 sio_data->skip_fan |= BIT(3);
3347 if (!(reg & BIT(4)))
3348 sio_data->skip_fan |= BIT(4);
3350 /* Check for pwm3, fan3 */
3351 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3353 sio_data->skip_pwm |= BIT(2);
3355 sio_data->skip_fan |= BIT(2);
3357 /* Check for pwm4 */
3358 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3360 sio_data->skip_pwm |= BIT(3);
3362 /* Check for pwm2, fan2 */
3363 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3365 sio_data->skip_pwm |= BIT(1);
3367 sio_data->skip_fan |= BIT(1);
3368 /* Check for pwm6, fan6 */
3369 if (!(reg & BIT(7))) {
3370 sio_data->skip_pwm |= BIT(5);
3371 sio_data->skip_fan |= BIT(5);
3374 /* Check if AVCC is on VIN3 */
3375 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3377 /* For it8686, the bit just enables AVCC3 */
3378 if (sio_data->type != it8686)
3379 sio_data->internal |= BIT(0);
3381 sio_data->internal &= ~BIT(3);
3382 sio_data->skip_in |= BIT(9);
3385 sio_data->beep_pin = superio_inb(sioaddr,
3386 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3387 } else if (sio_data->type == it8622) {
3390 superio_select(sioaddr, GPIO);
3392 /* Check for pwm4, fan4 */
3393 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3395 sio_data->skip_fan |= BIT(3);
3397 sio_data->skip_pwm |= BIT(3);
3399 /* Check for pwm3, fan3, pwm5, fan5 */
3400 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3402 sio_data->skip_pwm |= BIT(2);
3404 sio_data->skip_fan |= BIT(2);
3406 sio_data->skip_pwm |= BIT(4);
3408 sio_data->skip_fan |= BIT(4);
3410 /* Check for pwm2, fan2 */
3411 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3413 sio_data->skip_pwm |= BIT(1);
3415 sio_data->skip_fan |= BIT(1);
3417 /* Check for AVCC */
3418 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3419 if (!(reg & BIT(0)))
3420 sio_data->skip_in |= BIT(9);
3422 sio_data->beep_pin = superio_inb(sioaddr,
3423 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3424 } else if (sio_data->type == it8732 || sio_data->type == it8736 ||
3425 sio_data->type == it8738) {
3428 superio_select(sioaddr, GPIO);
3430 /* Check for pwm2, fan2 */
3431 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3433 sio_data->skip_pwm |= BIT(1);
3435 sio_data->skip_fan |= BIT(1);
3437 /* Check for pwm3, fan3, fan4 */
3438 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3440 sio_data->skip_pwm |= BIT(2);
3442 sio_data->skip_fan |= BIT(2);
3444 sio_data->skip_fan |= BIT(3);
3446 /* Check if AVCC is on VIN3 */
3447 if (sio_data->type != it8738) {
3448 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3450 sio_data->internal |= BIT(0);
3453 sio_data->beep_pin = superio_inb(sioaddr,
3454 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3455 } else if (sio_data->type == it8655) {
3458 superio_select(sioaddr, GPIO);
3460 /* Check for pwm2 */
3461 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3463 sio_data->skip_pwm |= BIT(1);
3465 /* Check for fan2 */
3466 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3468 sio_data->skip_fan |= BIT(1);
3470 /* Check for pwm3, fan3 */
3471 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3473 sio_data->skip_pwm |= BIT(2);
3475 sio_data->skip_fan |= BIT(2);
3477 sio_data->beep_pin = superio_inb(sioaddr,
3478 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3479 } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3480 int reg27, reg29, reg2d, regd3;
3482 superio_select(sioaddr, GPIO);
3484 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3485 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3486 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3487 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3489 /* Check for pwm2 */
3491 sio_data->skip_pwm |= BIT(1);
3493 /* Check for pwm3, fan3 */
3495 sio_data->skip_pwm |= BIT(2);
3497 sio_data->skip_fan |= BIT(2);
3499 /* Check for fan2, pwm4, fan4, pwm5, fan5 */
3500 if (sio_data->type == it8625) {
3501 int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3504 sio_data->skip_fan |= BIT(1);
3506 sio_data->skip_fan |= BIT(3);
3508 sio_data->skip_pwm |= BIT(3);
3510 sio_data->skip_pwm |= BIT(4);
3511 if (!(reg27 & BIT(1)))
3512 sio_data->skip_fan |= BIT(4);
3514 int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3517 sio_data->skip_fan |= BIT(1);
3519 sio_data->skip_pwm |= BIT(3);
3521 sio_data->skip_fan |= BIT(3);
3523 sio_data->skip_pwm |= BIT(4);
3525 * Table 6-1 in datasheet claims that FAN_TAC5 would
3526 * be enabled with 26h[4]=0. This contradicts with the
3527 * information in section 8.3.9 and with feedback from
3530 if (!(reg26 & BIT(4)))
3531 sio_data->skip_fan |= BIT(4);
3534 /* Check for pwm6, fan6 */
3536 sio_data->skip_pwm |= BIT(5);
3538 sio_data->skip_fan |= BIT(5);
3540 sio_data->beep_pin = superio_inb(sioaddr,
3541 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3546 superio_select(sioaddr, GPIO);
3548 /* Check for fan4, fan5 */
3549 if (has_five_fans(config)) {
3550 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3551 switch (sio_data->type) {
3554 sio_data->skip_fan |= BIT(3);
3556 sio_data->skip_fan |= BIT(4);
3561 if (!(reg & BIT(5)))
3562 sio_data->skip_fan |= BIT(3);
3563 if (!(reg & BIT(4)))
3564 sio_data->skip_fan |= BIT(4);
3571 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3572 if (!sio_data->skip_vid) {
3573 /* We need at least 4 VID pins */
3575 pr_info("VID is disabled (pins used for GPIO)\n");
3576 sio_data->skip_vid = 1;
3580 /* Check if fan3 is there or not */
3582 sio_data->skip_pwm |= BIT(2);
3584 sio_data->skip_fan |= BIT(2);
3586 /* Check if fan2 is there or not */
3587 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3589 sio_data->skip_pwm |= BIT(1);
3591 sio_data->skip_fan |= BIT(1);
3593 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3594 !(sio_data->skip_vid))
3595 sio_data->vid_value = superio_inb(sioaddr,
3598 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3600 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3603 * The IT8720F has no VIN7 pin, so VCCH should always be
3604 * routed internally to VIN7 with an internal divider.
3605 * Curiously, there still is a configuration bit to control
3606 * this, which means it can be set incorrectly. And even
3607 * more curiously, many boards out there are improperly
3608 * configured, even though the IT8720F datasheet claims
3609 * that the internal routing of VCCH to VIN7 is the default
3610 * setting. So we force the internal routing in this case.
3612 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3613 * If UART6 is enabled, re-route VIN7 to the internal divider
3614 * if that is not already the case.
3616 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3618 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3619 pr_notice("Routing internal VCCH to in7\n");
3622 sio_data->internal |= BIT(0);
3624 sio_data->internal |= BIT(1);
3627 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3628 * While VIN7 can be routed to the internal voltage divider,
3629 * VIN5 and VIN6 are not available if UART6 is enabled.
3631 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3632 * is the temperature source. Since we can not read the
3633 * temperature source here, skip_temp is preliminary.
3636 sio_data->skip_in |= BIT(5) | BIT(6);
3637 sio_data->skip_temp |= BIT(2);
3640 sio_data->beep_pin = superio_inb(sioaddr,
3641 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3643 if (sio_data->beep_pin)
3644 pr_info("Beeping is supported\n");
3646 if (config->smbus_bitmap && !base) {
3649 superio_select(sioaddr, PME);
3650 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3651 sio_data->ec_special_config = reg;
3652 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3656 superio_exit(sioaddr, doexit);
3660 static void it87_init_regs(struct platform_device *pdev)
3662 struct it87_data *data = platform_get_drvdata(pdev);
3664 /* Initialize chip specific register pointers */
3665 switch (data->type) {
3668 data->REG_FAN = IT87_REG_FAN;
3669 data->REG_FANX = IT87_REG_FANX;
3670 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3671 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3672 data->REG_PWM = IT87_REG_PWM;
3673 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3674 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3675 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3680 data->REG_FAN = IT87_REG_FAN_8665;
3681 data->REG_FANX = IT87_REG_FANX_8665;
3682 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3683 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3684 data->REG_PWM = IT87_REG_PWM_8665;
3685 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3686 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3687 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3690 data->REG_FAN = IT87_REG_FAN;
3691 data->REG_FANX = IT87_REG_FANX;
3692 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3693 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3694 data->REG_PWM = IT87_REG_PWM_8665;
3695 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3696 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3697 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3700 data->REG_FAN = IT87_REG_FAN;
3701 data->REG_FANX = IT87_REG_FANX;
3702 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3703 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3704 data->REG_PWM = IT87_REG_PWM_8665;
3705 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3706 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3707 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3710 data->REG_FAN = IT87_REG_FAN;
3711 data->REG_FANX = IT87_REG_FANX;
3712 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3713 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3714 data->REG_PWM = IT87_REG_PWM;
3715 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3716 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3717 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3722 data->read = it87_mmio_read;
3723 data->write = it87_mmio_write;
3724 } else if (has_bank_sel(data)) {
3725 data->read = it87_io_read;
3726 data->write = it87_io_write;
3728 data->read = _it87_io_read;
3729 data->write = _it87_io_write;
3733 /* Called when we have found a new IT87. */
3734 static void it87_init_device(struct platform_device *pdev)
3736 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3737 struct it87_data *data = platform_get_drvdata(pdev);
3741 if (has_new_tempmap(data)) {
3742 data->pwm_temp_map_shift = 3;
3743 data->pwm_temp_map_mask = 0x07;
3745 data->pwm_temp_map_shift = 0;
3746 data->pwm_temp_map_mask = 0x03;
3750 * For each PWM channel:
3751 * - If it is in automatic mode, setting to manual mode should set
3752 * the fan to full speed by default.
3753 * - If it is in manual mode, we need a mapping to temperature
3754 * channels to use when later setting to automatic mode later.
3755 * Map to the first sensor by default (we are clueless.)
3756 * In both cases, the value can (and should) be changed by the user
3757 * prior to switching to a different mode.
3758 * Note that this is no longer needed for the IT8721F and later, as
3759 * these have separate registers for the temperature mapping and the
3760 * manual duty cycle.
3762 for (i = 0; i < NUM_AUTO_PWM; i++) {
3763 data->pwm_temp_map[i] = 0;
3764 data->pwm_duty[i] = 0x7f; /* Full speed */
3765 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
3769 * Some chips seem to have default value 0xff for all limit
3770 * registers. For low voltage limits it makes no sense and triggers
3771 * alarms, so change to 0 instead. For high temperature limits, it
3772 * means -1 degree C, which surprisingly doesn't trigger an alarm,
3773 * but is still confusing, so change to 127 degrees C.
3775 for (i = 0; i < NUM_VIN_LIMIT; i++) {
3776 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3778 data->write(data, IT87_REG_VIN_MIN(i), 0);
3780 for (i = 0; i < data->num_temp_limit; i++) {
3781 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3783 data->write(data, data->REG_TEMP_HIGH[i], 127);
3787 * Temperature channels are not forcibly enabled, as they can be
3788 * set to two different sensor types and we can't guess which one
3789 * is correct for a given system. These channels can be enabled at
3790 * run-time through the temp{1-3}_type sysfs accessors if needed.
3793 /* Check if voltage monitors are reset manually or by some reason */
3794 tmp = data->read(data, IT87_REG_VIN_ENABLE);
3795 if ((tmp & 0xff) == 0) {
3796 /* Enable all voltage monitors */
3797 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3800 /* Check if tachometers are reset manually or by some reason */
3801 mask = 0x70 & ~(sio_data->skip_fan << 4);
3802 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3803 if ((data->fan_main_ctrl & mask) == 0) {
3804 /* Enable all fan tachometers */
3805 data->fan_main_ctrl |= mask;
3806 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3808 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3810 tmp = data->read(data, IT87_REG_FAN_16BIT);
3812 /* Set tachometers to 16-bit mode if needed */
3813 if (has_fan16_config(data)) {
3814 if (~tmp & 0x07 & data->has_fan) {
3816 "Setting fan1-3 to 16-bit mode\n");
3817 data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3821 /* Check for additional fans */
3822 if (has_four_fans(data) && (tmp & BIT(4)))
3823 data->has_fan |= BIT(3); /* fan4 enabled */
3824 if (has_five_fans(data) && (tmp & BIT(5)))
3825 data->has_fan |= BIT(4); /* fan5 enabled */
3826 if (has_six_fans(data)) {
3827 switch (data->type) {
3832 data->has_fan |= BIT(5); /* fan6 enabled */
3836 tmp = data->read(data, IT87_REG_FAN_DIV);
3838 data->has_fan |= BIT(5); /* fan6 enabled */
3845 /* Fan input pins may be used for alternative functions */
3846 data->has_fan &= ~sio_data->skip_fan;
3848 /* Check if pwm6 is enabled */
3849 if (has_six_pwm(data)) {
3850 switch (data->type) {
3853 tmp = data->read(data, IT87_REG_FAN_DIV);
3854 if (!(tmp & BIT(3)))
3855 sio_data->skip_pwm |= BIT(5);
3862 if (has_bank_sel(data)) {
3863 for (i = 0; i < 3; i++)
3865 data->read(data, IT87_REG_TEMP_SRC1[i]);
3866 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3869 /* Start monitoring */
3870 data->write(data, IT87_REG_CONFIG,
3871 (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3872 (update_vbat ? 0x41 : 0x01));
3875 /* Return 1 if and only if the PWM interface is safe to use */
3876 static int it87_check_pwm(struct device *dev)
3878 struct it87_data *data = dev_get_drvdata(dev);
3880 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3881 * and polarity set to active low is sign that this is the case so we
3882 * disable pwm control to protect the user.
3884 int tmp = data->read(data, IT87_REG_FAN_CTL);
3886 if ((tmp & 0x87) == 0) {
3887 if (fix_pwm_polarity) {
3889 * The user asks us to attempt a chip reconfiguration.
3890 * This means switching to active high polarity and
3891 * inverting all fan speed values.
3896 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3897 pwm[i] = data->read(data,
3901 * If any fan is in automatic pwm mode, the polarity
3902 * might be correct, as suspicious as it seems, so we
3903 * better don't change anything (but still disable the
3906 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3908 "Reconfiguring PWM to active high polarity\n");
3909 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3910 for (i = 0; i < 3; i++)
3911 data->write(data, data->REG_PWM[i],
3917 "PWM configuration is too broken to be fixed\n");
3921 "Detected broken BIOS defaults, disabling PWM interface\n");
3923 } else if (fix_pwm_polarity) {
3925 "PWM configuration looks sane, won't touch\n");
3931 static int it87_probe(struct platform_device *pdev)
3933 struct it87_data *data;
3934 struct resource *res;
3935 struct device *dev = &pdev->dev;
3936 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3937 int enable_pwm_interface;
3938 struct device *hwmon_dev;
3941 data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3945 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3947 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3949 dev_err(dev, "Failed to request region %pR\n", res);
3953 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3954 data->mmio = devm_ioremap_resource(dev, res);
3955 if (IS_ERR(data->mmio))
3956 return PTR_ERR(data->mmio);
3959 data->addr = res->start;
3960 data->type = sio_data->type;
3961 data->sioaddr = sio_data->sioaddr;
3962 data->smbus_bitmap = sio_data->smbus_bitmap;
3963 data->ec_special_config = sio_data->ec_special_config;
3964 data->doexit = sio_data->doexit;
3965 data->features = it87_devices[sio_data->type].features;
3966 data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3967 data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3968 data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3969 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3970 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3973 * IT8705F Datasheet 0.4.1, 3h == Version G.
3974 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3975 * These are the first revisions with 16-bit tachometer support.
3977 switch (data->type) {
3979 if (sio_data->revision >= 0x03) {
3980 data->features &= ~FEAT_OLD_AUTOPWM;
3981 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3985 if (sio_data->revision >= 0x08) {
3986 data->features &= ~FEAT_OLD_AUTOPWM;
3987 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3995 platform_set_drvdata(pdev, data);
3997 mutex_init(&data->update_lock);
3999 /* Initialize register pointers */
4000 it87_init_regs(pdev);
4003 * We need to disable SMBus before we can read any registers in
4004 * the envmon address space, even if it is for chip identification
4005 * purposes. If the chip has SMBus client support, it likely also has
4006 * multi-page envmon registers, so we have to set the page anyway
4007 * before accessing those registers. Kind of a chicken-and-egg
4009 * Fortunately, the chip was already identified through the SIO
4010 * address space, only recent chips are affected, and this is just
4011 * an additional safeguard.
4013 err = smbus_disable(data);
4017 /* Now, we do the remaining detection. */
4018 if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
4019 data->read(data, IT87_REG_CHIPID) != 0x90) {
4024 /* Check PWM configuration */
4025 enable_pwm_interface = it87_check_pwm(dev);
4027 /* Starting with IT8721F, we handle scaling of internal voltages */
4028 if (has_scaling(data)) {
4029 if (sio_data->internal & BIT(0))
4030 data->in_scaled |= BIT(3); /* in3 is AVCC */
4031 if (sio_data->internal & BIT(1))
4032 data->in_scaled |= BIT(7); /* in7 is VSB */
4033 if (sio_data->internal & BIT(2))
4034 data->in_scaled |= BIT(8); /* in8 is Vbat */
4035 if (sio_data->internal & BIT(3))
4036 data->in_scaled |= BIT(9); /* in9 is AVCC */
4037 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
4038 sio_data->type == it8783) {
4039 if (sio_data->internal & BIT(0))
4040 data->in_scaled |= BIT(3); /* in3 is VCC5V */
4041 if (sio_data->internal & BIT(1))
4042 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
4045 data->has_temp = 0x07;
4046 if (sio_data->skip_temp & BIT(2)) {
4047 if (sio_data->type == it8782 &&
4048 !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
4049 data->has_temp &= ~BIT(2);
4052 data->in_internal = sio_data->internal;
4053 data->has_in = 0x3ff & ~sio_data->skip_in;
4055 if (has_four_temp(data)) {
4056 data->has_temp |= BIT(3);
4057 } else if (has_six_temp(data)) {
4058 if (sio_data->type == it8655 || sio_data->type == it8665) {
4059 data->has_temp |= BIT(3) | BIT(4) | BIT(5);
4061 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
4063 /* Check for additional temperature sensors */
4064 if ((reg & 0x03) >= 0x02)
4065 data->has_temp |= BIT(3);
4066 if (((reg >> 2) & 0x03) >= 0x02)
4067 data->has_temp |= BIT(4);
4068 if (((reg >> 4) & 0x03) >= 0x02)
4069 data->has_temp |= BIT(5);
4071 /* Check for additional voltage sensors */
4072 if ((reg & 0x03) == 0x01)
4073 data->has_in |= BIT(10);
4074 if (((reg >> 2) & 0x03) == 0x01)
4075 data->has_in |= BIT(11);
4076 if (((reg >> 4) & 0x03) == 0x01)
4077 data->has_in |= BIT(12);
4081 data->has_beep = !!sio_data->beep_pin;
4083 /* Initialize the IT87 chip */
4084 it87_init_device(pdev);
4088 if (!sio_data->skip_vid) {
4089 data->has_vid = true;
4090 data->vrm = vid_which_vrm();
4091 /* VID reading from Super-I/O config space if available */
4092 data->vid = sio_data->vid_value;
4095 /* Prepare for sysfs hooks */
4096 data->groups[0] = &it87_group;
4097 data->groups[1] = &it87_group_in;
4098 data->groups[2] = &it87_group_temp;
4099 data->groups[3] = &it87_group_fan;
4101 if (enable_pwm_interface) {
4102 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4103 data->has_pwm &= ~sio_data->skip_pwm;
4105 data->groups[4] = &it87_group_pwm;
4106 if (has_old_autopwm(data) || has_newer_autopwm(data))
4107 data->groups[5] = &it87_group_auto_pwm;
4110 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4111 it87_devices[sio_data->type].name,
4112 data, data->groups);
4113 return PTR_ERR_OR_ZERO(hwmon_dev);
4116 static struct platform_driver it87_driver = {
4120 .probe = it87_probe,
4123 static int __init it87_device_add(int index, unsigned short sio_address,
4124 phys_addr_t mmio_address,
4125 const struct it87_sio_data *sio_data)
4127 struct platform_device *pdev;
4128 struct resource res = {
4134 res.start = mmio_address;
4135 res.end = mmio_address + 0x400 - 1;
4136 res.flags = IORESOURCE_MEM;
4138 res.start = sio_address + IT87_EC_OFFSET;
4139 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4140 res.flags = IORESOURCE_IO;
4143 err = acpi_check_resource_conflict(&res);
4145 if (!ignore_resource_conflict)
4149 pdev = platform_device_alloc(DRVNAME, sio_address);
4153 err = platform_device_add_resources(pdev, &res, 1);
4155 pr_err("Device resource addition failed (%d)\n", err);
4156 goto exit_device_put;
4159 err = platform_device_add_data(pdev, sio_data,
4160 sizeof(struct it87_sio_data));
4162 pr_err("Platform data allocation failed\n");
4163 goto exit_device_put;
4166 err = platform_device_add(pdev);
4168 pr_err("Device addition failed (%d)\n", err);
4169 goto exit_device_put;
4172 it87_pdev[index] = pdev;
4176 platform_device_put(pdev);
4180 struct it87_dmi_data {
4181 bool sio2_force_config; /* force sio2 into configuration mode */
4182 u8 skip_pwm; /* pwm channels to skip for this board */
4186 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4187 * (IT8792E) needs to be in configuration mode before accessing the first
4188 * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4189 * This needs to be done before accessing the first Super-IO chip since
4190 * the second chip may have been accessed prior to loading this driver.
4192 * The problem is also reported to affect IT8795E, which is used on X299 boards
4193 * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4194 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4196 * DMI entries for those systems will be added as they become available and
4197 * as the problem is confirmed to affect those boards.
4199 static struct it87_dmi_data gigabyte_sio2_force = {
4200 .sio2_force_config = true,
4204 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4205 * connected to a fan, but to something else. One user
4206 * has reported instant system power-off when changing
4207 * the PWM2 duty cycle, so we disable it.
4208 * I use the board name string as the trigger in case
4209 * the same board is ever used in other systems.
4211 static struct it87_dmi_data nvidia_fn68pt = {
4215 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4218 DMI_MATCH(DMI_SYS_VENDOR,
4219 "Gigabyte Technology Co., Ltd."),
4220 DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4222 .driver_data = &gigabyte_sio2_force,
4226 DMI_MATCH(DMI_SYS_VENDOR,
4227 "Gigabyte Technology Co., Ltd."),
4228 DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4230 .driver_data = &gigabyte_sio2_force,
4234 DMI_MATCH(DMI_SYS_VENDOR,
4235 "Gigabyte Technology Co., Ltd."),
4236 DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4238 .driver_data = &gigabyte_sio2_force,
4242 DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4243 DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4245 .driver_data = &nvidia_fn68pt,
4250 static int __init sm_it87_init(void)
4252 const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4253 struct it87_dmi_data *dmi_data = NULL;
4254 int sioaddr[2] = { REG_2E, REG_4E };
4255 struct it87_sio_data sio_data;
4256 unsigned short isa_address;
4257 phys_addr_t mmio_address;
4261 pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4264 dmi_data = dmi->driver_data;
4266 err = platform_driver_register(&it87_driver);
4270 if (dmi_data && dmi_data->sio2_force_config)
4271 __superio_enter(REG_4E);
4273 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4274 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4277 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4279 if (err || isa_address == 0)
4283 sio_data.skip_pwm |= dmi_data->skip_pwm;
4284 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4286 goto exit_dev_unregister;
4292 goto exit_unregister;
4296 exit_dev_unregister:
4297 /* NULL check handled by platform_device_unregister */
4298 platform_device_unregister(it87_pdev[0]);
4300 platform_driver_unregister(&it87_driver);
4304 static void __exit sm_it87_exit(void)
4306 /* NULL check handled by platform_device_unregister */
4307 platform_device_unregister(it87_pdev[1]);
4308 platform_device_unregister(it87_pdev[0]);
4309 platform_driver_unregister(&it87_driver);
4312 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4313 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4314 module_param(update_vbat, bool, 0000);
4315 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4316 module_param(fix_pwm_polarity, bool, 0000);
4317 MODULE_PARM_DESC(fix_pwm_polarity,
4318 "Force PWM polarity to active high (DANGEROUS)");
4319 MODULE_LICENSE("GPL");
4320 MODULE_VERSION(IT87_DRIVER_VERSION);
4322 module_init(sm_it87_init);
4323 module_exit(sm_it87_exit);