2 * clocks.c - figure out sclk/cclk/vco and such
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
10 #include <asm/blackfin.h>
12 /* Get the voltage input multiplier */
13 static u_long cached_vco_pll_ctl, cached_vco;
18 u_long pll_ctl = bfin_read_PLL_CTL();
19 if (pll_ctl == cached_vco_pll_ctl)
22 cached_vco_pll_ctl = pll_ctl;
24 msel = (pll_ctl >> 9) & 0x3F;
28 cached_vco = CONFIG_CLKIN_HZ;
29 cached_vco >>= (1 & pll_ctl); /* DF bit */
34 /* Get the Core clock */
35 static u_long cached_cclk_pll_div, cached_cclk;
40 if (bfin_read_PLL_STAT() & 0x1)
41 return CONFIG_CLKIN_HZ;
43 ssel = bfin_read_PLL_DIV();
44 if (ssel == cached_cclk_pll_div)
47 cached_cclk_pll_div = ssel;
49 csel = ((ssel >> 4) & 0x03);
51 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
52 cached_cclk = get_vco() / ssel;
54 cached_cclk = get_vco() >> csel;
58 /* Get the System clock */
59 static u_long cached_sclk_pll_div, cached_sclk;
64 if (bfin_read_PLL_STAT() & 0x1)
65 return CONFIG_CLKIN_HZ;
67 ssel = bfin_read_PLL_DIV();
68 if (ssel == cached_sclk_pll_div)
71 cached_sclk_pll_div = ssel;
75 cached_sclk = get_vco() / ssel;