git.sur5r.net Git - cc65/blob - libsrc/c128/c128.inc

   1 ;
   2 ; C64 generic definitions. Stolen from Elite128
   3 ;
   4
   5
   6 ; ---------------------------------------------------------------------------
   7 ; Zero page, Commodore stuff
   8
   9 ST              = $90           ; IEC status byte
  10
  11 TIME            = $A0           ; 60HZ clock
  12 FNAM_LEN        = $B7           ; Length of filename
  13 SECADR          = $B9           ; Secondary address
  14 DEVNUM          = $BA           ; Device number
  15 FNAM_LO         = $BB           ; Address of filename
  16 FNAM_HI         = $BC
  17 FNAM_BANK       = $C7           ; Bank for filename
  18 KEY_COUNT       = $D0           ; Number of keys in input buffer
  19 MODE            = $D7           ; 40/80 column mode flag
  20 CURS_X          = $EC           ; Cursor column
  21 CURS_Y          = $EB           ; Cursor row
  22 SCREEN_PTR      = $E0           ; Pointer to current char in text screen
  23 CRAM_PTR        = $E2           ; Pointer to current char in color RAM
  24
  25 CHARCOLOR       = $F1
  26 FKEY_COUNT      = $D1           ; Characters for function key
  27 PALFLAG         = $A03          ; $FF=PAL, $00=NTSC
  28 INIT_STATUS     = $A04          ; Flag: Reset/NMI Status
  29 FKEY_LEN        = $1000         ; Function key lengths
  30 FKEY_TEXT       = $100A         ; Function key texts
  31
  32 ; ---------------------------------------------------------------------------
  33 ; Kernal routines
  34
  35 ; Direct entries
  36 CURS_ON         = $CD6F
  37 CURS_OFF        = $CD9F
  38 CLRSCR          = $C142
  39 KBDREAD         = $C006
  40
  41 ; Extended jump table
  42 SETBNK          = $FF68
  43
  44 ; ---------------------------------------------------------------------------
  45 ; Vectors
  46
  47 IRQVec          = $0314
  48 BRKVec          = $0316
  49 NMIVec          = $0318
  50 KeyStoreVec     = $033C
  51
  52 ; ---------------------------------------------------------------------------
  53 ; I/O: VIC
  54
  55 VIC             = $D000
  56 VIC_SPR0_X      = $D000
  57 VIC_SPR0_Y      = $D001
  58 VIC_SPR1_X      = $D002
  59 VIC_SPR1_Y      = $D003
  60 VIC_SPR2_X      = $D004
  61 VIC_SPR2_Y      = $D005
  62 VIC_SPR3_X      = $D006
  63 VIC_SPR3_Y      = $D007
  64 VIC_SPR4_X      = $D008
  65 VIC_SPR4_Y      = $D009
  66 VIC_SPR5_X      = $D00A
  67 VIC_SPR5_Y      = $D00B
  68 VIC_SPR6_X      = $D00C
  69 VIC_SPR6_Y      = $D00D
  70 VIC_SPR7_X      = $D00E
  71 VIC_SPR7_Y      = $D00F
  72 VIC_SPR_HI_X    = $D010
  73 VIC_SPR_ENA     = $D015
  74 VIC_SPR_EXP_X   = $D017
  75 VIC_SPR_EXP_Y   = $D01D
  76 VIC_SPR_MCOLOR  = $D01C
  77 VIC_SPR_BG_PRIO = $D01B
  78
  79 VIC_SPR_MCOLOR0 = $D025
  80 VIC_SPR_MCOLOR1 = $D026
  81
  82 VIC_SPR0_COLOR  = $D027
  83 VIC_SPR1_COLOR  = $D028
  84 VIC_SPR2_COLOR  = $D029
  85 VIC_SPR3_COLOR  = $D02A
  86 VIC_SPR4_COLOR  = $D02B
  87 VIC_SPR5_COLOR  = $D02C
  88 VIC_SPR6_COLOR  = $D02D
  89 VIC_SPR7_COLOR  = $D02E
  90
  91 VIC_CTRL1       = $D011
  92 VIC_CTRL2       = $D016
  93
  94 VIC_HLINE       = $D012
  95
  96 VIC_VIDEO_ADR   = $D018
  97
  98 VIC_IRR         = $D019         ; Interrupt request register
  99 VIC_IMR         = $D01A         ; Interrupt mask register
 100
 101 VIC_BORDERCOLOR = $D020
 102 VIC_BG_COLOR0   = $D021
 103 VIC_BG_COLOR1   = $D022
 104 VIC_BG_COLOR2   = $D023
 105 VIC_BG_COLOR3   = $D024
 106
 107 ; 128 stuff:
 108 VIC_KBD_128     = $D02F         ; Extended kbd bits (visible in 64 mode)
 109 VIC_CLK_128     = $D030         ; Clock rate register (visible in 64 mode)
 110
 111
 112 ; ---------------------------------------------------------------------------
 113 ; I/O: SID
 114
 115 SID             = $D400
 116 SID_S1Lo        = $D400
 117 SID_S1Hi        = $D401
 118 SID_PB1Lo       = $D402
 119 SID_PB1Hi       = $D403
 120 SID_Ctl1        = $D404
 121 SID_AD1         = $D405
 122 SID_SUR1        = $D406
 123
 124 SID_S2Lo        = $D407
 125 SID_S2Hi        = $D408
 126 SID_PB2Lo       = $D409
 127 SID_PB2Hi       = $D40A
 128 SID_Ctl2        = $D40B
 129 SID_AD2         = $D40C
 130 SID_SUR2        = $D40D
 131
 132 SID_S3Lo        = $D40E
 133 SID_S3Hi        = $D40F
 134 SID_PB3Lo       = $D410
 135 SID_PB3Hi       = $D411
 136 SID_Ctl3        = $D412
 137 SID_AD3         = $D413
 138 SID_SUR3        = $D414
 139
 140 SID_FltLo       = $D415
 141 SID_FltHi       = $D416
 142 SID_FltCtl      = $D417
 143 SID_Amp         = $D418
 144 SID_ADConv1     = $D419
 145 SID_ADConv2     = $D41A
 146 SID_Noise       = $D41B
 147 SID_Read3       = $D41C
 148
 149 ; ---------------------------------------------------------------------------
 150 ; I/O: VDC (128 only)
 151
 152 VDC_INDEX       = $D600
 153 VDC_DATA        = $D601
 154
 155 ; ---------------------------------------------------------------------------
 156 ; I/O: CIAs
 157
 158 CIA1            = $DC00
 159 CIA1_PRA        = $DC00
 160 CIA1_PRB        = $DC01
 161 CIA1_DDRA       = $DC02
 162 CIA1_DDRB       = $DC03
 163 CIA1_ICR        = $DC0D
 164 CIA1_CRA        = $DC0E
 165 CIA1_CRB        = $DC0F
 166
 167 CIA2            = $DD00
 168 CIA2_PRA        = $DD00
 169 CIA2_PRB        = $DD01
 170 CIA2_DDRA       = $DD02
 171 CIA2_DDRB       = $DD03
 172 CIA2_ICR        = $DD0D
 173 CIA2_CRA        = $DD0E
 174 CIA2_CRB        = $DD0F
 175
 176 ; ---------------------------------------------------------------------------
 177 ; I/O: MMU
 178
 179 MMU_CR          = $FF00
 180 MMU_CFG_CC65    = %00001110     ; Bank 0 with kernal ROM
 181 MMU_CFG_RAM0    = %00111111     ; Bank 0 full RAM
 182
 183
 184 ; ---------------------------------------------------------------------------
 185 ; Super CPU
 186
 187 SCPU_VIC_Bank1  = $D075
 188 SCPU_Slow       = $D07A
 189 SCPU_Fast       = $D07B
 190 SCPU_EnableRegs = $D07E
 191 SCPU_DisableRegs= $D07F
 192 SCPU_Detect     = $D0BC
 193
 194