git.sur5r.net Git - cc65/blob - libsrc/c128/c128.inc

   1 ;
   2 ; C64 generic definitions. Stolen from Elite128
   3 ;
   4
   5
   6 ; ---------------------------------------------------------------------------
   7 ; Zero page, Commodore stuff
   8
   9 ST              = $90           ; IEC status byte
  10
  11 TIME            = $A0           ; 60HZ clock
  12 FNAM_LEN        = $B7           ; Length of filename
  13 SECADR          = $B9           ; Secondary address
  14 DEVNUM          = $BA           ; Device number
  15 FNAM_LO         = $BB           ; Address of filename
  16 FNAM_HI         = $BC
  17 FNAM_BANK       = $C7           ; Bank for filename
  18 KEY_COUNT       = $D0           ; Number of keys in input buffer
  19 MODE            = $D7           ; 40/80 column mode flag
  20 CURS_X          = $EC           ; Cursor column
  21 CURS_Y          = $EB           ; Cursor row
  22 SCREEN_PTR      = $E0           ; Pointer to current char in text screen
  23 CRAM_PTR        = $E2           ; Pointer to current char in color RAM
  24
  25 CHARCOLOR       = $F1
  26 FKEY_COUNT      = $D1           ; Characters for function key
  27 INIT_STATUS     = $A04          ; Flag: Reset/NMI Status
  28 FKEY_LEN        = $1000         ; Function key lengths
  29 FKEY_TEXT       = $100A         ; Function key texts
  30
  31 ; ---------------------------------------------------------------------------
  32 ; Kernal routines
  33
  34 ; Direct entries
  35 CURS_ON         = $CD6F
  36 CURS_OFF        = $CD9F
  37 CLRSCR          = $C142
  38 KBDREAD         = $C006
  39
  40 ; Extended jump table
  41 SETBNK          = $FF68
  42
  43 ; ---------------------------------------------------------------------------
  44 ; Vectors
  45
  46 IRQVec          = $0314
  47 BRKVec          = $0316
  48 NMIVec          = $0318
  49 KeyStoreVec     = $033C
  50
  51 ; ---------------------------------------------------------------------------
  52 ; I/O: VIC
  53
  54 VIC             = $D000
  55 VIC_SPR0_X      = $D000
  56 VIC_SPR0_Y      = $D001
  57 VIC_SPR1_X      = $D002
  58 VIC_SPR1_Y      = $D003
  59 VIC_SPR2_X      = $D004
  60 VIC_SPR2_Y      = $D005
  61 VIC_SPR3_X      = $D006
  62 VIC_SPR3_Y      = $D007
  63 VIC_SPR4_X      = $D008
  64 VIC_SPR4_Y      = $D009
  65 VIC_SPR5_X      = $D00A
  66 VIC_SPR5_Y      = $D00B
  67 VIC_SPR6_X      = $D00C
  68 VIC_SPR6_Y      = $D00D
  69 VIC_SPR7_X      = $D00E
  70 VIC_SPR7_Y      = $D00F
  71 VIC_SPR_HI_X    = $D010
  72 VIC_SPR_ENA     = $D015
  73 VIC_SPR_EXP_X   = $D017
  74 VIC_SPR_EXP_Y   = $D01D
  75 VIC_SPR_MCOLOR  = $D01C
  76 VIC_SPR_BG_PRIO = $D01B
  77
  78 VIC_SPR_MCOLOR0 = $D025
  79 VIC_SPR_MCOLOR1 = $D026
  80
  81 VIC_SPR0_COLOR  = $D027
  82 VIC_SPR1_COLOR  = $D028
  83 VIC_SPR2_COLOR  = $D029
  84 VIC_SPR3_COLOR  = $D02A
  85 VIC_SPR4_COLOR  = $D02B
  86 VIC_SPR5_COLOR  = $D02C
  87 VIC_SPR6_COLOR  = $D02D
  88 VIC_SPR7_COLOR  = $D02E
  89
  90 VIC_CTRL1       = $D011
  91 VIC_CTRL2       = $D016
  92
  93 VIC_HLINE       = $D012
  94
  95 VIC_VIDEO_ADR   = $D018
  96
  97 VIC_IRR         = $D019         ; Interrupt request register
  98 VIC_IMR         = $D01A         ; Interrupt mask register
  99
 100 VIC_BORDERCOLOR = $D020
 101 VIC_BG_COLOR0   = $D021
 102 VIC_BG_COLOR1   = $D022
 103 VIC_BG_COLOR2   = $D023
 104 VIC_BG_COLOR3   = $D024
 105
 106 ; 128 stuff:
 107 VIC_KBD_128     = $D02F         ; Extended kbd bits (visible in 64 mode)
 108 VIC_CLK_128     = $D030         ; Clock rate register (visible in 64 mode)
 109
 110
 111 ; ---------------------------------------------------------------------------
 112 ; I/O: SID
 113
 114 SID             = $D400
 115 SID_S1Lo        = $D400
 116 SID_S1Hi        = $D401
 117 SID_PB1Lo       = $D402
 118 SID_PB1Hi       = $D403
 119 SID_Ctl1        = $D404
 120 SID_AD1         = $D405
 121 SID_SUR1        = $D406
 122
 123 SID_S2Lo        = $D407
 124 SID_S2Hi        = $D408
 125 SID_PB2Lo       = $D409
 126 SID_PB2Hi       = $D40A
 127 SID_Ctl2        = $D40B
 128 SID_AD2         = $D40C
 129 SID_SUR2        = $D40D
 130
 131 SID_S3Lo        = $D40E
 132 SID_S3Hi        = $D40F
 133 SID_PB3Lo       = $D410
 134 SID_PB3Hi       = $D411
 135 SID_Ctl3        = $D412
 136 SID_AD3         = $D413
 137 SID_SUR3        = $D414
 138
 139 SID_FltLo       = $D415
 140 SID_FltHi       = $D416
 141 SID_FltCtl      = $D417
 142 SID_Amp         = $D418
 143 SID_ADConv1     = $D419
 144 SID_ADConv2     = $D41A
 145 SID_Noise       = $D41B
 146 SID_Read3       = $D41C
 147
 148 ; ---------------------------------------------------------------------------
 149 ; I/O: VDC (128 only)
 150
 151 VDC_INDEX       = $D600
 152 VDC_DATA        = $D601
 153
 154 ; ---------------------------------------------------------------------------
 155 ; I/O: CIAs
 156
 157 CIA1            = $DC00
 158 CIA1_PRA        = $DC00
 159 CIA1_PRB        = $DC01
 160 CIA1_DDRA       = $DC02
 161 CIA1_DDRB       = $DC03
 162 CIA1_ICR        = $DC0D
 163 CIA1_CRA        = $DC0E
 164 CIA1_CRB        = $DC0F
 165
 166 CIA2            = $DD00
 167 CIA2_PRA        = $DD00
 168 CIA2_PRB        = $DD01
 169 CIA2_DDRA       = $DD02
 170 CIA2_DDRB       = $DD03
 171 CIA2_ICR        = $DD0D
 172 CIA2_CRA        = $DD0E
 173 CIA2_CRB        = $DD0F
 174
 175 ; ---------------------------------------------------------------------------
 176 ; I/O: MMU
 177
 178 MMU_CR          = $FF00
 179 CC65_MMU_CFG    = $0E   ; Bank 0 with kernal ROM
 180
 181 ; ---------------------------------------------------------------------------
 182 ; Super CPU
 183
 184 SCPU_VIC_Bank1  = $D075
 185 SCPU_Slow       = $D07A
 186 SCPU_Fast       = $D07B
 187 SCPU_EnableRegs = $D07E
 188 SCPU_DisableRegs= $D07F
 189 SCPU_Detect     = $D0BC
 190
 191