git.sur5r.net Git - cc65/blob - libsrc/c128/c128.inc

   1 ;
   2 ; C64 generic definitions. Stolen from Elite128
   3 ;
   4
   5
   6 ; ---------------------------------------------------------------------------
   7 ; Zero page, Commodore stuff
   8
   9 ST              = $90           ; IEC status byte
  10
  11 TIME            = $A0           ; 60HZ clock
  12 FNAM_LEN        = $B7           ; Length of filename
  13 SECADR          = $B9           ; Secondary address
  14 DEVNUM          = $BA           ; Device number
  15 FNAM_BANK       = $C7           ; Bank for filename
  16 FNAM_LO         = $BB           ; Address of filename
  17 FNAM_HI         = $BC
  18 KEY_COUNT       = $D0           ; Number of keys in input buffer
  19 MODE            = $D7           ; 40/80 column mode flag
  20 CURS_X          = $EC           ; Cursor column
  21 CURS_Y          = $EB           ; Cursor row
  22 SCREEN_PTR      = $E0           ; Pointer to current char in text screen
  23 CRAM_PTR        = $E2           ; Pointer to current char in color RAM
  24
  25 CHARCOLOR       = $F1
  26 FKEY_COUNT      = $D1           ; Characters for function key
  27 INIT_STATUS     = $A04          ; Flag: Reset/NMI Status
  28 FKEY_LEN        = $1000         ; Function key lengths
  29 FKEY_TEXT       = $100A         ; Function key texts
  30
  31 ; ---------------------------------------------------------------------------
  32 ; Kernal routines
  33
  34 ; Direct entries
  35 CURS_ON         = $CD6F
  36 CURS_OFF        = $CD9F
  37 CLRSCR          = $C142
  38 KBDREAD         = $C006
  39
  40 ; ---------------------------------------------------------------------------
  41 ; Vectors
  42
  43 IRQVec          = $0314
  44 BRKVec          = $0316
  45 NMIVec          = $0318
  46 KeyStoreVec     = $033C
  47
  48 ; ---------------------------------------------------------------------------
  49 ; I/O: VIC
  50
  51 VIC             = $D000
  52 VIC_SPR0_X      = $D000
  53 VIC_SPR0_Y      = $D001
  54 VIC_SPR1_X      = $D002
  55 VIC_SPR1_Y      = $D003
  56 VIC_SPR2_X      = $D004
  57 VIC_SPR2_Y      = $D005
  58 VIC_SPR3_X      = $D006
  59 VIC_SPR3_Y      = $D007
  60 VIC_SPR4_X      = $D008
  61 VIC_SPR4_Y      = $D009
  62 VIC_SPR5_X      = $D00A
  63 VIC_SPR5_Y      = $D00B
  64 VIC_SPR6_X      = $D00C
  65 VIC_SPR6_Y      = $D00D
  66 VIC_SPR7_X      = $D00E
  67 VIC_SPR7_Y      = $D00F
  68 VIC_SPR_HI_X    = $D010
  69 VIC_SPR_ENA     = $D015
  70 VIC_SPR_EXP_X   = $D017
  71 VIC_SPR_EXP_Y   = $D01D
  72 VIC_SPR_MCOLOR  = $D01C
  73 VIC_SPR_BG_PRIO = $D01B
  74
  75 VIC_SPR_MCOLOR0 = $D025
  76 VIC_SPR_MCOLOR1 = $D026
  77
  78 VIC_SPR0_COLOR  = $D027
  79 VIC_SPR1_COLOR  = $D028
  80 VIC_SPR2_COLOR  = $D029
  81 VIC_SPR3_COLOR  = $D02A
  82 VIC_SPR4_COLOR  = $D02B
  83 VIC_SPR5_COLOR  = $D02C
  84 VIC_SPR6_COLOR  = $D02D
  85 VIC_SPR7_COLOR  = $D02E
  86
  87 VIC_CTRL1       = $D011
  88 VIC_CTRL2       = $D016
  89
  90 VIC_HLINE       = $D012
  91
  92 VIC_VIDEO_ADR   = $D018
  93
  94 VIC_IRR         = $D019         ; Interrupt request register
  95 VIC_IMR         = $D01A         ; Interrupt mask register
  96
  97 VIC_BORDERCOLOR = $D020
  98 VIC_BG_COLOR0   = $D021
  99 VIC_BG_COLOR1   = $D022
 100 VIC_BG_COLOR2   = $D023
 101 VIC_BG_COLOR3   = $D024
 102
 103 ; 128 stuff:
 104 VIC_KBD_128     = $D02F         ; Extended kbd bits (visible in 64 mode)
 105 VIC_CLK_128     = $D030         ; Clock rate register (visible in 64 mode)
 106
 107
 108 ; ---------------------------------------------------------------------------
 109 ; I/O: SID
 110
 111 SID             = $D400
 112 SID_S1Lo        = $D400
 113 SID_S1Hi        = $D401
 114 SID_PB1Lo       = $D402
 115 SID_PB1Hi       = $D403
 116 SID_Ctl1        = $D404
 117 SID_AD1         = $D405
 118 SID_SUR1        = $D406
 119
 120 SID_S2Lo        = $D407
 121 SID_S2Hi        = $D408
 122 SID_PB2Lo       = $D409
 123 SID_PB2Hi       = $D40A
 124 SID_Ctl2        = $D40B
 125 SID_AD2         = $D40C
 126 SID_SUR2        = $D40D
 127
 128 SID_S3Lo        = $D40E
 129 SID_S3Hi        = $D40F
 130 SID_PB3Lo       = $D410
 131 SID_PB3Hi       = $D411
 132 SID_Ctl3        = $D412
 133 SID_AD3         = $D413
 134 SID_SUR3        = $D414
 135
 136 SID_FltLo       = $D415
 137 SID_FltHi       = $D416
 138 SID_FltCtl      = $D417
 139 SID_Amp         = $D418
 140 SID_ADConv1     = $D419
 141 SID_ADConv2     = $D41A
 142 SID_Noise       = $D41B
 143 SID_Read3       = $D41C
 144
 145 ; ---------------------------------------------------------------------------
 146 ; I/O: VDC (128 only)
 147
 148 VDC_INDEX       = $D600
 149 VDC_DATA        = $D601
 150
 151 ; ---------------------------------------------------------------------------
 152 ; I/O: CIAs
 153
 154 CIA1            = $DC00
 155 CIA1_PRA        = $DC00
 156 CIA1_PRB        = $DC01
 157 CIA1_DDRA       = $DC02
 158 CIA1_DDRB       = $DC03
 159 CIA1_ICR        = $DC0D
 160 CIA1_CRA        = $DC0E
 161 CIA1_CRB        = $DC0F
 162
 163 CIA2            = $DD00
 164 CIA2_PRA        = $DD00
 165 CIA2_PRB        = $DD01
 166 CIA2_DDRA       = $DD02
 167 CIA2_DDRB       = $DD03
 168 CIA2_ICR        = $DD0D
 169 CIA2_CRA        = $DD0E
 170 CIA2_CRB        = $DD0F
 171
 172 ; ---------------------------------------------------------------------------
 173 ; I/O: MMU
 174
 175 MMU_CR          = $FF00
 176 CC65_MMU_CFG    = $0E   ; Bank 0 with kernal ROM
 177
 178 ; ---------------------------------------------------------------------------
 179 ; Super CPU
 180
 181 SCPU_VIC_Bank1  = $D075
 182 SCPU_Slow       = $D07A
 183 SCPU_Fast       = $D07B
 184 SCPU_EnableRegs = $D07E
 185 SCPU_DisableRegs= $D07F
 186 SCPU_Detect     = $D0BC
 187
 188