git.sur5r.net Git - cc65/blob - libsrc/c128/c128.inc

   1 ;
   2 ; C64 generic definitions. Stolen from Elite128
   3 ;
   4
   5
   6 ; ---------------------------------------------------------------------------
   7 ; Zero page, Commodore stuff
   8
   9 ST              = $90           ; IEC status byte
  10
  11 TIME            = $A0           ; 60HZ clock
  12 FNAM_LEN        = $B7           ; Length of filename
  13 SECADR          = $B9           ; Secondary address
  14 DEVNUM          = $BA           ; Device number
  15 FNAM_LO         = $BB           ; Address of filename
  16 FNAM_HI         = $BC
  17 FNAM_BANK       = $C7           ; Bank for filename
  18 KEY_COUNT       = $D0           ; Number of keys in input buffer
  19 MODE            = $D7           ; 40/80 column mode flag
  20 CURS_X          = $EC           ; Cursor column
  21 CURS_Y          = $EB           ; Cursor row
  22 SCREEN_PTR      = $E0           ; Pointer to current char in text screen
  23 CRAM_PTR        = $E2           ; Pointer to current char in color RAM
  24
  25 CHARCOLOR       = $F1
  26 FKEY_COUNT      = $D1           ; Characters for function key
  27 FETCH           = $2A2          ; Fetch subroutine in RAM
  28 FETVEC          = $2AA          ; Vector patch location for FETCH
  29 STASH           = $2AF          ; Stash routine in RAM
  30 STAVEC          = $2B9          ; Vector patch location for STASH
  31 PALFLAG         = $A03          ; $FF=PAL, $00=NTSC
  32 INIT_STATUS     = $A04          ; Flag: Reset/NMI Status
  33 FKEY_LEN        = $1000         ; Function key lengths
  34 FKEY_TEXT       = $100A         ; Function key texts
  35
  36 ; ---------------------------------------------------------------------------
  37 ; Kernal routines
  38
  39 ; Direct entries
  40 CURS_ON         = $CD6F
  41 CURS_OFF        = $CD9F
  42 CLRSCR          = $C142
  43 KBDREAD         = $C006
  44
  45 ; Extended jump table
  46 SETBNK          = $FF68
  47
  48 ; ---------------------------------------------------------------------------
  49 ; Vectors
  50
  51 IRQVec          = $0314
  52 BRKVec          = $0316
  53 NMIVec          = $0318
  54 KeyStoreVec     = $033C
  55
  56 ; ---------------------------------------------------------------------------
  57 ; I/O: VIC
  58
  59 VIC             = $D000
  60 VIC_SPR0_X      = $D000
  61 VIC_SPR0_Y      = $D001
  62 VIC_SPR1_X      = $D002
  63 VIC_SPR1_Y      = $D003
  64 VIC_SPR2_X      = $D004
  65 VIC_SPR2_Y      = $D005
  66 VIC_SPR3_X      = $D006
  67 VIC_SPR3_Y      = $D007
  68 VIC_SPR4_X      = $D008
  69 VIC_SPR4_Y      = $D009
  70 VIC_SPR5_X      = $D00A
  71 VIC_SPR5_Y      = $D00B
  72 VIC_SPR6_X      = $D00C
  73 VIC_SPR6_Y      = $D00D
  74 VIC_SPR7_X      = $D00E
  75 VIC_SPR7_Y      = $D00F
  76 VIC_SPR_HI_X    = $D010
  77 VIC_SPR_ENA     = $D015
  78 VIC_SPR_EXP_X   = $D017
  79 VIC_SPR_EXP_Y   = $D01D
  80 VIC_SPR_MCOLOR  = $D01C
  81 VIC_SPR_BG_PRIO = $D01B
  82
  83 VIC_SPR_MCOLOR0 = $D025
  84 VIC_SPR_MCOLOR1 = $D026
  85
  86 VIC_SPR0_COLOR  = $D027
  87 VIC_SPR1_COLOR  = $D028
  88 VIC_SPR2_COLOR  = $D029
  89 VIC_SPR3_COLOR  = $D02A
  90 VIC_SPR4_COLOR  = $D02B
  91 VIC_SPR5_COLOR  = $D02C
  92 VIC_SPR6_COLOR  = $D02D
  93 VIC_SPR7_COLOR  = $D02E
  94
  95 VIC_CTRL1       = $D011
  96 VIC_CTRL2       = $D016
  97
  98 VIC_HLINE       = $D012
  99
 100 VIC_VIDEO_ADR   = $D018
 101
 102 VIC_IRR         = $D019         ; Interrupt request register
 103 VIC_IMR         = $D01A         ; Interrupt mask register
 104
 105 VIC_BORDERCOLOR = $D020
 106 VIC_BG_COLOR0   = $D021
 107 VIC_BG_COLOR1   = $D022
 108 VIC_BG_COLOR2   = $D023
 109 VIC_BG_COLOR3   = $D024
 110
 111 ; 128 stuff:
 112 VIC_KBD_128     = $D02F         ; Extended kbd bits (visible in 64 mode)
 113 VIC_CLK_128     = $D030         ; Clock rate register (visible in 64 mode)
 114
 115
 116 ; ---------------------------------------------------------------------------
 117 ; I/O: SID
 118
 119 SID             = $D400
 120 SID_S1Lo        = $D400
 121 SID_S1Hi        = $D401
 122 SID_PB1Lo       = $D402
 123 SID_PB1Hi       = $D403
 124 SID_Ctl1        = $D404
 125 SID_AD1         = $D405
 126 SID_SUR1        = $D406
 127
 128 SID_S2Lo        = $D407
 129 SID_S2Hi        = $D408
 130 SID_PB2Lo       = $D409
 131 SID_PB2Hi       = $D40A
 132 SID_Ctl2        = $D40B
 133 SID_AD2         = $D40C
 134 SID_SUR2        = $D40D
 135
 136 SID_S3Lo        = $D40E
 137 SID_S3Hi        = $D40F
 138 SID_PB3Lo       = $D410
 139 SID_PB3Hi       = $D411
 140 SID_Ctl3        = $D412
 141 SID_AD3         = $D413
 142 SID_SUR3        = $D414
 143
 144 SID_FltLo       = $D415
 145 SID_FltHi       = $D416
 146 SID_FltCtl      = $D417
 147 SID_Amp         = $D418
 148 SID_ADConv1     = $D419
 149 SID_ADConv2     = $D41A
 150 SID_Noise       = $D41B
 151 SID_Read3       = $D41C
 152
 153 ; ---------------------------------------------------------------------------
 154 ; I/O: VDC (128 only)
 155
 156 VDC_INDEX       = $D600
 157 VDC_DATA        = $D601
 158
 159 ; ---------------------------------------------------------------------------
 160 ; I/O: CIAs
 161
 162 CIA1            = $DC00
 163 CIA1_PRA        = $DC00
 164 CIA1_PRB        = $DC01
 165 CIA1_DDRA       = $DC02
 166 CIA1_DDRB       = $DC03
 167 CIA1_ICR        = $DC0D
 168 CIA1_CRA        = $DC0E
 169 CIA1_CRB        = $DC0F
 170
 171 CIA2            = $DD00
 172 CIA2_PRA        = $DD00
 173 CIA2_PRB        = $DD01
 174 CIA2_DDRA       = $DD02
 175 CIA2_DDRB       = $DD03
 176 CIA2_ICR        = $DD0D
 177 CIA2_CRA        = $DD0E
 178 CIA2_CRB        = $DD0F
 179
 180 ; ---------------------------------------------------------------------------
 181 ; I/O: MMU
 182
 183 MMU_CR          = $FF00
 184 MMU_CFG_CC65    = %00001110     ; Bank 0 with kernal ROM
 185 MMU_CFG_RAM0    = %00111111     ; Bank 0 full RAM
 186 MMU_CFG_RAM1    = %01111111     ; Bank 1 full RAM
 187
 188 ; ---------------------------------------------------------------------------
 189 ; Super CPU
 190
 191 SCPU_VIC_Bank1  = $D075
 192 SCPU_Slow       = $D07A
 193 SCPU_Fast       = $D07B
 194 SCPU_EnableRegs = $D07E
 195 SCPU_DisableRegs= $D07F
 196 SCPU_Detect     = $D0BC
 197
 198