git.sur5r.net Git - cc65/blob - libsrc/c128/c128.inc

   1 ;
   2 ; C64 generic definitions. Stolen from Elite128
   3 ;
   4
   5
   6 ; ---------------------------------------------------------------------------
   7 ; Zero page, Commodore stuff
   8
   9 ST              = $90           ; IEC status byte
  10
  11 TIME            = $A0           ; 60HZ clock
  12 FNAM_LEN        = $B7           ; Length of filename
  13 SECADR          = $B9           ; Secondary address
  14 DEVNUM          = $BA           ; Device number
  15 FNAM_LO         = $BB           ; Address of filename
  16 FNAM_HI         = $BC
  17 FNAM_BANK       = $C7           ; Bank for filename
  18 KEY_COUNT       = $D0           ; Number of keys in input buffer
  19 FKEY_COUNT      = $D1           ; Characters for function key
  20 MODE            = $D7           ; 40/80 column mode flag
  21 CURS_X          = $EC           ; Cursor column
  22 CURS_Y          = $EB           ; Cursor row
  23 SCREEN_PTR      = $E0           ; Pointer to current char in text screen
  24 CRAM_PTR        = $E2           ; Pointer to current char in color RAM
  25
  26 CHARCOLOR       = $F1
  27 RVS             = $F3           ; Reverse output flag
  28 SCROLL          = $F8           ; Disable scrolling flag
  29 FETCH           = $2A2          ; Fetch subroutine in RAM
  30 FETVEC          = $2AA          ; Vector patch location for FETCH
  31 STASH           = $2AF          ; Stash routine in RAM
  32 STAVEC          = $2B9          ; Vector patch location for STASH
  33 PALFLAG         = $A03          ; $FF=PAL, $00=NTSC
  34 INIT_STATUS     = $A04          ; Flag: Reset/NMI Status
  35 FKEY_LEN        = $1000         ; Function key lengths
  36 FKEY_TEXT       = $100A         ; Function key texts
  37
  38 ; ---------------------------------------------------------------------------
  39 ; Kernal routines
  40
  41 ; Direct entries
  42 CURS_SET        = $CD57
  43 CURS_ON         = $CD6F
  44 CURS_OFF        = $CD9F
  45 CLRSCR          = $C142
  46 KBDREAD         = $C006
  47 NEWLINE         = $C363
  48 PRINT           = $C322
  49
  50 ; Extended jump table
  51 C64MODE         = $FF4D
  52 SWAPPER         = $FF5F
  53 SETBNK          = $FF68
  54
  55 ; ---------------------------------------------------------------------------
  56 ; Vectors
  57
  58 IRQVec          = $0314
  59 BRKVec          = $0316
  60 NMIVec          = $0318
  61 KeyStoreVec     = $033C
  62
  63 ; ---------------------------------------------------------------------------
  64 ; I/O: VIC
  65
  66 VIC             = $D000
  67 VIC_SPR0_X      = $D000
  68 VIC_SPR0_Y      = $D001
  69 VIC_SPR1_X      = $D002
  70 VIC_SPR1_Y      = $D003
  71 VIC_SPR2_X      = $D004
  72 VIC_SPR2_Y      = $D005
  73 VIC_SPR3_X      = $D006
  74 VIC_SPR3_Y      = $D007
  75 VIC_SPR4_X      = $D008
  76 VIC_SPR4_Y      = $D009
  77 VIC_SPR5_X      = $D00A
  78 VIC_SPR5_Y      = $D00B
  79 VIC_SPR6_X      = $D00C
  80 VIC_SPR6_Y      = $D00D
  81 VIC_SPR7_X      = $D00E
  82 VIC_SPR7_Y      = $D00F
  83 VIC_SPR_HI_X    = $D010
  84 VIC_SPR_ENA     = $D015
  85 VIC_SPR_EXP_X   = $D017
  86 VIC_SPR_EXP_Y   = $D01D
  87 VIC_SPR_MCOLOR  = $D01C
  88 VIC_SPR_BG_PRIO = $D01B
  89
  90 VIC_SPR_MCOLOR0 = $D025
  91 VIC_SPR_MCOLOR1 = $D026
  92
  93 VIC_SPR0_COLOR  = $D027
  94 VIC_SPR1_COLOR  = $D028
  95 VIC_SPR2_COLOR  = $D029
  96 VIC_SPR3_COLOR  = $D02A
  97 VIC_SPR4_COLOR  = $D02B
  98 VIC_SPR5_COLOR  = $D02C
  99 VIC_SPR6_COLOR  = $D02D
 100 VIC_SPR7_COLOR  = $D02E
 101
 102 VIC_CTRL1       = $D011
 103 VIC_CTRL2       = $D016
 104
 105 VIC_HLINE       = $D012
 106
 107 VIC_VIDEO_ADR   = $D018
 108
 109 VIC_IRR         = $D019         ; Interrupt request register
 110 VIC_IMR         = $D01A         ; Interrupt mask register
 111
 112 VIC_BORDERCOLOR = $D020
 113 VIC_BG_COLOR0   = $D021
 114 VIC_BG_COLOR1   = $D022
 115 VIC_BG_COLOR2   = $D023
 116 VIC_BG_COLOR3   = $D024
 117
 118 ; 128 stuff:
 119 VIC_KBD_128     = $D02F         ; Extended kbd bits (visible in 64 mode)
 120 VIC_CLK_128     = $D030         ; Clock rate register (visible in 64 mode)
 121
 122
 123 ; ---------------------------------------------------------------------------
 124 ; I/O: SID
 125
 126 SID             = $D400
 127 SID_S1Lo        = $D400
 128 SID_S1Hi        = $D401
 129 SID_PB1Lo       = $D402
 130 SID_PB1Hi       = $D403
 131 SID_Ctl1        = $D404
 132 SID_AD1         = $D405
 133 SID_SUR1        = $D406
 134
 135 SID_S2Lo        = $D407
 136 SID_S2Hi        = $D408
 137 SID_PB2Lo       = $D409
 138 SID_PB2Hi       = $D40A
 139 SID_Ctl2        = $D40B
 140 SID_AD2         = $D40C
 141 SID_SUR2        = $D40D
 142
 143 SID_S3Lo        = $D40E
 144 SID_S3Hi        = $D40F
 145 SID_PB3Lo       = $D410
 146 SID_PB3Hi       = $D411
 147 SID_Ctl3        = $D412
 148 SID_AD3         = $D413
 149 SID_SUR3        = $D414
 150
 151 SID_FltLo       = $D415
 152 SID_FltHi       = $D416
 153 SID_FltCtl      = $D417
 154 SID_Amp         = $D418
 155 SID_ADConv1     = $D419
 156 SID_ADConv2     = $D41A
 157 SID_Noise       = $D41B
 158 SID_Read3       = $D41C
 159
 160 ; ---------------------------------------------------------------------------
 161 ; I/O: VDC (128 only)
 162
 163 VDC_INDEX       = $D600
 164 VDC_DATA        = $D601
 165
 166 ; ---------------------------------------------------------------------------
 167 ; I/O: CIAs
 168
 169 CIA1            = $DC00
 170 CIA1_PRA        = $DC00
 171 CIA1_PRB        = $DC01
 172 CIA1_DDRA       = $DC02
 173 CIA1_DDRB       = $DC03
 174 CIA1_ICR        = $DC0D
 175 CIA1_CRA        = $DC0E
 176 CIA1_CRB        = $DC0F
 177
 178 CIA2            = $DD00
 179 CIA2_PRA        = $DD00
 180 CIA2_PRB        = $DD01
 181 CIA2_DDRA       = $DD02
 182 CIA2_DDRB       = $DD03
 183 CIA2_ICR        = $DD0D
 184 CIA2_CRA        = $DD0E
 185 CIA2_CRB        = $DD0F
 186
 187 ; ---------------------------------------------------------------------------
 188 ; I/O: MMU
 189
 190 MMU_CR          = $FF00
 191 MMU_CFG_CC65    = %00001110     ; Bank 0 with kernal ROM
 192 MMU_CFG_RAM0    = %00111111     ; Bank 0 full RAM
 193 MMU_CFG_RAM1    = %01111111     ; Bank 1 full RAM
 194
 195 ; ---------------------------------------------------------------------------
 196 ; Super CPU
 197
 198 SCPU_VIC_Bank1  = $D075
 199 SCPU_Slow       = $D07A
 200 SCPU_Fast       = $D07B
 201 SCPU_EnableRegs = $D07E
 202 SCPU_DisableRegs= $D07F
 203 SCPU_Detect     = $D0BC
 204
 205