2 * Copyright 2007 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
35 const qe_iop_conf_t qe_iop_conf_tab[] = {
37 {4, 10, 1, 0, 2}, /* TxD0 */
38 {4, 9, 1, 0, 2}, /* TxD1 */
39 {4, 8, 1, 0, 2}, /* TxD2 */
40 {4, 7, 1, 0, 2}, /* TxD3 */
41 {4, 23, 1, 0, 2}, /* TxD4 */
42 {4, 22, 1, 0, 2}, /* TxD5 */
43 {4, 21, 1, 0, 2}, /* TxD6 */
44 {4, 20, 1, 0, 2}, /* TxD7 */
45 {4, 15, 2, 0, 2}, /* RxD0 */
46 {4, 14, 2, 0, 2}, /* RxD1 */
47 {4, 13, 2, 0, 2}, /* RxD2 */
48 {4, 12, 2, 0, 2}, /* RxD3 */
49 {4, 29, 2, 0, 2}, /* RxD4 */
50 {4, 28, 2, 0, 2}, /* RxD5 */
51 {4, 27, 2, 0, 2}, /* RxD6 */
52 {4, 26, 2, 0, 2}, /* RxD7 */
53 {4, 11, 1, 0, 2}, /* TX_EN */
54 {4, 24, 1, 0, 2}, /* TX_ER */
55 {4, 16, 2, 0, 2}, /* RX_DV */
56 {4, 30, 2, 0, 2}, /* RX_ER */
57 {4, 17, 2, 0, 2}, /* RX_CLK */
58 {4, 19, 1, 0, 2}, /* GTX_CLK */
59 {1, 31, 2, 0, 3}, /* GTX125 */
62 {5, 10, 1, 0, 2}, /* TxD0 */
63 {5, 9, 1, 0, 2}, /* TxD1 */
64 {5, 8, 1, 0, 2}, /* TxD2 */
65 {5, 7, 1, 0, 2}, /* TxD3 */
66 {5, 23, 1, 0, 2}, /* TxD4 */
67 {5, 22, 1, 0, 2}, /* TxD5 */
68 {5, 21, 1, 0, 2}, /* TxD6 */
69 {5, 20, 1, 0, 2}, /* TxD7 */
70 {5, 15, 2, 0, 2}, /* RxD0 */
71 {5, 14, 2, 0, 2}, /* RxD1 */
72 {5, 13, 2, 0, 2}, /* RxD2 */
73 {5, 12, 2, 0, 2}, /* RxD3 */
74 {5, 29, 2, 0, 2}, /* RxD4 */
75 {5, 28, 2, 0, 2}, /* RxD5 */
76 {5, 27, 2, 0, 3}, /* RxD6 */
77 {5, 26, 2, 0, 2}, /* RxD7 */
78 {5, 11, 1, 0, 2}, /* TX_EN */
79 {5, 24, 1, 0, 2}, /* TX_ER */
80 {5, 16, 2, 0, 2}, /* RX_DV */
81 {5, 30, 2, 0, 2}, /* RX_ER */
82 {5, 17, 2, 0, 2}, /* RX_CLK */
83 {5, 19, 1, 0, 2}, /* GTX_CLK */
84 {1, 31, 2, 0, 3}, /* GTX125 */
85 {4, 6, 3, 0, 2}, /* MDIO */
86 {4, 5, 1, 0, 2}, /* MDC */
87 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
91 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
92 extern void ddr_enable_ecc(unsigned int dram_size);
95 extern long int spd_sdram(void);
97 void local_bus_init(void);
98 void sdram_init(void);
100 int board_early_init_f (void)
103 * Initialize local bus.
107 enable_8568mds_duart();
108 enable_8568mds_flash_write();
109 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
110 enable_8568mds_qe_mdio();
113 #ifdef CFG_I2C2_OFFSET
114 /* Enable I2C2_SCL and I2C2_SDA */
115 volatile struct par_io *port_c;
116 port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
117 port_c->cpdir2 |= 0x0f000000;
118 port_c->cppar2 &= ~0x0f000000;
119 port_c->cppar2 |= 0x0a000000;
125 int checkboard (void)
127 printf ("Board: 8568 MDS\n");
133 initdram(int board_type)
136 volatile immap_t *immap = (immap_t *)CFG_IMMR;
138 puts("Initializing\n");
140 #if defined(CONFIG_DDR_DLL)
143 * Work around to stabilize DDR DLL MSYNC_IN.
144 * Errata DDR9 seems to have been fixed.
145 * This is now the workaround for Errata DDR11:
146 * Override DLL = 1, Course Adj = 1, Tap Select = 0
149 volatile ccsr_gur_t *gur= &immap->im_gur;
151 gur->ddrdllcr = 0x81000000;
152 asm("sync;isync;msync");
156 dram_size = spd_sdram();
158 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
160 * Initialize and enable DDR ECC.
162 ddr_enable_ecc(dram_size);
165 * SDRAM Initialization
174 * Initialize Local Bus
179 volatile immap_t *immap = (immap_t *)CFG_IMMR;
180 volatile ccsr_gur_t *gur = &immap->im_gur;
181 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
187 get_sys_info(&sysinfo);
188 clkdiv = (lbc->lcrr & 0x0f) * 2;
189 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
191 gur->lbiuiplldcr1 = 0x00078080;
193 gur->lbiuiplldcr0 = 0x7c0f1bf0;
194 } else if (clkdiv == 8) {
195 gur->lbiuiplldcr0 = 0x6c0f1bf0;
196 } else if (clkdiv == 4) {
197 gur->lbiuiplldcr0 = 0x5c0f1bf0;
200 lbc->lcrr |= 0x00030000;
202 asm("sync;isync;msync");
206 * Initialize SDRAM memory on the Local Bus.
211 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
214 volatile immap_t *immap = (immap_t *)CFG_IMMR;
215 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
216 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
221 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
224 * Setup SDRAM Base and Option Registers
226 lbc->or2 = CFG_OR2_PRELIM;
229 lbc->br2 = CFG_BR2_PRELIM;
232 lbc->lbcr = CFG_LBC_LBCR;
236 lbc->lsrt = CFG_LBC_LSRT;
237 lbc->mrtpr = CFG_LBC_MRTPR;
241 * MPC8568 uses "new" 15-16 style addressing.
243 lsdmr_common = CFG_LBC_LSDMR_COMMON;
244 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
247 * Issue PRECHARGE ALL command.
249 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
252 ppcDcbf((unsigned long) sdram_addr);
256 * Issue 8 AUTO REFRESH commands.
258 for (idx = 0; idx < 8; idx++) {
259 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
262 ppcDcbf((unsigned long) sdram_addr);
267 * Issue 8 MODE-set command.
269 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
272 ppcDcbf((unsigned long) sdram_addr);
276 * Issue NORMAL OP command.
278 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
281 ppcDcbf((unsigned long) sdram_addr);
282 udelay(200); /* Overkill. Must wait > 200 bus cycles */
284 #endif /* enable SDRAM init */
287 #if defined(CFG_DRAM_TEST)
291 uint *pstart = (uint *) CFG_MEMTEST_START;
292 uint *pend = (uint *) CFG_MEMTEST_END;
295 printf("Testing DRAM from 0x%08x to 0x%08x\n",
299 printf("DRAM test phase 1:\n");
300 for (p = pstart; p < pend; p++)
303 for (p = pstart; p < pend; p++) {
304 if (*p != 0xaaaaaaaa) {
305 printf ("DRAM test fails at: %08x\n", (uint) p);
310 printf("DRAM test phase 2:\n");
311 for (p = pstart; p < pend; p++)
314 for (p = pstart; p < pend; p++) {
315 if (*p != 0x55555555) {
316 printf ("DRAM test fails at: %08x\n", (uint) p);
321 printf("DRAM test passed.\n");
326 #if defined(CONFIG_PCI)
327 #ifndef CONFIG_PCI_PNP
328 static struct pci_config_table pci_mpc8568mds_config_table[] = {
330 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
331 pci_cfgfunc_config_device,
334 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
340 static struct pci_controller hose[] = {
342 #ifndef CONFIG_PCI_PNP
343 config_table: pci_mpc8568mds_config_table,
348 #endif /* CONFIG_PCI */
351 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
356 u8 val8, orig_i2c_bus;
358 * Assign PIB PMC2/3 to PCI bus
361 /*switch temporarily to I2C bus #2 */
362 orig_i2c_bus = i2c_get_bus_num();
366 i2c_write(0x23, 0x6, 1, &val8, 1);
367 i2c_write(0x23, 0x7, 1, &val8, 1);
369 i2c_write(0x23, 0x2, 1, &val8, 1);
370 i2c_write(0x23, 0x3, 1, &val8, 1);
373 i2c_write(0x26, 0x6, 1, &val8, 1);
375 i2c_write(0x26, 0x7, 1, &val8, 1);
377 i2c_write(0x26, 0x2, 1, &val8, 1);
379 i2c_write(0x26, 0x3, 1, &val8, 1);
382 i2c_write(0x27, 0x6, 1, &val8, 1);
383 i2c_write(0x27, 0x7, 1, &val8, 1);
385 i2c_write(0x27, 0x2, 1, &val8, 1);
387 i2c_write(0x27, 0x3, 1, &val8, 1);
397 pci_mpc85xx_init(hose);