2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/immap_85xx.h>
28 #include <asm/fsl_ddr_sdram.h>
29 #include <asm/fsl_law.h>
30 #include <asm/global_data.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 unsigned long ddr_freq_mhz;
38 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
40 u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
42 __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
43 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
44 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
45 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
46 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
48 if (ddr_freq_mhz < 700) {
49 __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
50 __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
51 __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
52 __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
53 __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
54 __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
55 __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
56 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
57 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
59 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
60 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
61 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
62 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
63 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
64 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
65 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
66 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
67 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
70 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
71 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
72 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
74 /* P1014 and it's derivatives support max 16bit DDR width */
75 if (svr == SVR_P1014) {
76 __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
77 __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
78 /* For CS0_BNDS we divide the start and end address by 2, so we can just
79 * shift the entire register to achieve the desired result and the mask
80 * the value so we don't write reserved fields */
81 __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
86 /* Let the controller go */
87 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
89 set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
92 void board_init_f(ulong bootflag)
94 u32 plat_ratio, ddr_ratio;
95 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
97 /* initialize selected port with appropriate baud rate */
98 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
100 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
102 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
103 ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
104 ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
106 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
107 gd->bus_clk / 16 / CONFIG_BAUDRATE);
109 puts("\nNAND boot... ");
111 /* Initialize the DDR3 */
114 /* copy code to RAM and jump to it - this should not return */
115 /* NOTE - code has to be copied out of NAND buffer before
116 * other blocks can be read.
118 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
119 CONFIG_SYS_NAND_U_BOOT_RELOC);
122 void board_init_r(gd_t *gd, ulong dest_addr)
130 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
132 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
135 void puts(const char *str)