git.sur5r.net Git - u-boot/blob - nand_spl/nand_boot.c

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <asm/io.h>
  24
  25 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  26
  27 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
  28 /*
  29  * NAND command for small page NAND devices (512)
  30  */
  31 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  32 {
  33         struct nand_chip *this = mtd->priv;
  34         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  35
  36         while (!this->dev_ready(mtd))
  37                 ;
  38
  39         /* Begin command latch cycle */
  40         this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  41         /* Set ALE and clear CLE to start address cycle */
  42         /* Column address */
  43         this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  44         this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
  45         this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
  46                        NAND_CTRL_ALE); /* A[24:17] */
  47 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
  48         /* One more address cycle for devices > 32MiB */
  49         this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
  50                        NAND_CTRL_ALE); /* A[28:25] */
  51 #endif
  52         /* Latch in address */
  53         this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  54
  55         /*
  56          * Wait a while for the data to be ready
  57          */
  58         while (!this->dev_ready(mtd))
  59                 ;
  60
  61         return 0;
  62 }
  63 #else
  64 /*
  65  * NAND command for large page NAND devices (2k)
  66  */
  67 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  68 {
  69         struct nand_chip *this = mtd->priv;
  70         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  71         void (*hwctrl)(struct mtd_info *mtd, int cmd,
  72                         unsigned int ctrl) = this->cmd_ctrl;
  73
  74         while (!this->dev_ready(mtd))
  75                 ;
  76
  77         /* Emulate NAND_CMD_READOOB */
  78         if (cmd == NAND_CMD_READOOB) {
  79                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
  80                 cmd = NAND_CMD_READ0;
  81         }
  82
  83         /* Shift the offset from byte addressing to word addressing. */
  84         if (this->options & NAND_BUSWIDTH_16)
  85                 offs >>= 1;
  86
  87         /* Begin command latch cycle */
  88         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  89         /* Set ALE and clear CLE to start address cycle */
  90         /* Column address */
  91         hwctrl(mtd, offs & 0xff,
  92                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  93         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  94         /* Row address */
  95         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
  96         hwctrl(mtd, ((page_addr >> 8) & 0xff),
  97                        NAND_CTRL_ALE); /* A[27:20] */
  98 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  99         /* One more address cycle for devices > 128MiB */
 100         hwctrl(mtd, (page_addr >> 16) & 0x0f,
 101                        NAND_CTRL_ALE); /* A[31:28] */
 102 #endif
 103         /* Latch in address */
 104         hwctrl(mtd, NAND_CMD_READSTART,
 105                        NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 106         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 107
 108         /*
 109          * Wait a while for the data to be ready
 110          */
 111         while (!this->dev_ready(mtd))
 112                 ;
 113
 114         return 0;
 115 }
 116 #endif
 117
 118 static int nand_is_bad_block(struct mtd_info *mtd, int block)
 119 {
 120         struct nand_chip *this = mtd->priv;
 121
 122         nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 123
 124         /*
 125          * Read one byte
 126          */
 127         if (readb(this->IO_ADDR_R) != 0xff)
 128                 return 1;
 129
 130         return 0;
 131 }
 132
 133 static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
 134 {
 135         struct nand_chip *this = mtd->priv;
 136         u_char *ecc_calc;
 137         u_char *ecc_code;
 138         u_char *oob_data;
 139         int i;
 140         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 141         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 142         int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 143         uint8_t *p = dst;
 144         int stat;
 145
 146         nand_command(mtd, block, page, 0, NAND_CMD_READ0);
 147
 148         /* No malloc available for now, just use some temporary locations
 149          * in SDRAM
 150          */
 151         ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
 152         ecc_code = ecc_calc + 0x100;
 153         oob_data = ecc_calc + 0x200;
 154
 155         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 156                 this->ecc.hwctl(mtd, NAND_ECC_READ);
 157                 this->read_buf(mtd, p, eccsize);
 158                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
 159         }
 160         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 161
 162         /* Pick the ECC bytes out of the oob data */
 163         for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
 164                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 165
 166         eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 167         p = dst;
 168
 169         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 170                 /* No chance to do something with the possible error message
 171                  * from correct_data(). We just hope that all possible errors
 172                  * are corrected by this routine.
 173                  */
 174                 stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int nand_load(struct mtd_info *mtd, unsigned int offs,
 181                      unsigned int uboot_size, uchar *dst)
 182 {
 183         unsigned int block, lastblock;
 184         unsigned int page;
 185
 186         /*
 187          * offs has to be aligned to a page address!
 188          */
 189         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 190         lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 191         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
 192
 193         while (block <= lastblock) {
 194                 if (!nand_is_bad_block(mtd, block)) {
 195                         /*
 196                          * Skip bad blocks
 197                          */
 198                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 199                                 nand_read_page(mtd, block, page, dst);
 200                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
 201                                 page++;
 202                         }
 203
 204                         page = 0;
 205                 } else {
 206                         lastblock++;
 207                 }
 208
 209                 block++;
 210         }
 211
 212         return 0;
 213 }
 214
 215 /*
 216  * The main entry for NAND booting. It's necessary that SDRAM is already
 217  * configured and available since this code loads the main U-Boot image
 218  * from NAND into SDRAM and starts it from there.
 219  */
 220 void nand_boot(void)
 221 {
 222         struct nand_chip nand_chip;
 223         nand_info_t nand_info;
 224         int ret;
 225         __attribute__((noreturn)) void (*uboot)(void);
 226
 227         /*
 228          * Init board specific nand support
 229          */
 230         nand_chip.select_chip = NULL;
 231         nand_info.priv = &nand_chip;
 232         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CONFIG_SYS_NAND_BASE;
 233         nand_chip.dev_ready = NULL;     /* preset to NULL */
 234         nand_chip.options = 0;
 235         board_nand_init(&nand_chip);
 236
 237         if (nand_chip.select_chip)
 238                 nand_chip.select_chip(&nand_info, 0);
 239
 240         /*
 241          * Load U-Boot image from NAND into RAM
 242          */
 243         ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
 244                         (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 245
 246 #ifdef CONFIG_NAND_ENV_DST
 247         nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 248                   (uchar *)CONFIG_NAND_ENV_DST);
 249
 250 #ifdef CONFIG_ENV_OFFSET_REDUND
 251         nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 252                   (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 253 #endif
 254 #endif
 255
 256         if (nand_chip.select_chip)
 257                 nand_chip.select_chip(&nand_info, -1);
 258
 259         /*
 260          * Jump to U-Boot image
 261          */
 262         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 263         (*uboot)();
 264 }