git.sur5r.net Git - u-boot/blob - nand_spl/nand_boot.c

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <asm/io.h>
  24
  25 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  26
  27 #define ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / \
  28                                         CONFIG_SYS_NAND_ECCSIZE)
  29 #define ECCTOTAL        (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  30
  31
  32 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
  33 /*
  34  * NAND command for small page NAND devices (512)
  35  */
  36 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  37 {
  38         struct nand_chip *this = mtd->priv;
  39         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  40
  41         while (!this->dev_ready(mtd))
  42                 ;
  43
  44         /* Begin command latch cycle */
  45         this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  46         /* Set ALE and clear CLE to start address cycle */
  47         /* Column address */
  48         this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  49         this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
  50         this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
  51                        NAND_CTRL_ALE); /* A[24:17] */
  52 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
  53         /* One more address cycle for devices > 32MiB */
  54         this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
  55                        NAND_CTRL_ALE); /* A[28:25] */
  56 #endif
  57         /* Latch in address */
  58         this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  59
  60         /*
  61          * Wait a while for the data to be ready
  62          */
  63         while (!this->dev_ready(mtd))
  64                 ;
  65
  66         return 0;
  67 }
  68 #else
  69 /*
  70  * NAND command for large page NAND devices (2k)
  71  */
  72 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  73 {
  74         struct nand_chip *this = mtd->priv;
  75         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  76         void (*hwctrl)(struct mtd_info *mtd, int cmd,
  77                         unsigned int ctrl) = this->cmd_ctrl;
  78
  79         while (!this->dev_ready(mtd))
  80                 ;
  81
  82         /* Emulate NAND_CMD_READOOB */
  83         if (cmd == NAND_CMD_READOOB) {
  84                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
  85                 cmd = NAND_CMD_READ0;
  86         }
  87
  88         /* Shift the offset from byte addressing to word addressing. */
  89         if (this->options & NAND_BUSWIDTH_16)
  90                 offs >>= 1;
  91
  92         /* Begin command latch cycle */
  93         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  94         /* Set ALE and clear CLE to start address cycle */
  95         /* Column address */
  96         hwctrl(mtd, offs & 0xff,
  97                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  98         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  99         /* Row address */
 100         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
 101         hwctrl(mtd, ((page_addr >> 8) & 0xff),
 102                        NAND_CTRL_ALE); /* A[27:20] */
 103 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 104         /* One more address cycle for devices > 128MiB */
 105         hwctrl(mtd, (page_addr >> 16) & 0x0f,
 106                        NAND_CTRL_ALE); /* A[31:28] */
 107 #endif
 108         /* Latch in address */
 109         hwctrl(mtd, NAND_CMD_READSTART,
 110                        NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 111         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 112
 113         /*
 114          * Wait a while for the data to be ready
 115          */
 116         while (!this->dev_ready(mtd))
 117                 ;
 118
 119         return 0;
 120 }
 121 #endif
 122
 123 static int nand_is_bad_block(struct mtd_info *mtd, int block)
 124 {
 125         struct nand_chip *this = mtd->priv;
 126
 127         nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 128
 129         /*
 130          * Read one byte (or two if it's a 16 bit chip).
 131          */
 132         if (this->options & NAND_BUSWIDTH_16) {
 133                 if (readw(this->IO_ADDR_R) != 0xffff)
 134                         return 1;
 135         } else {
 136                 if (readb(this->IO_ADDR_R) != 0xff)
 137                         return 1;
 138         }
 139
 140         return 0;
 141 }
 142
 143 #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
 144 static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
 145 {
 146         struct nand_chip *this = mtd->priv;
 147         u_char ecc_calc[ECCTOTAL];
 148         u_char ecc_code[ECCTOTAL];
 149         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 150         int i;
 151         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 152         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 153         int eccsteps = ECCSTEPS;
 154         uint8_t *p = dst;
 155
 156         nand_command(mtd, block, page, 0, NAND_CMD_READOOB);
 157         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 158         nand_command(mtd, block, page, 0, NAND_CMD_READ0);
 159
 160         /* Pick the ECC bytes out of the oob data */
 161         for (i = 0; i < ECCTOTAL; i++)
 162                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 163
 164
 165         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 166                 this->ecc.hwctl(mtd, NAND_ECC_READ);
 167                 this->read_buf(mtd, p, eccsize);
 168                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
 169                 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 170         }
 171
 172         return 0;
 173 }
 174 #else
 175 static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
 176 {
 177         struct nand_chip *this = mtd->priv;
 178         u_char ecc_calc[ECCTOTAL];
 179         u_char ecc_code[ECCTOTAL];
 180         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 181         int i;
 182         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 183         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 184         int eccsteps = ECCSTEPS;
 185         uint8_t *p = dst;
 186
 187         nand_command(mtd, block, page, 0, NAND_CMD_READ0);
 188
 189         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 190                 this->ecc.hwctl(mtd, NAND_ECC_READ);
 191                 this->read_buf(mtd, p, eccsize);
 192                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
 193         }
 194         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 195
 196         /* Pick the ECC bytes out of the oob data */
 197         for (i = 0; i < ECCTOTAL; i++)
 198                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 199
 200         eccsteps = ECCSTEPS;
 201         p = dst;
 202
 203         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 204                 /* No chance to do something with the possible error message
 205                  * from correct_data(). We just hope that all possible errors
 206                  * are corrected by this routine.
 207                  */
 208                 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 209         }
 210
 211         return 0;
 212 }
 213 #endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */
 214
 215 static int nand_load(struct mtd_info *mtd, unsigned int offs,
 216                      unsigned int uboot_size, uchar *dst)
 217 {
 218         unsigned int block, lastblock;
 219         unsigned int page;
 220
 221         /*
 222          * offs has to be aligned to a page address!
 223          */
 224         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 225         lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 226         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
 227
 228         while (block <= lastblock) {
 229                 if (!nand_is_bad_block(mtd, block)) {
 230                         /*
 231                          * Skip bad blocks
 232                          */
 233                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 234                                 nand_read_page(mtd, block, page, dst);
 235                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
 236                                 page++;
 237                         }
 238
 239                         page = 0;
 240                 } else {
 241                         lastblock++;
 242                 }
 243
 244                 block++;
 245         }
 246
 247         return 0;
 248 }
 249
 250 /*
 251  * The main entry for NAND booting. It's necessary that SDRAM is already
 252  * configured and available since this code loads the main U-Boot image
 253  * from NAND into SDRAM and starts it from there.
 254  */
 255 void nand_boot(void)
 256 {
 257         struct nand_chip nand_chip;
 258         nand_info_t nand_info;
 259         __attribute__((noreturn)) void (*uboot)(void);
 260
 261         /*
 262          * Init board specific nand support
 263          */
 264         nand_chip.select_chip = NULL;
 265         nand_info.priv = &nand_chip;
 266         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CONFIG_SYS_NAND_BASE;
 267         nand_chip.dev_ready = NULL;     /* preset to NULL */
 268         nand_chip.options = 0;
 269         board_nand_init(&nand_chip);
 270
 271         if (nand_chip.select_chip)
 272                 nand_chip.select_chip(&nand_info, 0);
 273
 274         /*
 275          * Load U-Boot image from NAND into RAM
 276          */
 277         nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
 278                   (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 279
 280 #ifdef CONFIG_NAND_ENV_DST
 281         nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 282                   (uchar *)CONFIG_NAND_ENV_DST);
 283
 284 #ifdef CONFIG_ENV_OFFSET_REDUND
 285         nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 286                   (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 287 #endif
 288 #endif
 289
 290         if (nand_chip.select_chip)
 291                 nand_chip.select_chip(&nand_info, -1);
 292
 293         /*
 294          * Jump to U-Boot image
 295          */
 296         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 297         (*uboot)();
 298 }