2 * Board specific setup info
4 * (C) Copyright 2005-2008 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
7 * Derived from board/omap2420h4/platform.S
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/omap2420.h>
30 #include <asm/arch/mem.h>
31 #include <asm/arch/clocks.h>
33 #define APOLLON_CS0_BASE 0x00000000
36 #define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
37 #define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
38 #define SDRC_RFR_CTRL_0_VAL 0x00044C01
41 #define APOLLON_GPMC_CONFIG1_0 0xe30d1201
42 #define APOLLON_GPMC_CONFIG2_0 0x000c1000
43 #define APOLLON_GPMC_CONFIG3_0 0x00030400
44 #define APOLLON_GPMC_CONFIG4_0 0x0B841006
45 #define APOLLON_GPMC_CONFIG5_0 0x020F0C11
46 #define APOLLON_GPMC_CONFIG6_0 0x00000000
47 #define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
49 #elif defined(PRCM_CONFIG_II)
50 #define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
51 #define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
52 #define SDRC_RFR_CTRL_0_VAL 0x00030001
55 #define APOLLON_GPMC_CONFIG1_0 0xe30d1201
56 #define APOLLON_GPMC_CONFIG2_0 0x00080E81
57 #define APOLLON_GPMC_CONFIG3_0 0x00030400
58 #define APOLLON_GPMC_CONFIG4_0 0x08041586
59 #define APOLLON_GPMC_CONFIG5_0 0x020C090E
60 #define APOLLON_GPMC_CONFIG6_0 0x00000000
61 #define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
64 #error "Please configure PRCM schecm"
68 .word TEXT_BASE /* sdram load addr from config.mk */
72 mov r3, r0 /* save skip information */
74 /* Disable watchdog */
84 ldr r0, =0x480000E5 /* ball AA10, mode 3 */
89 /* Pin muxing for SDRC */
91 ldr r0, =0x480000A1 /* ball C12, mode 0 */
94 ldr r0, =0x48000032 /* ball D11, mode 0 */
97 ldr r0, =0x480000A3 /* ball B13, mode 0 */
101 ldr r0, =OMAP2420_SDRC_BASE
108 /* SDRC CS0 configuration */
109 #ifdef CONFIG_APOLLON_PLUS
116 ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
119 ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
122 ldr r1, =SDRC_RFR_CTRL_0_VAL
128 /* Manual command sequence */
143 * CS0 SDRC Mode register
144 * Burst length = 4 - DDR memory
151 /* Note: You MUST set EMR values */
157 #ifdef OLD_SDRC_DLLA_CTRL
173 #ifdef __BROKEN_FEATURE__
182 /* little delay after init */
189 str ip, [sp] /* stash old link register */
190 mov ip, lr /* save link reg across call */
191 mov r0, r3 /* pass skip info to s_init */
193 bl s_init /* go setup pll,mux,memory */
195 ldr ip, [sp] /* restore save ip */
196 mov lr, ip /* restore link reg */
198 /* back to arch calling code */
201 /* the literal pools origin */
205 .word LOW_LEVEL_SRAM_STACK