3 The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
4 P1010RDB-PB is a variation of previous P1010RDB-PA board.
6 The P1010 is a cost-effective, low-power, highly integrated host processor
7 based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
8 addresses the requirements of several routing, gateways, storage, consumer,
9 and industrial applications. Applications of interest include the main CPUs and
10 I/O processors in network attached storage (NAS), the voice over IP (VoIP)
11 router/gateway, and wireless LAN (WLAN) and industrial controllers.
13 The P1010RDB-PB board features are as following:
15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
16 - 32M bytes NOR flash single-chip memory
17 - 2G bytes NAND flash memory
18 - 16M bytes SPI memory
19 - 256K bit M24256 I2C EEPROM
20 - I2C Board EEPROM 128x8 bit memory
21 - SD/MMC connector to interface with the SD memory card
23 - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
24 - PCIe 2.0: two x1 mini-PCIe slots
25 - SATA 2.0: two SATA interfaces
26 - USB 2.0: one USB interface
27 - FlexCAN: two FlexCAN interfaces (revision 2.0B)
28 - UART: one USB-to-Serial interface
29 - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
30 1 FXO port connected via a relay to FXS for switchover to POTS
33 - Mini-ITX power supply connector
34 - JTAG/COP for debugging
36 POR: support critical POR setting changed via switch on board
37 PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
39 Physical Memory Map on P1010RDB
40 ===============================
41 Address Start Address End Memory type Attributes
42 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
43 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
44 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
45 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
46 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
47 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
48 0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
49 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
52 Serial Port Configuration on P1010RDB
53 =====================================
54 Configure the serial port of the attached computer with the following values:
55 -Data rate: 115200 bps
56 -Number of data bits: 8
58 -Number of Stop bits: 1
59 -Flow Control: Hardware/None
62 P1010RDB-PB default DIP-switch settings
63 =======================================
71 P1010RDB-PB boot mode settings via DIP-switch
72 =============================================
73 SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
74 SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
75 SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
76 SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
77 Note: 1 stands for 'on', 0 stands for 'off'
80 Switch P1010RDB-PB boot mode via software without setting DIP-switch
81 ====================================================================
82 => run boot_bank0 (boot from NOR bank0)
83 => run boot_bank1 (boot from NOR bank1)
84 => run boot_nand (boot from NAND flash)
85 => run boot_spi (boot from SPI flash)
86 => run boot_sd (boot from SD card)
89 Frequency combination support on P1010RDB-PB
90 =============================================
91 SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
92 0101 1 1010 0 800 400 800
93 1001 1 1010 0 800 400 667
94 1010 1 1100 0 667 333 667
95 1000 0 1010 0 533 266 667
96 0101 1 1010 1 1000 400 800
97 1001 1 1010 1 1000 400 667
102 Since pins multiplexing, TDM and CAN are muxed with SPI flash.
103 SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
106 => setenv hwconfig fsl_p1010mux:tdm_can=tdm
110 => setenv hwconfig fsl_p1010mux:tdm_can=can
113 To enable SDHC in case of NOR/NAND/SPI boot
114 a) For temporary use case in runtime without reboot system
115 run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
117 b) For long-term use case
118 set 'esdhc' in hwconfig and save it.
120 To enable IFC in case of SD boot
121 a) For temporary use case in runtime without reboot system
122 run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
124 b) For long-term use case
125 set 'ifc' in hwconfig and save it.
128 Build images for different boot mode
129 ====================================
130 First setup cross compile environment on build host
131 $ export ARCH=powerpc
132 $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
135 $ make P1010RDB-PB_NOR
138 $ make P1010RDB-PB_NAND
141 $ make P1010RDB-PB_SPIFLASH
144 $ make P1010RDB-PB_SDCARD
147 Steps to program images to flash for different boot mode
148 ========================================================
150 => tftp 1000000 u-boot.bin
152 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
153 set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
156 => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize
157 set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
160 => tftp 1000000 u-boot-nand.bin
161 => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
162 Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
165 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
166 2) => tftp 1000000 u-boot-spi-combined.bin
167 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
168 set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
171 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
172 2) => tftp 1000000 u-boot-sd-combined.bin
174 4) => mmc write 1000000 0 1050
175 set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
178 Boot Linux from network using TFTP on P1010RDB-PB
179 =================================================
180 Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
181 => tftp 1000000 uImage
182 => tftp 2000000 p1010rdb.dtb
183 => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
184 => bootm 1000000 3000000 2000000
187 For more details, please refer to P1010RDB-PB User Guide and access website
188 www.freescale.com and Freescale QorIQ SDK Infocenter document.