2 * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
4 * Developed for DENX Software Engineering GmbH
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* This test performs testing of FPGA SCRATCH register,
27 * gets FPGA version and run get_ram_size() on FPGA memory
34 DECLARE_GLOBAL_DATA_PTR;
36 #define FPGA_SCRATCH_REG 0xC4000050
37 #define FPGA_VERSION_REG 0xC4000040
38 #define FPGA_RAM_START 0xC4200000
39 #define FPGA_RAM_END 0xC4203FFF
40 #define FPGA_STAT 0xC400000C
41 #define FPGA_BUFFER 0x00800000
42 #define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1)
44 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
46 const static unsigned long pattern[] = {
61 const static unsigned long otherpattern = 0x01234567;
63 static int one_scratch_test(uint value)
68 out_be32((void *)FPGA_SCRATCH_REG, value);
69 /* read other location (protect against data lines capacity) */
70 ret = in_be16((void *)FPGA_VERSION_REG);
71 /* verify test pattern */
72 read_value = in_be32((void *)FPGA_SCRATCH_REG);
73 if (read_value != value) {
74 post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
82 static int fpga_post_test1(ulong *start, ulong size, ulong val)
89 for (i = 0; i < size / sizeof(ulong); i++) {
95 for (i = 0; i < size / sizeof(ulong); i++) {
97 if (readback != val) {
98 post_log("FPGA Memory error at %08x, "
99 "wrote %08x, read %08x !\n",
100 mem + i, val, readback);
110 static int fpga_post_test2(ulong *start, ulong size)
117 for (i = 0; i < size / sizeof(ulong); i++) {
118 mem[i] = 1 << (i % 32);
123 for (i = 0; i < size / sizeof(ulong); i++) {
125 if (readback != 1 << (i % 32)) {
126 post_log("FPGA Memory error at %08x, "
127 "wrote %08x, read %08x !\n",
128 mem + i, 1 << (i % 32), readback);
139 static int fpga_post_test3(ulong *start, ulong size)
146 for (i = 0; i < size / sizeof(ulong); i++) {
152 for (i = 0; i < size / sizeof(ulong); i++) {
155 post_log("FPGA Memory error at %08x, "
156 "wrote %08x, read %08x !\n",
157 mem + i, i, readback);
168 static int fpga_post_test4(ulong *start, ulong size)
175 for (i = 0; i < size / sizeof(ulong); i++) {
181 for (i = 0; i < size / sizeof(ulong); i++) {
183 if (readback != ~i) {
184 post_log("FPGA Memory error at %08x, "
185 "wrote %08x, read %08x !\n",
186 mem + i, ~i, readback);
197 /* FPGA Memory-pattern-test */
198 static int fpga_mem_test(void)
201 ulong* start = (ulong *)FPGA_RAM_START;
202 ulong size = FPGA_RAM_SIZE;
205 ret = fpga_post_test1(start, size, 0x00000000);
208 ret = fpga_post_test1(start, size, 0xffffffff);
211 ret = fpga_post_test1(start, size, 0x55555555);
214 ret = fpga_post_test1(start, size, 0xaaaaaaaa);
219 ret = fpga_post_test2(start, size);
222 ret = fpga_post_test3(start, size);
225 ret = fpga_post_test4(start, size);
232 /* Verify FPGA addresslines */
233 static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
235 unsigned long *target;
237 unsigned long readback;
241 end = (ulong *)((ulong)base + size);
244 for (xor = sizeof(ulong); xor > 0; xor <<= 1) {
245 target = (ulong*)((ulong)address ^ xor);
246 if ((target >= base) && (target < end)) {
250 if (readback == *address) {
251 post_log("Memory (address line) error at %08x"
252 "XOR value %08x !\n",
253 address, target, xor);
263 /* Verify FPGA addresslines */
264 static int fpga_post_dataline(ulong *address)
266 unsigned long temp32 = 0;
270 for (i = 0; i < ARRAY_SIZE(pattern); i++) {
271 *address = pattern[i];
273 * Put a different pattern on the data lines: otherwise they
274 * may float long enough to read back what we wrote.
276 *(address + 1) = otherpattern;
279 if (temp32 != pattern[i]){
280 post_log("Memory (date line) error at %08x, "
281 "wrote %08x, read %08x !\n",
282 address, pattern[i], temp32);
290 /* Verify FPGA, get version & memory size */
291 int fpga_post_test(int flags)
299 old_value = in_be32((void *)FPGA_SCRATCH_REG);
301 if (one_scratch_test(0x55555555))
303 if (one_scratch_test(0xAAAAAAAA))
306 out_be32((void *)FPGA_SCRATCH_REG, old_value);
308 version = in_be32((void *)FPGA_VERSION_REG);
309 post_log("FPGA version %u.%u\n",
310 (version >> 8) & 0xFF, version & 0xFF);
312 /* Enable write to FPGA RAM */
313 out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
316 read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, FPGA_RAM_SIZE);
317 post_log("FPGA RAM size %d bytes\n", read_value);
320 /* copy fpga memory to DDR2 RAM*/
321 memcpy((void *)FPGA_BUFFER,(void *)FPGA_RAM_START, FPGA_RAM_SIZE);
325 if (fpga_post_dataline((ulong *)FPGA_RAM_START)) {
331 /* Test addresslines */
332 if (fpga_post_addrline((ulong *)FPGA_RAM_START,
333 (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
338 if (fpga_post_addrline((ulong *)FPGA_RAM_END - sizeof(long),
339 (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
345 /* Memory Pattern Test */
346 if (fpga_mem_test()) {
353 memcpy((void *)FPGA_RAM_START,(void *)FPGA_BUFFER, FPGA_RAM_SIZE);
357 /* Disable write to RAM */
358 out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF);
362 #endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC3 */