3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 * The Serial Communication Controllers (SCC) listed in ctlr_list array below
14 * are tested in the loopback ethernet mode.
15 * The controllers are configured accordingly and several packets
16 * are transmitted. The configurable test parameters are:
17 * MIN_PACKET_LENGTH - minimum size of packet to transmit
18 * MAX_PACKET_LENGTH - maximum size of packet to transmit
19 * TEST_NUM - number of tests
23 #if CONFIG_POST & CONFIG_SYS_POST_ETHER
24 #if defined(CONFIG_8xx)
26 #elif defined(CONFIG_MPC8260)
27 #include <asm/cpm_8260.h>
29 #error "Apparently a bad configuration, please fix."
36 DECLARE_GLOBAL_DATA_PTR;
38 #define MIN_PACKET_LENGTH 64
39 #define MAX_PACKET_LENGTH 256
44 extern void spi_init_f (void);
45 extern void spi_init_r (void);
47 /* The list of controllers to test */
48 #if defined(CONFIG_MPC823)
49 static int ctlr_list[][2] = { {CTLR_SCC, 1} };
51 static int ctlr_list[][2] = { };
55 void (*init) (int index);
56 void (*halt) (int index);
57 int (*send) (int index, volatile void *packet, int length);
58 int (*recv) (int index, void *packet, int length);
61 static char *ctlr_name[1] = { "SCC" };
63 /* Ethernet Transmit and Receive Buffers */
64 #define DBUF_LENGTH 1520
70 static char txbuf[DBUF_LENGTH];
72 static uint rxIdx; /* index of the current RX buffer */
73 static uint txIdx; /* index of the current TX buffer */
76 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
77 * immr->udata_bd address on Dual-Port RAM
78 * Provide for Double Buffering
81 typedef volatile struct CommonBufferDescriptor {
82 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
83 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
92 static void scc_init (int scc_index)
96 static int proff[] = {
102 static unsigned int cpm_cr[] = {
110 scc_enet_t *pram_ptr;
112 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
114 immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
115 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
117 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
122 #ifdef CONFIG_SYS_ALLOC_DPRAM
123 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
124 dpram_alloc_align (sizeof (RTXBD), 8));
126 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
131 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
132 /* Configure port A pins for Txd and Rxd.
134 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
135 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
136 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
137 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
138 /* Configure port B pins for Txd and Rxd.
140 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
141 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
142 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
144 #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
147 #if defined(PC_ENET_LBK)
148 /* Configure port C pins to disable External Loopback
150 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
151 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
152 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
153 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
154 #endif /* PC_ENET_LBK */
156 /* Configure port C pins to enable CLSN and RENA.
158 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
159 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
160 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
162 /* Configure port A for TCLK and RCLK.
164 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
165 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
168 * Configure Serial Interface clock routing -- see section 16.7.5.3
169 * First, clear all SCC bits to zero, then set the ones we want.
172 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
173 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
176 * SCC2 receive clock is BRG2
177 * SCC2 transmit clock is BRG3
179 immr->im_cpm.cp_brgc2 = 0x0001000C;
180 immr->im_cpm.cp_brgc3 = 0x0001000C;
182 immr->im_cpm.cp_sicr &= ~0x00003F00;
183 immr->im_cpm.cp_sicr |= 0x00000a00;
188 * Initialize SDCR -- see section 16.9.23.7
189 * SDMA configuration register
191 immr->im_siu_conf.sc_sdcr = 0x01;
195 * Setup SCC Ethernet Parameter RAM
198 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
199 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
201 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
203 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
204 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
207 * Setup Receiver Buffer Descriptors (13.14.24.18)
212 for (i = 0; i < PKTBUFSRX; i++) {
213 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
214 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
215 rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
218 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
221 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
223 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
226 for (i = 0; i < TX_BUF_CNT; i++) {
227 rtx->txbd[i].cbd_sc =
228 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
229 rtx->txbd[i].cbd_datlen = 0; /* Reset */
230 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
233 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
236 * Enter Command: Initialize Rx Params for SCC
239 do { /* Spin until ready to issue command */
241 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
243 immr->im_cpm.cp_cpcr =
244 ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
246 do { /* Spin until command processed */
248 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
251 * Ethernet Specific Parameter RAM
252 * see table 13-16, pg. 660,
253 * pg. 681 (example with suggested settings)
256 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
257 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
258 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
259 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
260 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
261 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
263 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
264 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
265 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
267 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
268 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
270 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
271 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
272 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
273 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
275 eth_getenv_enetaddr("ethaddr", ea);
276 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
277 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
278 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
280 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
281 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
282 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
283 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
284 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
285 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
286 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
287 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
290 * Enter Command: Initialize Tx Params for SCC
293 do { /* Spin until ready to issue command */
295 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
297 immr->im_cpm.cp_cpcr =
298 ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
300 do { /* Spin until command processed */
302 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
305 * Mask all Events in SCCM - we use polling mode
307 immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
310 * Clear Events in SCCE -- Clear bits by writing 1's
313 immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
317 * Initialize GSMR High 32-Bits
318 * Settings: Normal Mode
321 immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
324 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
328 * TPP = Repeating 10's
333 immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
336 SCC_GSMRL_DIAG_LOOP |
337 SCC_GSMRL_MODE_ENET);
340 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
343 immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
346 * Initialize the PSMR
349 * NIB = Begin searching for SFD 22 bits after RENA
350 * LPB = Loopback Enable (Needed when FDE is set)
352 immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
353 SCC_PSMR_NIB22 | SCC_PSMR_LPB;
356 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
359 immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
360 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
363 static void scc_halt (int scc_index)
365 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
367 immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
368 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
369 immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
372 static int scc_send (int index, volatile void *packet, int length)
376 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
377 udelay (1); /* will also trigger Wd if needed */
381 printf ("TX not ready\n");
382 rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
383 rtx->txbd[txIdx].cbd_datlen = length;
384 rtx->txbd[txIdx].cbd_sc |=
385 (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
386 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
387 udelay (1); /* will also trigger Wd if needed */
391 printf ("TX timeout\n");
392 i = (rtx->txbd[txIdx].
393 cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
397 static int scc_recv (int index, void *packet, int max_length)
401 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
402 goto Done; /* nothing received */
405 if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
406 length = rtx->rxbd[rxIdx].cbd_datlen - 4;
408 (void *)(net_rx_packets[rxIdx]),
409 length < max_length ? length : max_length);
412 /* Give the buffer back to the SCC. */
413 rtx->rxbd[rxIdx].cbd_datlen = 0;
415 /* wrap around buffer index when necessary */
416 if ((rxIdx + 1) >= PKTBUFSRX) {
417 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
418 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
421 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
433 static void packet_fill (char *packet, int length)
435 char c = (char) length;
445 for (i = 6; i < length; i++) {
450 static int packet_check (char *packet, int length)
452 char c = (char) length;
455 for (i = 6; i < length; i++) {
456 if (packet[i] != c++)
463 static int test_ctlr (int ctlr, int index)
466 char packet_send[MAX_PACKET_LENGTH];
467 char packet_recv[MAX_PACKET_LENGTH];
472 ctlr_proc[ctlr].init (index);
474 for (i = 0; i < TEST_NUM; i++) {
475 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
476 packet_fill (packet_send, l);
478 ctlr_proc[ctlr].send (index, packet_send, l);
480 length = ctlr_proc[ctlr].recv (index, packet_recv,
483 if (length != l || packet_check (packet_recv, length) < 0) {
493 ctlr_proc[ctlr].halt (index);
496 * SCC2 Ethernet parameter RAM space overlaps
497 * the SPI parameter RAM space. So we need to restore
498 * the SPI configuration after SCC2 ethernet test.
500 #if defined(CONFIG_SPI)
501 if (ctlr == CTLR_SCC && index == 1) {
508 post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
515 int ether_post_test (int flags)
520 ctlr_proc[CTLR_SCC].init = scc_init;
521 ctlr_proc[CTLR_SCC].halt = scc_halt;
522 ctlr_proc[CTLR_SCC].send = scc_send;
523 ctlr_proc[CTLR_SCC].recv = scc_recv;
525 for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
526 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
531 #if !defined(CONFIG_8xx_CONS_NONE)
532 serial_reinit_all ();
537 #endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */