3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 * The Serial Management Controllers (SMC) and the Serial Communication
14 * Controllers (SCC) listed in ctlr_list array below are tested in
15 * the loopback UART mode.
16 * The controllers are configured accordingly and several characters
17 * are transmitted. The configurable test parameters are:
18 * MIN_PACKET_LENGTH - minimum size of packet to transmit
19 * MAX_PACKET_LENGTH - maximum size of packet to transmit
20 * TEST_NUM - number of tests
24 #if CONFIG_POST & CONFIG_SYS_POST_UART
25 #if defined(CONFIG_8xx)
27 #elif defined(CONFIG_MPC8260)
28 #include <asm/cpm_8260.h>
30 #error "Apparently a bad configuration, please fix."
35 DECLARE_GLOBAL_DATA_PTR;
40 /* The list of controllers to test */
41 #if defined(CONFIG_MPC823)
42 static int ctlr_list[][2] =
43 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
45 static int ctlr_list[][2] = { };
49 void (*init) (int index);
50 void (*halt) (int index);
51 void (*putc) (int index, const char c);
52 int (*getc) (int index);
55 static char *ctlr_name[2] = { "SMC", "SCC" };
57 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
58 static int proff_scc[] =
59 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
65 static void smc_init (int smc_index)
67 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
69 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
71 volatile smc_uart_t *up;
72 volatile cbd_t *tbdf, *rbdf;
73 volatile cpm8xx_t *cp = &(im->im_cpm);
76 /* initialize pointers to SMC */
78 sp = (smc_t *) & (cp->cp_smc[smc_index]);
79 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
81 /* Disable transmitter/receiver.
83 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
87 im->im_siu_conf.sc_sdcr = 1;
89 /* clear error conditions */
90 #ifdef CONFIG_SYS_SDSR
91 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
93 im->im_sdma.sdma_sdsr = 0x83;
96 /* clear SDMA interrupt mask */
97 #ifdef CONFIG_SYS_SDMR
98 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
100 im->im_sdma.sdma_sdmr = 0x00;
103 /* Set the physical address of the host memory buffers in
104 * the buffer descriptors.
107 #ifdef CONFIG_SYS_ALLOC_DPRAM
108 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
110 dpaddr = CPM_POST_BASE;
113 /* Allocate space for two buffer descriptors in the DP ram.
114 * For now, this address seems OK, but it may have to
115 * change with newer versions of the firmware.
116 * damm: allocating space after the two buffers for rx/tx data
119 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
120 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
123 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
126 /* Set up the uart parameters in the parameter ram.
128 up->smc_rbase = dpaddr;
129 up->smc_tbase = dpaddr + sizeof (cbd_t);
130 up->smc_rfcr = SMC_EB;
131 up->smc_tfcr = SMC_EB;
133 /* Set UART mode, 8 bit, no parity, one stop.
134 * Enable receive and transmit.
135 * Set local loopback mode.
137 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
139 /* Mask all interrupts and remove anything pending.
144 /* Set up the baud rate generator.
146 cp->cp_simode = 0x00000000;
149 (((gd->cpu_clk / 16 / gd->baudrate) -
150 1) << 1) | CPM_BRG_EN;
152 /* Make the first buffer the only buffer.
154 tbdf->cbd_sc |= BD_SC_WRAP;
155 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
157 /* Single character receive.
162 /* Initialize Tx/Rx parameters.
165 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
169 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
171 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
174 /* Enable transmitter/receiver.
176 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
179 static void smc_halt(int smc_index)
183 static void smc_putc (int smc_index, const char c)
185 volatile cbd_t *tbdf;
187 volatile smc_uart_t *up;
188 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
189 volatile cpm8xx_t *cpmp = &(im->im_cpm);
191 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
193 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
195 /* Wait for last character to go.
198 buf = (char *) tbdf->cbd_bufaddr;
201 while (tbdf->cbd_sc & BD_SC_READY)
206 tbdf->cbd_datlen = 1;
207 tbdf->cbd_sc |= BD_SC_READY;
210 while (tbdf->cbd_sc & BD_SC_READY)
215 static int smc_getc (int smc_index)
217 volatile cbd_t *rbdf;
218 volatile unsigned char *buf;
219 volatile smc_uart_t *up;
220 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
221 volatile cpm8xx_t *cpmp = &(im->im_cpm);
225 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
227 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
229 /* Wait for character to show up.
231 buf = (unsigned char *) rbdf->cbd_bufaddr;
233 while (rbdf->cbd_sc & BD_SC_EMPTY);
235 for (i = 100; i > 0; i--) {
236 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
245 rbdf->cbd_sc |= BD_SC_EMPTY;
254 static void scc_init (int scc_index)
256 static int cpm_cr_ch[] = {
263 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
265 volatile scc_uart_t *up;
266 volatile cbd_t *tbdf, *rbdf;
267 volatile cpm8xx_t *cp = &(im->im_cpm);
270 /* initialize pointers to SCC */
272 sp = (scc_t *) & (cp->cp_scc[scc_index]);
273 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
275 /* Disable transmitter/receiver.
277 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
280 /* Allocate space for two buffer descriptors in the DP ram.
283 #ifdef CONFIG_SYS_ALLOC_DPRAM
284 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
286 dpaddr = CPM_POST_BASE;
291 im->im_siu_conf.sc_sdcr = 0x0001;
293 /* Set the physical address of the host memory buffers in
294 * the buffer descriptors.
297 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
298 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
301 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
304 /* Set up the baud rate generator.
306 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
307 /* no |= needed, since BRG1 is 000 */
310 (((gd->cpu_clk / 16 / gd->baudrate) -
311 1) << 1) | CPM_BRG_EN;
313 /* Set up the uart parameters in the parameter ram.
315 up->scc_genscc.scc_rbase = dpaddr;
316 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
318 /* Initialize Tx/Rx parameters.
320 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
323 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
325 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
328 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
329 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
331 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
332 up->scc_maxidl = 0; /* disable max idle */
333 up->scc_brkcr = 1; /* send one break character on stop TX */
341 up->scc_char1 = 0x8000;
342 up->scc_char2 = 0x8000;
343 up->scc_char3 = 0x8000;
344 up->scc_char4 = 0x8000;
345 up->scc_char5 = 0x8000;
346 up->scc_char6 = 0x8000;
347 up->scc_char7 = 0x8000;
348 up->scc_char8 = 0x8000;
349 up->scc_rccm = 0xc0ff;
351 /* Set low latency / small fifo.
353 sp->scc_gsmrh = SCC_GSMRH_RFW;
357 sp->scc_gsmrl &= ~0xF;
358 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
360 /* Set local loopback mode.
362 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
363 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
365 /* Set clock divider 16 on Tx and Rx
367 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
369 sp->scc_psmr |= SCU_PSMR_CL;
371 /* Mask all interrupts and remove anything pending.
374 sp->scc_scce = 0xffff;
375 sp->scc_dsr = 0x7e7e;
376 sp->scc_psmr = 0x3000;
378 /* Make the first buffer the only buffer.
380 tbdf->cbd_sc |= BD_SC_WRAP;
381 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
383 /* Enable transmitter/receiver.
385 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
388 static void scc_halt(int scc_index)
390 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
391 volatile cpm8xx_t *cp = &(im->im_cpm);
392 volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
394 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
397 static void scc_putc (int scc_index, const char c)
399 volatile cbd_t *tbdf;
401 volatile scc_uart_t *up;
402 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
403 volatile cpm8xx_t *cpmp = &(im->im_cpm);
405 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
407 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
409 /* Wait for last character to go.
412 buf = (char *) tbdf->cbd_bufaddr;
415 while (tbdf->cbd_sc & BD_SC_READY)
420 tbdf->cbd_datlen = 1;
421 tbdf->cbd_sc |= BD_SC_READY;
424 while (tbdf->cbd_sc & BD_SC_READY)
429 static int scc_getc (int scc_index)
431 volatile cbd_t *rbdf;
432 volatile unsigned char *buf;
433 volatile scc_uart_t *up;
434 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
435 volatile cpm8xx_t *cpmp = &(im->im_cpm);
439 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
441 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
443 /* Wait for character to show up.
445 buf = (unsigned char *) rbdf->cbd_bufaddr;
447 while (rbdf->cbd_sc & BD_SC_EMPTY);
449 for (i = 100; i > 0; i--) {
450 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
459 rbdf->cbd_sc |= BD_SC_EMPTY;
468 static int test_ctlr (int ctlr, int index)
471 char test_str[] = "*** UART Test String ***\r\n";
474 ctlr_proc[ctlr].init (index);
476 for (i = 0; i < sizeof (test_str) - 1; i++) {
477 ctlr_proc[ctlr].putc (index, test_str[i]);
478 if (ctlr_proc[ctlr].getc (index) != test_str[i])
485 ctlr_proc[ctlr].halt (index);
488 post_log ("uart %s%d test failed\n",
489 ctlr_name[ctlr], index + 1);
495 int uart_post_test (int flags)
500 ctlr_proc[CTLR_SMC].init = smc_init;
501 ctlr_proc[CTLR_SMC].halt = smc_halt;
502 ctlr_proc[CTLR_SMC].putc = smc_putc;
503 ctlr_proc[CTLR_SMC].getc = smc_getc;
505 ctlr_proc[CTLR_SCC].init = scc_init;
506 ctlr_proc[CTLR_SCC].halt = scc_halt;
507 ctlr_proc[CTLR_SCC].putc = scc_putc;
508 ctlr_proc[CTLR_SCC].getc = scc_getc;
510 for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
511 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
516 #if !defined(CONFIG_8xx_CONS_NONE)
517 serial_reinit_all ();
523 #endif /* CONFIG_POST & CONFIG_SYS_POST_UART */