3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 * The Serial Management Controllers (SMC) and the Serial Communication
14 * Controllers (SCC) listed in ctlr_list array below are tested in
15 * the loopback UART mode.
16 * The controllers are configured accordingly and several characters
17 * are transmitted. The configurable test parameters are:
18 * MIN_PACKET_LENGTH - minimum size of packet to transmit
19 * MAX_PACKET_LENGTH - maximum size of packet to transmit
20 * TEST_NUM - number of tests
24 #if CONFIG_POST & CONFIG_SYS_POST_UART
25 #if defined(CONFIG_8xx)
27 #elif defined(CONFIG_MPC8260)
28 #include <asm/cpm_8260.h>
30 #error "Apparently a bad configuration, please fix."
35 DECLARE_GLOBAL_DATA_PTR;
40 /* The list of controllers to test */
41 #if defined(CONFIG_MPC823)
42 static int ctlr_list[][2] =
43 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
45 static int ctlr_list[][2] = { };
49 void (*init) (int index);
50 void (*halt) (int index);
51 void (*putc) (int index, const char c);
52 int (*getc) (int index);
55 static char *ctlr_name[2] = { "SMC", "SCC" };
57 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
58 static int proff_scc[] =
59 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
65 static void smc_init (int smc_index)
67 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
69 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
71 volatile smc_uart_t *up;
72 volatile cbd_t *tbdf, *rbdf;
73 volatile cpm8xx_t *cp = &(im->im_cpm);
76 /* initialize pointers to SMC */
78 sp = (smc_t *) & (cp->cp_smc[smc_index]);
79 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
81 /* Disable transmitter/receiver.
83 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
87 im->im_siu_conf.sc_sdcr = 1;
89 /* clear error conditions */
90 #ifdef CONFIG_SYS_SDSR
91 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
93 im->im_sdma.sdma_sdsr = 0x83;
96 /* clear SDMA interrupt mask */
97 #ifdef CONFIG_SYS_SDMR
98 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
100 im->im_sdma.sdma_sdmr = 0x00;
103 #if defined(CONFIG_FADS)
106 ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
109 /* Set the physical address of the host memory buffers in
110 * the buffer descriptors.
113 #ifdef CONFIG_SYS_ALLOC_DPRAM
114 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
116 dpaddr = CPM_POST_BASE;
119 /* Allocate space for two buffer descriptors in the DP ram.
120 * For now, this address seems OK, but it may have to
121 * change with newer versions of the firmware.
122 * damm: allocating space after the two buffers for rx/tx data
125 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
126 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
129 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
132 /* Set up the uart parameters in the parameter ram.
134 up->smc_rbase = dpaddr;
135 up->smc_tbase = dpaddr + sizeof (cbd_t);
136 up->smc_rfcr = SMC_EB;
137 up->smc_tfcr = SMC_EB;
139 /* Set UART mode, 8 bit, no parity, one stop.
140 * Enable receive and transmit.
141 * Set local loopback mode.
143 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
145 /* Mask all interrupts and remove anything pending.
150 /* Set up the baud rate generator.
152 cp->cp_simode = 0x00000000;
155 (((gd->cpu_clk / 16 / gd->baudrate) -
156 1) << 1) | CPM_BRG_EN;
158 /* Make the first buffer the only buffer.
160 tbdf->cbd_sc |= BD_SC_WRAP;
161 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
163 /* Single character receive.
168 /* Initialize Tx/Rx parameters.
171 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
175 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
177 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
180 /* Enable transmitter/receiver.
182 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
185 static void smc_halt(int smc_index)
189 static void smc_putc (int smc_index, const char c)
191 volatile cbd_t *tbdf;
193 volatile smc_uart_t *up;
194 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
195 volatile cpm8xx_t *cpmp = &(im->im_cpm);
197 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
199 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
201 /* Wait for last character to go.
204 buf = (char *) tbdf->cbd_bufaddr;
207 while (tbdf->cbd_sc & BD_SC_READY)
212 tbdf->cbd_datlen = 1;
213 tbdf->cbd_sc |= BD_SC_READY;
216 while (tbdf->cbd_sc & BD_SC_READY)
221 static int smc_getc (int smc_index)
223 volatile cbd_t *rbdf;
224 volatile unsigned char *buf;
225 volatile smc_uart_t *up;
226 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
227 volatile cpm8xx_t *cpmp = &(im->im_cpm);
231 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
233 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
235 /* Wait for character to show up.
237 buf = (unsigned char *) rbdf->cbd_bufaddr;
239 while (rbdf->cbd_sc & BD_SC_EMPTY);
241 for (i = 100; i > 0; i--) {
242 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
251 rbdf->cbd_sc |= BD_SC_EMPTY;
260 static void scc_init (int scc_index)
262 static int cpm_cr_ch[] = {
269 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
271 volatile scc_uart_t *up;
272 volatile cbd_t *tbdf, *rbdf;
273 volatile cpm8xx_t *cp = &(im->im_cpm);
276 /* initialize pointers to SCC */
278 sp = (scc_t *) & (cp->cp_scc[scc_index]);
279 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
281 /* Disable transmitter/receiver.
283 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
286 /* Allocate space for two buffer descriptors in the DP ram.
289 #ifdef CONFIG_SYS_ALLOC_DPRAM
290 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
292 dpaddr = CPM_POST_BASE;
297 im->im_siu_conf.sc_sdcr = 0x0001;
299 /* Set the physical address of the host memory buffers in
300 * the buffer descriptors.
303 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
304 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
307 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
310 /* Set up the baud rate generator.
312 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
313 /* no |= needed, since BRG1 is 000 */
316 (((gd->cpu_clk / 16 / gd->baudrate) -
317 1) << 1) | CPM_BRG_EN;
319 /* Set up the uart parameters in the parameter ram.
321 up->scc_genscc.scc_rbase = dpaddr;
322 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
324 /* Initialize Tx/Rx parameters.
326 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
329 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
331 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
334 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
335 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
337 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
338 up->scc_maxidl = 0; /* disable max idle */
339 up->scc_brkcr = 1; /* send one break character on stop TX */
347 up->scc_char1 = 0x8000;
348 up->scc_char2 = 0x8000;
349 up->scc_char3 = 0x8000;
350 up->scc_char4 = 0x8000;
351 up->scc_char5 = 0x8000;
352 up->scc_char6 = 0x8000;
353 up->scc_char7 = 0x8000;
354 up->scc_char8 = 0x8000;
355 up->scc_rccm = 0xc0ff;
357 /* Set low latency / small fifo.
359 sp->scc_gsmrh = SCC_GSMRH_RFW;
363 sp->scc_gsmrl &= ~0xF;
364 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
366 /* Set local loopback mode.
368 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
369 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
371 /* Set clock divider 16 on Tx and Rx
373 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
375 sp->scc_psmr |= SCU_PSMR_CL;
377 /* Mask all interrupts and remove anything pending.
380 sp->scc_scce = 0xffff;
381 sp->scc_dsr = 0x7e7e;
382 sp->scc_psmr = 0x3000;
384 /* Make the first buffer the only buffer.
386 tbdf->cbd_sc |= BD_SC_WRAP;
387 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
389 /* Enable transmitter/receiver.
391 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
394 static void scc_halt(int scc_index)
396 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
397 volatile cpm8xx_t *cp = &(im->im_cpm);
398 volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
400 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
403 static void scc_putc (int scc_index, const char c)
405 volatile cbd_t *tbdf;
407 volatile scc_uart_t *up;
408 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
409 volatile cpm8xx_t *cpmp = &(im->im_cpm);
411 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
413 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
415 /* Wait for last character to go.
418 buf = (char *) tbdf->cbd_bufaddr;
421 while (tbdf->cbd_sc & BD_SC_READY)
426 tbdf->cbd_datlen = 1;
427 tbdf->cbd_sc |= BD_SC_READY;
430 while (tbdf->cbd_sc & BD_SC_READY)
435 static int scc_getc (int scc_index)
437 volatile cbd_t *rbdf;
438 volatile unsigned char *buf;
439 volatile scc_uart_t *up;
440 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
441 volatile cpm8xx_t *cpmp = &(im->im_cpm);
445 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
447 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
449 /* Wait for character to show up.
451 buf = (unsigned char *) rbdf->cbd_bufaddr;
453 while (rbdf->cbd_sc & BD_SC_EMPTY);
455 for (i = 100; i > 0; i--) {
456 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
465 rbdf->cbd_sc |= BD_SC_EMPTY;
474 static int test_ctlr (int ctlr, int index)
477 char test_str[] = "*** UART Test String ***\r\n";
480 ctlr_proc[ctlr].init (index);
482 for (i = 0; i < sizeof (test_str) - 1; i++) {
483 ctlr_proc[ctlr].putc (index, test_str[i]);
484 if (ctlr_proc[ctlr].getc (index) != test_str[i])
491 ctlr_proc[ctlr].halt (index);
494 post_log ("uart %s%d test failed\n",
495 ctlr_name[ctlr], index + 1);
501 int uart_post_test (int flags)
506 ctlr_proc[CTLR_SMC].init = smc_init;
507 ctlr_proc[CTLR_SMC].halt = smc_halt;
508 ctlr_proc[CTLR_SMC].putc = smc_putc;
509 ctlr_proc[CTLR_SMC].getc = smc_getc;
511 ctlr_proc[CTLR_SCC].init = scc_init;
512 ctlr_proc[CTLR_SCC].halt = scc_halt;
513 ctlr_proc[CTLR_SCC].putc = scc_putc;
514 ctlr_proc[CTLR_SCC].getc = scc_getc;
516 for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
517 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
522 #if !defined(CONFIG_8xx_CONS_NONE)
523 serial_reinit_all ();
529 #endif /* CONFIG_POST & CONFIG_SYS_POST_UART */