3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * The Ethernet Media Access Controllers (EMAC) are tested in the
32 * internal loopback mode.
33 * The controllers are configured accordingly and several packets
34 * are transmitted. The configurable test parameters are:
35 * MIN_PACKET_LENGTH - minimum size of packet to transmit
36 * MAX_PACKET_LENGTH - maximum size of packet to transmit
37 * TEST_NUM - number of tests
44 #if CONFIG_POST & CFG_POST_ETHER
46 #include <asm/cache.h>
48 #include <asm/processor.h>
50 #include <ppc4xx_enet.h>
53 DECLARE_GLOBAL_DATA_PTR;
56 * Get count of EMAC devices (doesn't have to be the max. possible number
57 * supported by the cpu)
59 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
60 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
61 * 405EX/405EXr eval board, using the same binary.
63 #if defined(CONFIG_BOARD_EMAC_COUNT)
64 #define LAST_EMAC_NUM board_emac_count()
65 #else /* CONFIG_BOARD_EMAC_COUNT */
66 #if defined(CONFIG_HAS_ETH3)
67 #define LAST_EMAC_NUM 4
68 #elif defined(CONFIG_HAS_ETH2)
69 #define LAST_EMAC_NUM 3
70 #elif defined(CONFIG_HAS_ETH1)
71 #define LAST_EMAC_NUM 2
73 #define LAST_EMAC_NUM 1
75 #endif /* CONFIG_BOARD_EMAC_COUNT */
77 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
78 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
81 #define MIN_PACKET_LENGTH 64
82 #define MAX_PACKET_LENGTH 256
85 static volatile mal_desc_t tx __cacheline_aligned;
86 static volatile mal_desc_t rx __cacheline_aligned;
90 int board_emac_count(void);
92 static void ether_post_init (int devnum, int hw_addr)
95 #if defined(CONFIG_440GX) || \
96 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
97 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
101 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
105 #if defined(CONFIG_440GX) || \
106 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
107 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
108 /* Need to get the OPB frequency so we can access the PHY */
109 get_sys_info (&sysinfo);
112 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
113 /* provide clocks for EMAC internal loopback */
114 mfsdr (sdr_mfr, mfr);
115 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
116 mtsdr (sdr_mfr, mfr);
120 out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
124 if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
127 printf ("Timeout resetting EMAC\n");
132 #if defined(CONFIG_440GX) || \
133 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
134 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
135 /* Whack the M1 register */
137 if (sysinfo.freqOPB <= 50000000);
138 else if (sysinfo.freqOPB <= 66666667)
139 mode_reg |= EMAC_M1_OBCI_66;
140 else if (sysinfo.freqOPB <= 83333333)
141 mode_reg |= EMAC_M1_OBCI_83;
142 else if (sysinfo.freqOPB <= 100000000)
143 mode_reg |= EMAC_M1_OBCI_100;
145 mode_reg |= EMAC_M1_OBCI_GT100;
147 out32 (EMAC_M1 + hw_addr, mode_reg);
149 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
151 /* set the Mal configuration reg */
152 #if defined(CONFIG_440GX) || \
153 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
154 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
155 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
156 MAL_CR_PLBLT_DEFAULT | 0x00330000);
158 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
159 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
160 if (get_pvr() == PVR_440GP_RB) {
161 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
164 /* setup buffer descriptors */
165 tx.ctrl = MAL_TX_CTRL_WRAP;
167 tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
169 rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
171 rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
175 /* setup MAL tx & rx channel pointers */
176 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
177 mtdcr (maltxctp2r, &tx);
179 mtdcr (maltxctp1r, &tx);
181 #if defined(CONFIG_440)
182 mtdcr (maltxbattr, 0x0);
183 mtdcr (malrxbattr, 0x0);
185 mtdcr (malrxctp1r, &rx);
186 /* set RX buffer size */
187 mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
191 /* setup MAL tx & rx channel pointers */
192 #if defined(CONFIG_440)
193 mtdcr (maltxbattr, 0x0);
194 mtdcr (malrxbattr, 0x0);
196 mtdcr (maltxctp0r, &tx);
197 mtdcr (malrxctp0r, &rx);
198 /* set RX buffer size */
199 mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
203 /* Enable MAL transmit and receive channels */
204 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
205 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
207 mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
209 mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
211 /* set internal loopback mode */
212 #ifdef CFG_POST_ETHER_EXT_LOOPBACK
213 out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
214 EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
215 EMAC_M1_MF_100MBPS | EMAC_M1_IST |
218 out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
219 EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
220 EMAC_M1_MF_100MBPS | EMAC_M1_IST |
224 /* set transmit enable & receive enable */
225 out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
227 /* enable broadcast address */
228 out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
230 /* set transmit request threshold register */
231 out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */
233 /* set receive low/high water mark register */
234 #if defined(CONFIG_440)
235 /* 440s has a 64 byte burst length */
236 out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
238 /* 405s have a 16 byte burst length */
239 out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
240 #endif /* defined(CONFIG_440) */
241 out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
243 /* Set fifo limit entry in tx mode 0 */
244 out32 (EMAC_TXM0 + hw_addr, 0x00000003);
246 out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
250 static void ether_post_halt (int devnum, int hw_addr)
253 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
257 /* 1st reset MAL channel */
258 /* Note: writing a 0 to a channel has no effect */
259 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
260 mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
262 mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
264 mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
267 while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
273 out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
275 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
276 /* remove clocks for EMAC internal loopback */
277 mfsdr (sdr_mfr, mfr);
278 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
279 mtsdr (sdr_mfr, mfr);
283 static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
287 while (tx.ctrl & MAL_TX_CTRL_READY) {
289 printf ("TX timeout\n");
294 tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
295 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
296 tx.data_len = length;
297 memcpy (tx.data_ptr, packet, length);
300 out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
304 static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
309 while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
311 printf ("RX timeout\n");
316 length = rx.data_len - 4;
317 if (length <= max_length)
318 memcpy(packet, rx.data_ptr, length);
321 rx.ctrl |= MAL_RX_CTRL_EMPTY;
331 static void packet_fill (char *packet, int length)
333 char c = (char) length;
336 /* set up ethernet header */
337 memset (packet, 0xff, 14);
339 for (i = 14; i < length; i++) {
344 static int packet_check (char *packet, int length)
346 char c = (char) length;
349 for (i = 14; i < length; i++) {
350 if (packet[i] != c++)
357 static int test_ctlr (int devnum, int hw_addr)
360 char packet_send[MAX_PACKET_LENGTH];
361 char packet_recv[MAX_PACKET_LENGTH];
366 ether_post_init (devnum, hw_addr);
368 for (i = 0; i < TEST_NUM; i++) {
369 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
370 packet_fill (packet_send, l);
372 ether_post_send (devnum, hw_addr, packet_send, l);
374 length = ether_post_recv (devnum, hw_addr, packet_recv,
375 sizeof (packet_recv));
377 if (length != l || packet_check (packet_recv, length) < 0) {
387 ether_post_halt (devnum, hw_addr);
390 post_log ("EMAC%d test failed\n", devnum);
396 int ether_post_test (int flags)
401 /* Allocate tx & rx packet buffers */
402 tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
403 rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
405 if (!tx_buf || !rx_buf) {
406 printf ("Failed to allocate packet buffers\n");
411 for (i = 0; i < LAST_EMAC_NUM; i++) {
412 if (test_ctlr (i, i*0x100))
423 #endif /* CONFIG_POST & CFG_POST_ETHER */
424 #endif /* CONFIG_POST */