3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * The controllers are configured to loopback mode and several
32 * characters are transmitted.
39 #if CONFIG_POST & CFG_POST_UART
42 * This table defines the UART's that should be tested and can
43 * be overridden in the board config file
45 #ifndef CFG_POST_UART_TABLE
46 #define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
49 #include <asm/processor.h>
52 #if defined(CONFIG_440)
53 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
54 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
55 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
56 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
57 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
58 #define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
60 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
61 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
64 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
65 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
68 #if defined(CONFIG_440GP)
69 #define CR0_MASK 0x3fff0000
70 #define CR0_EXTCLK_ENA 0x00600000
71 #define CR0_UDIV_POS 16
72 #define UDIV_SUBTRACT 1
73 #define UART0_SDR cntrl0
74 #define MFREG(a, d) d = mfdcr(a)
75 #define MTREG(a, d) mtdcr(a, d)
76 #else /* #if defined(CONFIG_440GP) */
77 /* all other 440 PPC's access clock divider via sdr register */
78 #define CR0_MASK 0xdfffffff
79 #define CR0_EXTCLK_ENA 0x00800000
80 #define CR0_UDIV_POS 0
81 #define UDIV_SUBTRACT 0
82 #define UART0_SDR sdr_uart0
83 #define UART1_SDR sdr_uart1
84 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
85 defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
86 defined(CONFIG_440SP) || defined(CONFIG_440SPe)
87 #define UART2_SDR sdr_uart2
89 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
90 defined(CONFIG_440GR) || defined(CONFIG_440GRx)
91 #define UART3_SDR sdr_uart3
93 #define MFREG(a, d) mfsdr(a, d)
94 #define MTREG(a, d) mtsdr(a, d)
95 #endif /* #if defined(CONFIG_440GP) */
96 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
97 #define UART0_BASE 0xef600300
98 #define UART1_BASE 0xef600400
99 #define UCR0_MASK 0x0000007f
100 #define UCR1_MASK 0x00007f00
101 #define UCR0_UDIV_POS 0
102 #define UCR1_UDIV_POS 8
104 #else /* CONFIG_405GP || CONFIG_405CR */
105 #define UART0_BASE 0xef600300
106 #define UART1_BASE 0xef600400
107 #define CR0_MASK 0x00001fff
108 #define CR0_EXTCLK_ENA 0x000000c0
109 #define CR0_UDIV_POS 1
113 #define UART_RBR 0x00
114 #define UART_THR 0x00
115 #define UART_IER 0x01
116 #define UART_IIR 0x02
117 #define UART_FCR 0x02
118 #define UART_LCR 0x03
119 #define UART_MCR 0x04
120 #define UART_LSR 0x05
121 #define UART_MSR 0x06
122 #define UART_SCR 0x07
123 #define UART_DLL 0x00
124 #define UART_DLM 0x01
127 * Line Status Register.
129 #define asyncLSRDataReady1 0x01
130 #define asyncLSROverrunError1 0x02
131 #define asyncLSRParityError1 0x04
132 #define asyncLSRFramingError1 0x08
133 #define asyncLSRBreakInterrupt1 0x10
134 #define asyncLSRTxHoldEmpty1 0x20
135 #define asyncLSRTxShiftEmpty1 0x40
136 #define asyncLSRRxFifoError1 0x80
138 DECLARE_GLOBAL_DATA_PTR;
141 #if !defined(CFG_EXT_SERIAL_CLOCK)
142 static void serial_divs (int baudrate, unsigned long *pudiv,
143 unsigned short *pbdiv)
146 unsigned long div; /* total divisor udiv * bdiv */
147 unsigned long umin; /* minimum udiv */
148 unsigned short diff; /* smallest diff */
149 unsigned long udiv; /* best udiv */
150 unsigned short idiff; /* current diff */
151 unsigned short ibdiv; /* current bdiv */
153 unsigned long est; /* current estimate */
155 get_sys_info(&sysinfo);
157 udiv = 32; /* Assume lowest possible serial clk */
158 div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
159 umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
160 diff = 32; /* highest possible */
162 /* i is the test udiv value -- start with the largest
163 * possible (32) to minimize serial clock and constrain
166 for (i = 32; i > umin; i--) {
169 idiff = (est > div) ? (est-div) : (div-est);
172 break; /* can't do better */
173 } else if (idiff < diff) {
174 udiv = i; /* best so far */
175 diff = idiff; /* update lowest diff*/
185 #if defined(CONFIG_440)
187 static int uart_post_init (unsigned long dev_base)
193 #ifdef CFG_EXT_SERIAL_CLOCK
198 for (i = 0; i < 3500; i++) {
199 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
203 MFREG(UART0_SDR, reg);
206 #ifdef CFG_EXT_SERIAL_CLOCK
207 reg |= CR0_EXTCLK_ENA;
209 tmp = gd->baudrate * 16;
210 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
212 /* For 440, the cpu clock is on divider chain A, UART on divider
213 * chain B ... so cpu clock is irrelevant. Get the "optimized"
214 * values that are subject to the 1/2 opb clock constraint
216 serial_divs (gd->baudrate, &udiv, &bdiv);
219 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
222 * Configure input clock to baudrate generator for all
223 * available serial ports here
225 MTREG(UART0_SDR, reg);
226 #if defined(UART1_SDR)
227 MTREG(UART1_SDR, reg);
229 #if defined(UART2_SDR)
230 MTREG(UART2_SDR, reg);
232 #if defined(UART3_SDR)
233 MTREG(UART3_SDR, reg);
236 out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
237 out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
238 out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
239 out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
240 out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
241 out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
242 val = in8(dev_base + UART_LSR); /* clear line status */
243 val = in8(dev_base + UART_RBR); /* read receive buffer */
244 out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
245 out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
250 #else /* CONFIG_440 */
252 static int uart_post_init (unsigned long dev_base)
262 for (i = 0; i < 3500; i++) {
263 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
268 #if defined(CONFIG_405EZ)
269 serial_divs(gd->baudrate, &udiv, &bdiv);
273 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
275 tmp = CFG_BASE_BAUD * 16;
276 udiv = (clk + tmp / 2) / tmp;
277 if (udiv > UDIV_MAX) /* max. n bits for udiv */
279 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
280 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
281 mtdcr (cpc0_ucr, reg);
282 #else /* CONFIG_405EP */
283 reg = mfdcr(cntrl0) & ~CR0_MASK;
284 #ifdef CFG_EXT_SERIAL_CLOCK
285 clk = CFG_EXT_SERIAL_CLOCK;
287 reg |= CR0_EXTCLK_ENA;
290 #ifdef CFG_405_UART_ERRATA_59
291 udiv = 31; /* Errata 59: stuck at 31 */
293 tmp = CFG_BASE_BAUD * 16;
294 udiv = (clk + tmp / 2) / tmp;
295 if (udiv > UDIV_MAX) /* max. n bits for udiv */
299 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
301 #endif /* CONFIG_405EP */
302 tmp = gd->baudrate * udiv * 16;
303 bdiv = (clk + tmp / 2) / tmp;
304 #endif /* CONFIG_405EZ */
306 out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
307 out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
308 out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
309 out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
310 out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
311 out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
312 val = in8(dev_base + UART_LSR); /* clear line status */
313 val = in8(dev_base + UART_RBR); /* read receive buffer */
314 out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
315 out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
319 #endif /* CONFIG_440 */
321 static void uart_post_putc (unsigned long dev_base, char c)
325 out8 (dev_base + UART_THR, c); /* put character out */
327 /* Wait for transfer completion */
328 for (i = 0; i < 3500; i++) {
329 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
335 static int uart_post_getc (unsigned long dev_base)
339 /* Wait for character available */
340 for (i = 0; i < 3500; i++) {
341 if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
345 return 0xff & in8 (dev_base + UART_RBR);
348 static int test_ctlr (unsigned long dev_base, int index)
351 char test_str[] = "*** UART Test String ***\r\n";
354 uart_post_init (dev_base);
356 for (i = 0; i < sizeof (test_str) - 1; i++) {
357 uart_post_putc (dev_base, test_str[i]);
358 if (uart_post_getc (dev_base) != test_str[i])
364 post_log ("uart%d test failed\n", index);
369 int uart_post_test (int flags)
372 static unsigned long base[] = CFG_POST_UART_TABLE;
374 for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
375 if (test_ctlr (base[i], i))
378 serial_reinit_all ();
383 #endif /* CONFIG_POST & CFG_POST_UART */
384 #endif /* CONFIG_POST */