3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * Condition register istructions: mtcr, mfcr, mcrxr,
29 * crand, crandc, cror, crorc, crxor,
30 * crnand, crnor, creqv, mcrf
32 * The mtcrf/mfcr instructions is tested by loading different
33 * values into the condition register (mtcrf), moving its value
34 * to a general-purpose register (mfcr) and comparing this value
35 * with the expected one.
36 * The mcrxr instruction is tested by loading a fixed value
37 * into the XER register (mtspr), moving XER value to the
38 * condition register (mcrxr), moving it to a general-purpose
39 * register (mfcr) and comparing the value of this register with
41 * The rest of instructions is tested by loading a fixed
42 * value into the condition register (mtcrf), executing each
43 * instruction several times to modify all 4-bit condition
44 * fields, moving the value of the conditional register to a
45 * general-purpose register (mfcr) and comparing it with the
52 #if CONFIG_POST & CONFIG_SYS_POST_CPU
54 extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
55 extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3);
57 static ulong cpu_post_cr_table1[] =
62 static unsigned int cpu_post_cr_size1 = ARRAY_SIZE(cpu_post_cr_table1);
64 static struct cpu_post_cr_s2 {
67 } cpu_post_cr_table2[] =
78 static unsigned int cpu_post_cr_size2 = ARRAY_SIZE(cpu_post_cr_table2);
80 static struct cpu_post_cr_s3 {
85 } cpu_post_cr_table3[] =
100 static unsigned int cpu_post_cr_size3 = ARRAY_SIZE(cpu_post_cr_table3);
102 static struct cpu_post_cr_s4 {
109 } cpu_post_cr_table4[] =
240 static unsigned int cpu_post_cr_size4 = ARRAY_SIZE(cpu_post_cr_table4);
242 int cpu_post_test_cr (void)
246 unsigned long cr_sav;
247 int flag = disable_interrupts();
249 asm ( "mfcr %0" : "=r" (cr_sav) : );
251 for (i = 0; i < cpu_post_cr_size1 && ret == 0; i++)
253 ulong cr = cpu_post_cr_table1[i];
256 unsigned long code[] =
263 cpu_post_exec_11 (code, &res, cr);
265 ret = res == cr ? 0 : -1;
269 post_log ("Error at cr1 test %d !\n", i);
273 for (i = 0; i < cpu_post_cr_size2 && ret == 0; i++)
275 struct cpu_post_cr_s2 *test = cpu_post_cr_table2 + i;
279 unsigned long code[] =
288 cpu_post_exec_21x (code, &res, &xer, test->xer);
290 ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ?
295 post_log ("Error at cr2 test %d !\n", i);
299 for (i = 0; i < cpu_post_cr_size3 && ret == 0; i++)
301 struct cpu_post_cr_s3 *test = cpu_post_cr_table3 + i;
304 unsigned long code[] =
307 ASM_MCRF(test->cd, test->cs),
312 cpu_post_exec_11 (code, &res, test->cr);
314 ret = res == test->res ? 0 : -1;
318 post_log ("Error at cr3 test %d !\n", i);
322 for (i = 0; i < cpu_post_cr_size4 && ret == 0; i++)
324 struct cpu_post_cr_s4 *test = cpu_post_cr_table4 + i;
327 unsigned long code[] =
330 ASM_12F(test->cmd, test->op3, test->op1, test->op2),
335 cpu_post_exec_11 (code, &res, test->cr);
337 ret = res == test->res ? 0 : -1;
341 post_log ("Error at cr4 test %d !\n", i);
345 asm ( "mtcr %0" : : "r" (cr_sav));