3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * Shift instructions: rlwnm
30 * The test contains a pre-built table of instructions, operands and
31 * expected results. For each table entry, the test will cyclically use
32 * different sets of operand registers and result registers.
38 #if CONFIG_POST & CONFIG_SYS_POST_CPU
40 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
42 extern ulong cpu_post_makecr (long v);
44 static struct cpu_post_rlwnm_s
52 } cpu_post_rlwnm_table[] =
63 static unsigned int cpu_post_rlwnm_size = ARRAY_SIZE(cpu_post_rlwnm_table);
65 int cpu_post_test_rlwnm (void)
69 int flag = disable_interrupts();
71 for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++)
73 struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i;
75 for (reg = 0; reg < 32 && ret == 0; reg++)
77 unsigned int reg0 = (reg + 0) % 32;
78 unsigned int reg1 = (reg + 1) % 32;
79 unsigned int reg2 = (reg + 2) % 32;
80 unsigned int stk = reg < 16 ? 31 : 15;
81 unsigned long code[] =
84 ASM_ADDI(stk, 1, -24),
87 ASM_STW(reg0, stk, 8),
88 ASM_STW(reg1, stk, 4),
89 ASM_STW(reg2, stk, 0),
90 ASM_LWZ(reg1, stk, 12),
91 ASM_LWZ(reg0, stk, 16),
92 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me),
93 ASM_STW(reg2, stk, 12),
94 ASM_LWZ(reg2, stk, 0),
95 ASM_LWZ(reg1, stk, 4),
96 ASM_LWZ(reg0, stk, 8),
102 unsigned long codecr[] =
105 ASM_ADDI(stk, 1, -24),
108 ASM_STW(reg0, stk, 8),
109 ASM_STW(reg1, stk, 4),
110 ASM_STW(reg2, stk, 0),
111 ASM_LWZ(reg1, stk, 12),
112 ASM_LWZ(reg0, stk, 16),
113 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) |
115 ASM_STW(reg2, stk, 12),
116 ASM_LWZ(reg2, stk, 0),
117 ASM_LWZ(reg1, stk, 4),
118 ASM_LWZ(reg0, stk, 8),
120 ASM_ADDI(1, stk, 24),
130 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
132 ret = res == test->res && cr == 0 ? 0 : -1;
136 post_log ("Error at rlwnm test %d !\n", i);
142 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
144 ret = res == test->res &&
145 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
149 post_log ("Error at rlwnm test %d !\n", i);