1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * Ternary instructions instr rA,rS,UIMM
13 * Logic instructions: ori, oris, xori, xoris
15 * The test contains a pre-built table of instructions, operands and
16 * expected results. For each table entry, the test will cyclically use
17 * different sets of operand registers and result registers.
23 #if CONFIG_POST & CONFIG_SYS_POST_CPU
25 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
26 extern ulong cpu_post_makecr (long v);
28 static struct cpu_post_threei_s
34 } cpu_post_threei_table[] =
61 static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
63 int cpu_post_test_threei (void)
67 int flag = disable_interrupts();
69 for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
71 struct cpu_post_threei_s *test = cpu_post_threei_table + i;
73 for (reg = 0; reg < 32 && ret == 0; reg++)
75 unsigned int reg0 = (reg + 0) % 32;
76 unsigned int reg1 = (reg + 1) % 32;
77 unsigned int stk = reg < 16 ? 31 : 15;
78 unsigned long code[] =
81 ASM_ADDI(stk, 1, -16),
83 ASM_STW(reg0, stk, 4),
84 ASM_STW(reg1, stk, 0),
85 ASM_LWZ(reg0, stk, 8),
86 ASM_11IX(test->cmd, reg1, reg0, test->op2),
87 ASM_STW(reg1, stk, 8),
88 ASM_LWZ(reg1, stk, 0),
89 ASM_LWZ(reg0, stk, 4),
99 cpu_post_exec_21 (code, & cr, & res, test->op1);
101 ret = res == test->res && cr == 0 ? 0 : -1;
105 post_log ("Error at threei test %d !\n", i);