3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * The Serial Management Controllers (SMC) and the Serial Communication
30 * Controllers (SCC) listed in ctlr_list array below are tested in
31 * the loopback UART mode.
32 * The controllers are configured accordingly and several characters
33 * are transmitted. The configurable test parameters are:
34 * MIN_PACKET_LENGTH - minimum size of packet to transmit
35 * MAX_PACKET_LENGTH - maximum size of packet to transmit
36 * TEST_NUM - number of tests
42 #if defined(CONFIG_8xx)
44 #elif defined(CONFIG_MPC8260)
45 #include <asm/cpm_8260.h>
47 #error "Apparently a bad configuration, please fix."
52 #if CONFIG_POST & CFG_POST_UART
57 /* The list of controllers to test */
58 #if defined(CONFIG_MPC823)
59 static int ctlr_list[][2] =
60 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
62 static int ctlr_list[][2] = { };
65 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
68 void (*init) (int index);
69 void (*putc) (int index, const char c);
70 int (*getc) (int index);
73 static char *ctlr_name[2] = { "SMC", "SCC" };
75 static int used_by_uart[2] = { -1, -1 };
76 static int used_by_ether[2] = { -1, -1 };
78 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
79 static int proff_scc[] =
80 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
86 static void smc_init (int smc_index)
88 DECLARE_GLOBAL_DATA_PTR;
90 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
92 volatile immap_t *im = (immap_t *) CFG_IMMR;
94 volatile smc_uart_t *up;
95 volatile cbd_t *tbdf, *rbdf;
96 volatile cpm8xx_t *cp = &(im->im_cpm);
99 /* initialize pointers to SMC */
101 sp = (smc_t *) & (cp->cp_smc[smc_index]);
102 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
104 /* Disable transmitter/receiver.
106 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
110 im->im_siu_conf.sc_sdcr = 1;
112 /* clear error conditions */
114 im->im_sdma.sdma_sdsr = CFG_SDSR;
116 im->im_sdma.sdma_sdsr = 0x83;
119 /* clear SDMA interrupt mask */
121 im->im_sdma.sdma_sdmr = CFG_SDMR;
123 im->im_sdma.sdma_sdmr = 0x00;
126 #if defined(CONFIG_FADS)
129 ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
132 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
133 /* Enable Monitor Port Transceiver */
134 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
137 /* Set the physical address of the host memory buffers in
138 * the buffer descriptors.
141 #ifdef CFG_ALLOC_DPRAM
142 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
144 dpaddr = CPM_POST_BASE;
147 /* Allocate space for two buffer descriptors in the DP ram.
148 * For now, this address seems OK, but it may have to
149 * change with newer versions of the firmware.
150 * damm: allocating space after the two buffers for rx/tx data
153 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
154 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
157 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
160 /* Set up the uart parameters in the parameter ram.
162 up->smc_rbase = dpaddr;
163 up->smc_tbase = dpaddr + sizeof (cbd_t);
164 up->smc_rfcr = SMC_EB;
165 up->smc_tfcr = SMC_EB;
167 #if defined(CONFIG_MBX)
168 board_serial_init ();
171 /* Set UART mode, 8 bit, no parity, one stop.
172 * Enable receive and transmit.
173 * Set local loopback mode.
175 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
177 /* Mask all interrupts and remove anything pending.
182 /* Set up the baud rate generator.
184 cp->cp_simode = 0x00000000;
187 (((gd->cpu_clk / 16 / gd->baudrate) -
188 1) << 1) | CPM_BRG_EN;
190 /* Make the first buffer the only buffer.
192 tbdf->cbd_sc |= BD_SC_WRAP;
193 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
195 /* Single character receive.
200 /* Initialize Tx/Rx parameters.
203 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
207 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
209 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
212 /* Enable transmitter/receiver.
214 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
217 static void smc_putc (int smc_index, const char c)
219 volatile cbd_t *tbdf;
221 volatile smc_uart_t *up;
222 volatile immap_t *im = (immap_t *) CFG_IMMR;
223 volatile cpm8xx_t *cpmp = &(im->im_cpm);
225 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
227 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
229 /* Wait for last character to go.
232 buf = (char *) tbdf->cbd_bufaddr;
235 while (tbdf->cbd_sc & BD_SC_READY)
240 tbdf->cbd_datlen = 1;
241 tbdf->cbd_sc |= BD_SC_READY;
244 while (tbdf->cbd_sc & BD_SC_READY)
249 static int smc_getc (int smc_index)
251 volatile cbd_t *rbdf;
252 volatile unsigned char *buf;
253 volatile smc_uart_t *up;
254 volatile immap_t *im = (immap_t *) CFG_IMMR;
255 volatile cpm8xx_t *cpmp = &(im->im_cpm);
259 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
261 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
263 /* Wait for character to show up.
265 buf = (unsigned char *) rbdf->cbd_bufaddr;
267 while (rbdf->cbd_sc & BD_SC_EMPTY);
269 for (i = 100; i > 0; i--) {
270 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
279 rbdf->cbd_sc |= BD_SC_EMPTY;
288 static void scc_init (int scc_index)
290 DECLARE_GLOBAL_DATA_PTR;
292 static int cpm_cr_ch[] = {
299 volatile immap_t *im = (immap_t *) CFG_IMMR;
301 volatile scc_uart_t *up;
302 volatile cbd_t *tbdf, *rbdf;
303 volatile cpm8xx_t *cp = &(im->im_cpm);
306 /* initialize pointers to SCC */
308 sp = (scc_t *) & (cp->cp_scc[scc_index]);
309 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
311 /* Disable transmitter/receiver.
313 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
316 /* Allocate space for two buffer descriptors in the DP ram.
319 #ifdef CFG_ALLOC_DPRAM
320 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
322 dpaddr = CPM_POST_BASE;
327 im->im_siu_conf.sc_sdcr = 0x0001;
329 /* Set the physical address of the host memory buffers in
330 * the buffer descriptors.
333 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
334 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
337 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
340 /* Set up the baud rate generator.
342 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
343 /* no |= needed, since BRG1 is 000 */
346 (((gd->cpu_clk / 16 / gd->baudrate) -
347 1) << 1) | CPM_BRG_EN;
349 /* Set up the uart parameters in the parameter ram.
351 up->scc_genscc.scc_rbase = dpaddr;
352 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
354 /* Initialize Tx/Rx parameters.
356 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
359 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
361 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
364 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
365 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
367 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
368 up->scc_maxidl = 0; /* disable max idle */
369 up->scc_brkcr = 1; /* send one break character on stop TX */
377 up->scc_char1 = 0x8000;
378 up->scc_char2 = 0x8000;
379 up->scc_char3 = 0x8000;
380 up->scc_char4 = 0x8000;
381 up->scc_char5 = 0x8000;
382 up->scc_char6 = 0x8000;
383 up->scc_char7 = 0x8000;
384 up->scc_char8 = 0x8000;
385 up->scc_rccm = 0xc0ff;
387 /* Set low latency / small fifo.
389 sp->scc_gsmrh = SCC_GSMRH_RFW;
393 sp->scc_gsmrl &= ~0xF;
394 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
396 /* Set local loopback mode.
398 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
399 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
401 /* Set clock divider 16 on Tx and Rx
403 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
405 sp->scc_psmr |= SCU_PSMR_CL;
407 /* Mask all interrupts and remove anything pending.
410 sp->scc_scce = 0xffff;
411 sp->scc_dsr = 0x7e7e;
412 sp->scc_psmr = 0x3000;
414 /* Make the first buffer the only buffer.
416 tbdf->cbd_sc |= BD_SC_WRAP;
417 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
419 /* Enable transmitter/receiver.
421 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
424 static void scc_putc (int scc_index, const char c)
426 volatile cbd_t *tbdf;
428 volatile scc_uart_t *up;
429 volatile immap_t *im = (immap_t *) CFG_IMMR;
430 volatile cpm8xx_t *cpmp = &(im->im_cpm);
432 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
434 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
436 /* Wait for last character to go.
439 buf = (char *) tbdf->cbd_bufaddr;
442 while (tbdf->cbd_sc & BD_SC_READY)
447 tbdf->cbd_datlen = 1;
448 tbdf->cbd_sc |= BD_SC_READY;
451 while (tbdf->cbd_sc & BD_SC_READY)
456 static int scc_getc (int scc_index)
458 volatile cbd_t *rbdf;
459 volatile unsigned char *buf;
460 volatile scc_uart_t *up;
461 volatile immap_t *im = (immap_t *) CFG_IMMR;
462 volatile cpm8xx_t *cpmp = &(im->im_cpm);
466 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
468 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
470 /* Wait for character to show up.
472 buf = (unsigned char *) rbdf->cbd_bufaddr;
474 while (rbdf->cbd_sc & BD_SC_EMPTY);
476 for (i = 100; i > 0; i--) {
477 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
486 rbdf->cbd_sc |= BD_SC_EMPTY;
495 static int test_ctlr (int ctlr, int index)
498 char test_str[] = "*** UART Test String ***\r\n";
501 #if !defined(CONFIG_8xx_CONS_NONE)
502 if (used_by_uart[ctlr] == index) {
503 while (ctlr_proc[ctlr].getc (index) != -1);
507 ctlr_proc[ctlr].init (index);
509 for (i = 0; i < sizeof (test_str) - 1; i++) {
510 ctlr_proc[ctlr].putc (index, test_str[i]);
511 if (ctlr_proc[ctlr].getc (index) != test_str[i])
519 #if !defined(CONFIG_8xx_CONS_NONE)
520 if (used_by_uart[ctlr] == index) {
525 #if defined(SCC_ENET)
526 if (used_by_ether[ctlr] == index) {
527 DECLARE_GLOBAL_DATA_PTR;
534 post_log ("uart %s%d test failed\n",
535 ctlr_name[ctlr], index + 1);
541 int uart_post_test (int flags)
546 #if defined(CONFIG_8xx_CONS_SMC1)
547 used_by_uart[CTLR_SMC] = 0;
548 #elif defined(CONFIG_8xx_CONS_SMC2)
549 used_by_uart[CTLR_SMC] = 1;
550 #elif defined(CONFIG_8xx_CONS_SCC1)
551 used_by_uart[CTLR_SCC] = 0;
552 #elif defined(CONFIG_8xx_CONS_SCC2)
553 used_by_uart[CTLR_SCC] = 1;
554 #elif defined(CONFIG_8xx_CONS_SCC3)
555 used_by_uart[CTLR_SCC] = 2;
556 #elif defined(CONFIG_8xx_CONS_SCC4)
557 used_by_uart[CTLR_SCC] = 3;
560 #if defined(SCC_ENET)
561 used_by_ether[CTLR_SCC] = SCC_ENET;
564 ctlr_proc[CTLR_SMC].init = smc_init;
565 ctlr_proc[CTLR_SMC].putc = smc_putc;
566 ctlr_proc[CTLR_SMC].getc = smc_getc;
568 ctlr_proc[CTLR_SCC].init = scc_init;
569 ctlr_proc[CTLR_SCC].putc = scc_putc;
570 ctlr_proc[CTLR_SCC].getc = scc_getc;
572 for (i = 0; i < CTRL_LIST_SIZE; i++) {
573 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
581 #endif /* CONFIG_POST & CFG_POST_UART */
583 #endif /* CONFIG_POST */