git.sur5r.net Git - cc65/blob - src/ca65/instr.h

   1 /*****************************************************************************/
   2 /*                                                                           */
   3 /*                                  instr.h                                  */
   4 /*                                                                           */
   5 /*             Instruction encoding for the ca65 macroassembler              */
   6 /*                                                                           */
   7 /*                                                                           */
   8 /*                                                                           */
   9 /* (C) 1998-2012, Ullrich von Bassewitz                                      */
  10 /*                Roemerstrasse 52                                           */
  11 /*                D-70794 Filderstadt                                        */
  12 /* EMail:         uz@cc65.org                                                */
  13 /*                                                                           */
  14 /*                                                                           */
  15 /* This software is provided 'as-is', without any expressed or implied       */
  16 /* warranty.  In no event will the authors be held liable for any damages    */
  17 /* arising from the use of this software.                                    */
  18 /*                                                                           */
  19 /* Permission is granted to anyone to use this software for any purpose,     */
  20 /* including commercial applications, and to alter it and redistribute it    */
  21 /* freely, subject to the following restrictions:                            */
  22 /*                                                                           */
  23 /* 1. The origin of this software must not be misrepresented; you must not   */
  24 /*    claim that you wrote the original software. If you use this software   */
  25 /*    in a product, an acknowledgment in the product documentation would be  */
  26 /*    appreciated but is not required.                                       */
  27 /* 2. Altered source versions must be plainly marked as such, and must not   */
  28 /*    be misrepresented as being the original software.                      */
  29 /* 3. This notice may not be removed or altered from any source              */
  30 /*    distribution.                                                          */
  31 /*                                                                           */
  32 /*****************************************************************************/
  33
  34
  35
  36 #ifndef INSTR_H
  37 #define INSTR_H
  38
  39
  40
  41 /* common */
  42 #include "cpu.h"
  43 #include "strbuf.h"
  44
  45
  46
  47 /*****************************************************************************/
  48 /*                       Data for 6502 and successors                        */
  49 /*****************************************************************************/
  50
  51
  52
  53 /* Constants for the addressing mode. If an opcode is available in zero page
  54 ** and absolut adressing mode, both bits are set. When checking for valid
  55 ** modes, the zeropage bit is checked first. Similar, the implicit bit is set
  56 ** on accu adressing modes, so the 'A' for accu adressing is not needed (but
  57 ** may be specified).
  58 ** When assembling for the 6502 or 65C02, all addressing modes that are not
  59 ** available on these CPUs are removed before doing any checks.
  60 */
  61 #define AM65_IMPLICIT           0x00000003UL
  62 #define AM65_ACCU               0x00000002UL
  63 #define AM65_DIR                0x00000004UL
  64 #define AM65_ABS                0x00000008UL
  65 #define AM65_ABS_LONG           0x00000010UL
  66 #define AM65_DIR_X              0x00000020UL
  67 #define AM65_ABS_X              0x00000040UL
  68 #define AM65_ABS_LONG_X         0x00000080UL
  69 #define AM65_DIR_Y              0x00000100UL
  70 #define AM65_ABS_Y              0x00000200UL
  71 #define AM65_DIR_IND            0x00000400UL
  72 #define AM65_ABS_IND            0x00000800UL
  73 #define AM65_DIR_IND_LONG       0x00001000UL
  74 #define AM65_DIR_IND_Y          0x00002000UL
  75 #define AM65_DIR_IND_LONG_Y     0x00004000UL
  76 #define AM65_DIR_X_IND          0x00008000UL
  77 #define AM65_ABS_X_IND          0x00010000UL
  78 #define AM65_REL                0x00020000UL
  79 #define AM65_REL_LONG           0x00040000UL
  80 #define AM65_STACK_REL          0x00080000UL
  81 #define AM65_STACK_REL_IND_Y    0x00100000UL
  82 #define AM65_IMM_ACCU           0x00200000UL
  83 #define AM65_IMM_INDEX          0x00400000UL
  84 #define AM65_IMM_IMPLICIT       0x00800000UL
  85 #define AM65_BLOCKMOVE          0x01000000UL
  86 #define AM65_BLOCKXFER          0x02000000UL
  87 #define AM65_ABS_IND_LONG       0x04000000UL
  88 #define AM65_IMM_IMPLICIT_WORD  0x08000000UL /* PHW #$1234 (4510 only) */
  89
  90 /* Bitmask for all ZP operations that have correspondent ABS ops */
  91 #define AM65_SET_ZP     (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
  92
  93 /* Bitmask for all ABS operations that have correspondent FAR ops */
  94 #define AM65_SET_ABS    (AM65_ABS | AM65_ABS_X)
  95
  96 /* Bitmask for all ZP operations */
  97 #define AM65_ALL_ZP     (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
  98
  99 /* Bitmask for all ABS operations */
 100 #define AM65_ALL_ABS    (AM65_ABS | AM65_ABS_X | AM65_ABS_Y | AM65_ABS_IND | AM65_ABS_X_IND)
 101
 102 /* Bitmask for all FAR operations */
 103 #define AM65_ALL_FAR    (AM65_ABS_LONG | AM65_ABS_LONG_X)
 104
 105 /* Bitmask for all immediate operations */
 106 #define AM65_ALL_IMM    (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD)
 107
 108 /* Bit numbers and count */
 109 #define AM65I_IMM_ACCU          21
 110 #define AM65I_IMM_INDEX         22
 111 #define AM65I_IMM_IMPLICIT      23
 112 #define AM65I_IMM_IMPLICIT_WORD 27
 113 #define AM65I_COUNT             28
 114
 115
 116
 117 /* Description for one instruction */
 118 typedef struct InsDesc InsDesc;
 119 struct InsDesc {
 120     char                Mnemonic[5];
 121     unsigned long       AddrMode;               /* Valid adressing modes */
 122     unsigned char       BaseCode;               /* Base opcode */
 123     unsigned char       ExtCode;                /* Number of ext code table */
 124     void                (*Emit) (const InsDesc*);/* Handler function */
 125 };
 126
 127 /* An instruction table */
 128 typedef struct InsTable InsTable;
 129 struct InsTable {
 130     unsigned            Count;                  /* Number of intstructions */
 131     InsDesc             Ins[1];                 /* Varying length */
 132 };
 133
 134 /* The instruction table for the currently active CPU */
 135 extern const InsTable* InsTab;
 136
 137 /* Table that encodes the additional bytes for each instruction */
 138 extern unsigned char ExtBytes[AM65I_COUNT];
 139
 140
 141
 142 /*****************************************************************************/
 143 /*                      Data for the SWEET16 pseudo CPU                      */
 144 /*****************************************************************************/
 145
 146
 147
 148 /* SWEET16 addressing modes */
 149 #define AMSW16_IMP      0x0001          /* Implicit */
 150 #define AMSW16_BRA      0x0002          /* A branch */
 151 #define AMSW16_IMM      0x0004          /* Immediate */
 152 #define AMSW16_IND      0x0008          /* Indirect */
 153 #define AMSW16_REG      0x0010          /* Register */
 154
 155 #define AMSW16I_COUNT   5               /* Number of addressing modes */
 156
 157
 158
 159 /*****************************************************************************/
 160 /*                                   Code                                    */
 161 /*****************************************************************************/
 162
 163
 164
 165 void SetCPU (cpu_t NewCPU);
 166 /* Set a new CPU */
 167
 168 cpu_t GetCPU (void);
 169 /* Return the current CPU */
 170
 171 int FindInstruction (const StrBuf* Ident);
 172 /* Check if Ident is a valid mnemonic. If so, return the index in the
 173 ** instruction table. If not, return -1.
 174 */
 175
 176 void HandleInstruction (unsigned Index);
 177 /* Handle the mnemonic with the given index */
 178
 179
 180
 181 /* End of instr.h */
 182
 183 #endif